Cypress CY25566 User Manual
Spread Spectrum Clock Generator
CY25566
Features
• 25- to 200-MHz operating frequency range
• Wide range of spread selections (9)
• Accepts clock or crystal inputs
• Provides four clocks
—SSCLK1a
—SSCLK1b
—SSCLK2
—REFOUT
• Low-power dissipation
—3.3V = 70 mW (typical @ 40 MHz, no load)
Block Diagram
300K
Xin/
CLK
Xout
VDD
VSS
VSS
VSS
1
16
4
5
11
14
10
SSCC
REFERENCE
MODULA TION
20 K
DIVIDER
CONTROL
INPUT
DECODER
LOGIC
13
12
S0S1
• Center spread modulation
• Low cycle-to cycle jitter
• 16-pin SOIC package
Applications
• High-resolution VGA controllers
• LCD panels and monitors
• Printers and MFPs
Benefits
• Peak EMI reduction by 8 to 16 dB
• Fast time to market
• Cost reduction
Pin Configuration
REFOFF
2
15
14
13
12
11
10
98
XOUT
SSCLK2
VSS
S0
S1
VSS
SSCC
SSCLK1b
3
REFOUT
DIVIDER
&
MUX
Loop
Filter
vco
/2
SSCLK1a
8
915SSCLK1b
SSCLK2
PD
CP
FEEDBACK
DIVIDER
VDDVDD
20 K
RANGE
CONTROL
20 K20 K
VSSVSS
6
7
S3S2
XIN/ CLKIN
SSCLK1a
116
REFOFF
2
REFOUT
3
VDD
4
VSS
5
S2
6
S3
7
CY25566
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07429 Rev. *B Revised October 26, 2005
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CY25566
Pin Description
Pin Name Type Description
1 XIN/CLKIN I Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input
frequency range selection.
2REFOFFIInput pin enables REFOUT clock at pin 3. REFO FF 400K Ω internal pull-up resistor.
Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled.
3REFOUTOBuffered, non-modulated output clock derived from XIN/CLKIN input frequency.
4VDDPPositive power supply. Bypass to ground with 0.1-µF capacitor.
5, 11, 14 VSS G Positive power supply ground.
6S2IVCO range control. Refer to Table 1, Table 2, and Table 3 for detailed programming infor-
7S3IVCO range control. Refer to Table 1, Table 2, and Table 3 for detailed programming infor-
8 SSCLK1a O Modulated clock output . Pins 8 and 9 are identical but separate drivers.
9 SSCLK1b O Modulated clock output . Pins 8 and 9 are identical but separate drivers.
10 SSCC I Spread Spectrum clock control (enable/disable) function. SSCG function is enabled
12 S1 I Tri-level logic input control pin used to select frequency and bandwidth.
13 S0 I Tri-level logic input control pin used to select frequency and bandwidth.
15 SSCLK2 O Modulated output clock. Frequency of SSCLK2 = SSCLK1a/2. BW% of SSCLK2 is equal
16 XOUT O Oscillator output pin connected to crystal. Leave this pin unconnected if an external
There is a 180° phase shift from XIN to REFOUT.
mation. Has 400-KΩ internal pull-up to V
mation. Has 400-KΩ internal pull-up to V
DD
DD
.
.
when input is high and disabled when input is low. Internal 400-KΩ pull-up defaults to
modulation ON.
Frequency/bandwidth selection and tri-level logic programming details. See Figure 2 and
Table 1, Table 2, and Table 3. Pin 8 has internal resistor divider network to V
DD
Frequency/bandwidth selection and tri-level logic programming details. See Figure 2 and
Table 1, Table 2, and Table 3. Pin 8 has internal resistor divider network to V
DD
to BW% of SSCLK1a/b.
clock drives XIN/CLK.
and VSS.
and VSS.
General Description
The Cypress CY25566 is a Spread S pectrum Clock Generator
(SSCG) IC used for the purpose of reducing electromagnetic
interference (EMI) found in today’s high-speed digital
electronic systems.
The CY25566 uses a Cypress-proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
digital clock. By frequency modulating the clock, (SSCLK1a/b
and SSCLK2), the measured EMI at the fundamental and
harmonic frequencies is greatly reduced. The modulated
output frequency is centered on the input frequency.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements and
improve time to market without degrading system performance.
The CY25566 provides four output clocks: SSCLK1a,
SSCLK1b, SSCLK2, and REFOUT. SSCLK1a/b and SSCLK2
are modulated clocks and REFOUT is a buffered copy of the
reference clock or oscillator. The CY25566 frequency and
spread % ranges are selected by programming S0, S1, S2,
and S3 digital inputs. S0 and S1 use three (3) logic states
including High (H), Low (L), and Middle (M) to select one of
nine available frequency and spread % ranges. Refer to
Figure 2 for details on programming three level inputs S0 and
S1. See Table 1, Table 2, and Table 3 for programming details
for S2 and S3.
The CY25566 will operate over a wide range of frequencies
from 25 to 200 MHz. Operation to 200 MHz is possible with the
use of dual drivers at pins 8 and 9. With a wide range of
selectable bandwidths, the CY25566 is a very flexible low-EMI
clock. Modulation can be disabled to provide a four-output
conventional clock.
The CY25566 is available in a 16-pin SOIC (150-mil.) package
with a commercial operating temperature range of 0°C to
70°C.
Output Clock Architecture
The CY25566 provides four separate output clocks: REFOUT ,
SSCLK1a, SSCLK1b, and SSCLK2 for use in a wide variety of
applications. Each clock output is described below in detail.
REFOUT
REFOUT is a 3.3V CMOS level non-modulated inverted copy
of the clock at XIN/CLKIN. As an inverted clock, the output
clock at REFOUT is 180° out of phase with the input clock at
XIN/CLKIN. Placing a high(1) logic state of REFOFF , pin 2, will
disable the REFOUT clock. When REFOUT is disabled,
REFOUT, pin 3 is at a low(0) logic state.
Document #: 38-07429 Rev. *B Page 2 of 9
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CY25566
SSCLK1a/b
SSCLK1a and SSCLK1b are spread spectrum clock outputs
used for the purpose of reducing EMI in digital systems.
SSCLK1a and SSCLK1b can be connected in several different
ways to provide flexibility in application designs. Each clock
can drive separate nets with a capacitative load up to 15 pF
each or connected together to provide drive to a single net with
a capacitative load as high as 33 pF. When both clocks are
connected together, the CY25566 is capable of driving 3.3V
CMOS-compatible clocks to frequencies as high as 200 MHz.
If one clock output is not connected to a load, negligible EMI
will be generated at the unused pin because there is no current
being driven. The frequency and bandwidth of SSCLK1a and
SSCLK1b is programmed by the logic states presented to S2
and S3. The frequency multiplication at SSCLK1a and
SSCLK1b is either 1X or 2X, controlled by S2 and S3. The
modulated output clock SSCLK1 is provided at pins 8 and 9
with each pin having separate but identical drivers. Refer to
Figure 1 below .
CY25566
CY25566
9
8
9
8
33 pf.
15 pf.
15 pf.
Figure 1. SSCLK1a/b Driver Configurations
SSCLK2
SCLK2 is a Spread S pectrum Clock with a frequency half that
of the SSCLK1a clock frequency. When SSCLK1a is
programmed to provide a 2.5% modulated clock at 1X times
the reference clock, 40 MHz for example, the frequency of
SSCLK2 will be 20 MHz with a BW of 2.5%. Note that by
programming the frequency of SSCLK1a to 2X, the frequency
of SSCLK2 will be 1X times the reference clock frequency.
CY25566
Control Logic Structures
The CY25566 has six input control pins for programming VCO
range, BW %, Mod ON/OFF and REFOUT ON/OFF. These
programmable control pins are described below.
REFOFF
The output clock REFOUT can be enabled or disabled by
controlling the state of REFOFF. When REFOFF is at a logic
low(0) state, REFOUT is enabled and the reference clock
frequency is present at pin 3. When REFOFF is at a logic high
state (1), REFOUT is disabled and is set to a logic low state
on pin 3. REFOFF has a 400-KW internal pull-up resistor to
V
.
DD
S0 and S1 (Tri-level Inputs)
S0 and S1 are used to program the frequency range and
bandwidth of the modulated output clocks SSCLK1a/b and
SSCLK2. S0 and S1 of the CY25566 are designed to sense
three different analog levels. With this tri-level structure, the
CY25566 is able to detect 9 different logic states. Refer to
tables 5, 6 and 7 for the results of each of these 9 states. The
level of each state is defined as follows:
Logic State “0” is a voltage that is between 0 and 0.15 × V
Logic State “M” is a volt age between 0.4 × V
Logic State “1” is a voltage between 0.85 × V
and 0.6 × VDDV.
DD
and VDD.
DD
DD
Figure 2 illustrates how to program tri-level logic.
S2 and S3
S2 and S3 are used to program the CY25566 into different
frequency ranges and multipliers. The CY25566 operates over
a frequency range of 25 to 200 MHz and a 1X or 2X multipli cation of the reference frequency. S2 and S3 are binary logic
inputs and each has a 400 K W pull-up resistor to V
Table 1, Table 2, and Table 3 for programming details.
DD
. See
SSCC
SSCC is an input control pin that enable s or disables SSCG
modulation of the output clock at SSCLK1a/b and SSCLK2.
Disabling modulation is a method of comparing radiated EMI
in a product with SSCG turned on or off.
The CY25566 can be used as a conventional low jitter multiple
output clock when SSCC is set to low (0). SSCC has a 400-KW
internal pull-up resistor. Logic high (1) = Mo du l a ti on ON, logic
low (0) = Modulation OFF. Default is modulation ON.
VDD VDD
CY25566CY25566
V.
S0 = "M" (N/C)
S1 = "0" (GND)
SSCC = "1"
S0
13
S1
12
VDD
10
S0 = "1" S0 = "1"
S1 = "0" (GND)
SSCC = "1"
S1
12
VDD
10 10
S1 = "1"
SSCC = "1"
S0S0
1313
S1
12
Figure 2.
Document #: 38-07429 Rev. *B Page 3 of 9
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