Page 1
CY24713
Set-top Box Clock Generator with VCXO
Features
Logic Block Diagram
Note
1. Float X
OUT
if XIN is externally driven.
Benefits
■ Integrated phase-locked loop (PLL)
■ Low-jitter, high-accuracy outputs
■ VCXO with analog adjust
■ 3.3V Operation
■ 8-pin SOIC
■ High-performance PLL tailored for Set Top Box applications
■ Meets critical timing requirements in complex system designs
■ Large ±150-ppm range, better linearity
■ Meet industry standard voltage platforms
■ Industry standard packaging saves on board space
Part Number Outputs Input Frequency Range Output Frequencies
CY24713 3 27-MHz pullable crystal input
4.9152 MHz, 13.5 MHz, 27 MHz
per Cypress specification
Pin Configuration
Table 1. Pin Definition
Name Number Description
XIN 1 Reference Crystal Input
VDD 2 3.3V Voltage Supply
VCXO 3 Input Analog Control for VCXO
VSS 4 Ground
CLK_B 5 13.5-MHz Clock Output
CLK_A 6 4.9152-MHz Clock Output
CLK_C 7 27-MHz Clock Output
[1]
XOUT
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07396 Rev. *A Revised May 22, 2008
Figure 1. CY24713, 8-Pin SOIC
8 Reference Crystal Output
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CY24713
Absolute Maximum Conditions
Note
2. Rated for 10 years
Parameter Description Min Max Unit
V
DD
T
S
T
J
Supply Voltage –0.5 7.0 V
Storage Temperature
[2]
–65 125 °C
Junction Temperature – 125 °C
Digital Inputs V
Digital Outputs referred to V
DD
– 0.3 VDD + 0.3 V
SS
VSS – 0.3 VDD + 0.3 V
Electrostatic Discharge – 2000 V
Analog Input –0.5 7.0 V
Pullable Crystal Specifications
Parameter Description Condition Min Typ. Max Unit
F
C
R
R
NOM
LNOM
1
3/R1
Nominal crystal frequency Parallel resonance, funda-
–27–MHz
mental mode, AT cut
Nominal load capacitance – 14 – pF
Equivalent series resistance (ESR) Fundamental mode – – 25 Ω
Ratio of third overtone mode ESR to fundamen-
tal mode ESR
Ratio used because typica l R1
values are much less than the
3––
maximum spec.
DL Crystal drive level No external series resistor as-
–0.52.0mW
sumed
F
3SEPHI
F
3SEPLO
C
0
C
0/C1
C
1
Third overtone separation from 3*F
Third overtone separation from 3*F
NOM
NOM
High side 300 – – ppm
Low side – – –150 ppm
Crystal shunt capacitance – – 7 pF
Ratio of shunt to motional capacitance 180 – 250
Crystal motional capacitance 14.4 18 21.6 pF
Recommended Operating Conditions
V
DD
T
A
C
LOAD
t
PU
DC Electrical Characteristics
Parameter Description Conditions Min Typ. Max Unit
I
OH
I
OL
C
IN
I
IZ
f
ΔXO
V
VCXO
I
VDD
Document #: 38-07396 Rev. *A Page 2 of 5
Parameter Description Min Typ. Max Unit
Operating Voltage 3.135 3.3 3.465 V
Ambient Temperature 0 – 70 °C
Max. Load Capacitance – – 15 pF
Power up time for all VDDs to reach minimum specified voltage (power
0.05 – 500 ms
ramps must be monotonic)
Output High Current VOH = VDD – 0.5, V
Output Low Current VOL = 0.5, V
DD
= 3.3V 12 24 – mA
DD
= 3.3V 12 24 – mA
Input Capacitance – – 7 pF
Input Leakage Current – 5 – μA
VCXO pullability range ±150 – – ppm
VCXO input range 0 – V
DD
V
Supply Current – 25 30 mA
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CY24713
AC Electrical Characteristics (V
0.1 μF
V
DD
CLK out
C
LOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
Figure 3. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 4. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3, EF = 0.6 x VDD/t4
Note
3. Not 100% tested
Parameter
[3]
Description Conditions Min Typ. Max Unit
= 3.3V)
DD
DC Output Duty Cycle Duty Cycle is defined in Figure 3 50% of V
ER
EF
t
9
t
10
0
1
Rising Edge Rate Output Clock Edge Rate, Measured from 20% to
80% of
VDD, CLOAD
= 15 pF Figure 4.
Falling Edge Rate Output Clock Edge Rate, Measured from 80% to
20% of
VDD, CLOAD
= 15 pF Figure 4.
Clock Jitter Peak-Peak period jitter maximum absolute jitter – 200 250 ps
PLL Lock Time – – 3 ms
Figure 2. Test Circuit
DD
45 50 55 %
0.8 1.4 – V/ns
0.8 1.4 – V/ns
Document #: 38-07396 Rev. *A Page 3 of 5
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CY24713
Ordering Information
SEATING PLANE
PIN1ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
0°~8°
0.016[0.406]
0.010[0.254]
X 45°
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
14
58
3. REFERENCE JEDEC MS-012
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
4. PACKAGE WEIGHT 0.07gms
51-85066 *C
Note
4. Not recommended for new designs.
Ordering Code Package Type Operating Range Operating Voltage
CY24713SC
CY24713SCT
[4]
[4]
8-pin SOIC Commercial 3.3V
8-pin SOIC Commercial 3.3V
Pb-free
CY24713SXC
CY24713SXCT
[4]
8-pin SOIC Commercial 3.3V
[4]
8-pin SOIC-Tape and Reel Commercial 3.3V
CY24713KSXC 8-pin SOIC Commercial 3.3V
CY24713KSXCT 8-pin SOIC-Tape and Reel Commercial 3.3V
Package Diagram
Figure 5. 8-Lead (150-Mil) SOIC S8
Document #: 38-07396 Rev. *A Page 4 of 5
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CY24713
Document History Page
Document Title: CY24713 Set-top Box Clock Generator with VCXO
Document Number: 38-07396
REV. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 333175 RGL See ECN New Data Sheet
*A 2440886 AESA See ECN Updated template. Added Note “Not recommended for new designs.”
Added part number CY24713KSXC, and CY24713KSXCT in ordering information table.
Replaced Lead-Free with Pb-Free.
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Document #: 38-07396 Rev. *A Revised May 22, 2008 Page 5 of 5
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