CYPRESS CY23S08 User Manual

CY23S08

3.3V Zero Delay Buffer

Logic Block Diagram

REF

CLKA1
CLKA2
CLKA3
CLKA4

FBK

PLL

MUX

Select Input

Decoding

S2

S1

CLKB1
CLKB2
CLKB3
CLKB4

/2

Extra Divider (–2, –2H, –3)

/2

Extra Divider (–3, –4)

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Features

■ Zero input-output propagation delay, adjustable by capacitive

load on FBK input

■ Multiple configurations, see Table 3 on page 3

■ Multiple low-skew outputs
❐ 45 ps typical output-output skew(–1)
❐ Two banks of four outputs, three-stateable by two select in-

puts

■ 10 MHz to 133 MHz operating range

■ 65 ps typical cycle-cycle jitter (–1, –1H)

■ Advanced 0.65μ CMOS technology

■ Space saving 16-pin 150-mil SOIC/TSSOP packages

■ 3.3V operation

■ Spread Aware™

Functional Description

The CY23S08 is a 3.3V zero delay buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.

The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback must be driven into
the FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less th an
350 ps, and output-to-output skew is guaranteed to be less than
250 ps.

The CY23S08 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in Table 2 on page 3. If
all output clocks are not required, Bank B can be three-stated.
The select inputs also allow the input clock to be directly applied
to the output for chip and system testing purposes.

The CY23S08 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50 μA of current draw. The PLL shuts down in two additional
cases as shown in Table 2 on page 3.

Multiple CY23S08 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.

The CY23S08 is available in five different configurations, as
shown in Ta ble 3 on page 3. The CY23S08–1 is the base part,
where the output frequencies equal the reference if there is no
counter in the feedback path. The CY23S08–1H is the high-drive
version of the –1, and rise and fall times on this device are much
faster.

The CY23S08–2 enables the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the feedback
pin. The CY23S08–2H is the high-drive version of the –2, and
rise and fall times on this device are much faster.

The CY23S08–3 enables the user to obtain 4X and 2X
frequencies on the outputs.

The CY23S08–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile, and can be used
in a variety of applications.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07265 Rev. *G Revised September 05, 2007

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CY23S08

Pinouts

9

16

FBK
CLKA4

CLKA3
V

DD

GND
CLKB4
CLKB3
S1

1
2
3
4
5
6
7
8

10

11

12

13

14

15

REF

CLKA1
CLKA2

V

DD

GND
CLKB1
CLKB2

S2

Top View

SOIC

Notes

1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.

2. Weak pull down.

3. Weak pull down on all outputs.

4. Weak pull ups on these inputs.

Figure 1. Pin Diagram - 16 Pin SOIC Package

Table 1. Pin Definition - 16 Pin SOIC Package

Pin Signal Description

DD

DD

[2]

[3]
[3]

Input reference frequency, 5V tolerant input
Clock output, Bank A
Clock output, Bank A

3.3V supply

[3]

[3]
[4]
[4]

[3]

[3]

Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B

3.3V supply

[3]

[3]

Clock output, Bank A
Clock output, Bank A

1REF
2 CLKA1
3 CLKA2
4V
5 GND Ground
6 CLKB1
7 CLKB2
8S2

9S1
10 CLKB3
1 1 CLKB4
12 GND Ground
13 V
14 CLKA3
15 CLKA4
16 FBK PLL feedback input

Document #: 38-07265 Rev. *G Page 2 of 10

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CY23S08

Table 2. Select Input Decoding

S2 S1 CLOCK A1–A4 CLOCK B1–B4 Output Source PLL Shutdown

0 0 Three-State Three-S tate PLL Y

0 1 Driven Three-State PLL N

1 0 Driven Driven Reference Y

1 1 Driven Driven PLL N

Table 3. Available CY23S08 Configurations

Device Feedback From Bank A Frequency Ba nk B Frequency

CY23S08–1 Bank A or Bank B Reference Reference
CY23S08–1H Bank A or Bank B Reference Reference
CY23S08–2 Bank A Reference Reference/2
CY23S08–2H Bank A Reference Reference/2
CY23S08–2 Bank B 2 X Reference Reference
CY23S08–2H Bank B 2 X Reference Reference
CY23S08–3 Bank A 2 X Reference Reference or Reference
CY23S08–3 Bank B 4 X Reference 2 X Reference
CY23S08–4 Bank A or Bank B 2 X Reference 2 X Reference

[1]

Spread Aware

Many systems being designed now utilize a technology calle d Spread Spectrum Frequency Timing Generation. Cypress has been
one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant
amount of tracking skew which may cause problems in systems requiring synchronization.

For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with
Spread Spectrum Frequency Timing Generator (SSFTG) ICs.

Document #: 38-07265 Rev. *G Page 3 of 10

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