Cypress CY22392 User Manual
r
1CY2295
FLASH Programmable Clock Generato
Features
• Three integrated phase-locked loops
• Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit
Post Divide)
• Improved Linear Crystal Load capacitors
• Flash programmability
• Field programmable
• Low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Configurable Crystal drive strength
• Frequency Select via 3 external LVTTL Inputs
• 3.3V operation
• 16-pin TSSOP packages
• CyClocksRT™ Support
Benefits
• Generates up to 3 unique frequencies on 6 outputs up
to 200 MHz from an external source. Functional
upgrade for current CY2292 family.
• Allows for 0 ppm Frequency Generation and Frequency
Conversion under the most demanding applications.
• Improves frequency accuracy over temperature, age,
process, and initial offset.
CY22392
Three-PLL General Purpose
• Non-Volatile programming enables easy customization, ultra-fast turnaround, performance tweaking,
design timing margin testing, inventory control, lower
part count, and more secure product supply. In
addition, any part in the family can also be programmed
multiple times which reduces programming errors and
provides an easy upgrade path for existing designs.
• In-house programming of samples and prototype
quantities is available using the CY3672 FTG Development Kit. Production quantities are available through
Cypress Semiconductor’s value added Distribution
partners or by using third party programmers from BP
Microsystems, HiLo Systems, and others.
• Performance suitable for high-end multimedia, communications, industrial, A/D Converters, and consumer
applications.
• Supports numerous low-power application schemes
and reduces EMI by allowing unused outputs to be
turned off.
• Adjust Crystal Drive Strength for compatibility with
virtually all crystals.
• 3-Bit External Frequency Select Options for PLL1,
CLKA, and CLKB.
• Industry-standard supply voltage.
• Industry-standard packaging saves on board space.
• Easy to use software support for design entry.
Logic Block Diagram
XTALIN
XTALOUT
CONFIGURATION
SHUTDOWN
S2/SUSPEND
/OE
S0
S1
OSC.
FLASH
PLL1
11 BIT P
8 BIT Q
PLL2
11 BIT P
8 BIT Q
PLL3
11 BIT P
8 BIT Q
4x4
Crosspoint
Switch
Divider
/2,3, or 4
Divider
7 BIT
Divider
7 BIT
Divider
7 BIT
Divider
7 BIT
XBUF
CLKE
CLKD
CLKC
CLKB
CLKA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07013 Rev. *D Revised June 22, 2004
CY22392
Pin Configuration
CY22392
16-pin TSSOP
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN/OE
S2/SUSPEND
AV
DD
S1
S0
GND
CLKA
CLKB
Selector Guide
Part Number Outputs Input Frequency Range Output Frequency Range Specifics
CY22392FC 6 8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
CY22392FI 6 8 MHz–30 MHz (external crystal)
1 MHz–150 MHz (reference clock)
Up to 200 MHz Commercial Temperature
Up to 166 MHz Industrial Temperature
Pin Description
Name Pin Number Description
CLKC 1 Configurable clock output C
V
DD
AGND 3 Analog Ground
XTALIN 4 Reference crystal input or external reference clock input
XTALOUT 5 Reference crystal feedback
XBUF 6 Buffered reference clock output
CLKD 7 Configurable clock output D
CLKE 8 Configurable clock output E
CLKB 9 Configurable clock output B
CLKA 10 Configurable clock output A
GND 11 Ground
S0 12 General Purpose Input for Frequency Control; bit 0
S1 13 General Purpose Input for Frequency Control; bit 1
AV
DD
S2/
SUSPEND
SHUTDOWN/OE 16 Places outputs in three-state condition and shuts down chip when LOW. Optionally,
2 Power supply
14 Analog Power Supply
15 General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control
input.
only places outputs in tristate condition and does not shut down chip when LOW
Document #: 38-07013 Rev. *D Page 2 of 8
CY22392
Operation
The CY22392 is an upgrade to the existing CY2292. The new
device has a wider frequency range, greater flexibility,
improved performance, and incorporates many features that
reduce PLL sensitivity to external system issues.
The device has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The output of PLL1 is also sent to a
/2, /3, or /4 synchronous post-divider that is output through
CLKE. The frequency of PLL1 can be changed by external
CMOS inputs, S0, S1, S2. See the following section on
General-Purpose Inputs for more details.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
General-Purpose Inputs
S0, S1, and S2 are general-purpose inputs that can be
programmed to allow for eight different frequency settings.
Options that may be switched with these general purpose
inputs are as follows; the frequency of PLL1, the output divider
of CLKB, and the output divider of CLKA.
CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.
For example: the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed via a programmable crosspoint
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. In
addition, many outputs have a unique capability for even
greater flexibility. The following is a description of each output.
CLKA’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
S2 controls which of the two programmable registers is loaded
into CLKA’s 7-bit post divider. See the section
“General-Purpose Inputs” for more information.
CLKB’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
and S2 controls which of the two programmable registers is
loaded into CLKA’s 7-bit post divider. See the section
“General-Purpose” Inputs for more information.
CLKC’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
XBUF is simply the buffered reference.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Power Saving Features
The SHUTDOWN
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, the reference oscillator, and
all other active components. The resulting current on the V
pins will be less than 5 µA (typical). After leaving shutdown
mode, the PLLs will have to relock.
The S2/SUSPEND
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.
/OE input three-states the outputs when
DD
input can be configured to shut down a
Document #: 38-07013 Rev. *D Page 3 of 8
Loading...