Cypress CY22392 User Manual

r

1CY2295

FLASH Programmable Clock Generato

Features

• Three integrated phase-locked loops

• Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit
Post Divide)

• Improved Linear Crystal Load capacitors

• Flash programmability

• Field programmable

• Low-jitter, high-accuracy outputs

• Power-management options (Shutdown, OE, Suspend)

• Configurable Crystal drive strength

• Frequency Select via 3 external LVTTL Inputs

• 3.3V operation

• 16-pin TSSOP packages

• CyClocksRT™ Support

Benefits

• Generates up to 3 unique frequencies on 6 outputs up
to 200 MHz from an external source. Functional
upgrade for current CY2292 family.

• Allows for 0 ppm Frequency Generation and Frequency
Conversion under the most demanding applications.

• Improves frequency accuracy over temperature, age,
process, and initial offset.

CY22392

Three-PLL General Purpose

• Non-Volatile programming enables easy customi­zation, ultra-fast turnaround, performance tweaking,
design timing margin testing, inventory control, lower
part count, and more secure product supply. In
addition, any part in the family can also be programmed
multiple times which reduces programming errors and
provides an easy upgrade path for existing designs.

• In-house programming of samples and prototype
quantities is available using the CY3672 FTG Devel­opment Kit. Production quantities are available through
Cypress Semiconductor’s value added Distribution
partners or by using third party programmers from BP
Microsystems, HiLo Systems, and others.

• Performance suitable for high-end multimedia, commu­nications, industrial, A/D Converters, and consumer
applications.

• Supports numerous low-power application schemes
and reduces EMI by allowing unused outputs to be
turned off.

• Adjust Crystal Drive Strength for compatibility with
virtually all crystals.

• 3-Bit External Frequency Select Options for PLL1,
CLKA, and CLKB.

• Industry-standard supply voltage.

• Industry-standard packaging saves on board space.

• Easy to use software support for design entry.

Logic Block Diagram

XTALIN

XTALOUT

CONFIGURATION

SHUTDOWN

S2/SUSPEND

/OE

S0

S1

OSC.

FLASH

PLL1

11 BIT P

8 BIT Q

PLL2

11 BIT P

8 BIT Q

PLL3

11 BIT P

8 BIT Q

4x4

Crosspoint

Switch

Divider
/2,3, or 4

Divider

7 BIT

Divider

7 BIT

Divider

7 BIT

Divider

7 BIT

XBUF

CLKE

CLKD

CLKC

CLKB

CLKA

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07013 Rev. *D Revised June 22, 2004

CY22392

Pin Configuration

CY22392

16-pin TSSOP

CLKC

V

DD

AGND

XTALIN

XTALOUT

XBUF

CLKD

CLKE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SHUTDOWN/OE

S2/SUSPEND

AV

DD

S1

S0

GND

CLKA

CLKB

Selector Guide

Part Number Outputs Input Frequency Range Output Frequency Range Specifics

CY22392FC 6 8 MHz–30 MHz (external crystal)

1 MHz–166 MHz (reference clock)

CY22392FI 6 8 MHz–30 MHz (external crystal)

1 MHz–150 MHz (reference clock)

Up to 200 MHz Commercial Temperature

Up to 166 MHz Industrial Temperature

Pin Description

Name Pin Number Description

CLKC 1 Configurable clock output C

V

DD

AGND 3 Analog Ground

XTALIN 4 Reference crystal input or external reference clock input

XTALOUT 5 Reference crystal feedback

XBUF 6 Buffered reference clock output

CLKD 7 Configurable clock output D

CLKE 8 Configurable clock output E

CLKB 9 Configurable clock output B

CLKA 10 Configurable clock output A

GND 11 Ground

S0 12 General Purpose Input for Frequency Control; bit 0

S1 13 General Purpose Input for Frequency Control; bit 1

AV

DD

S2/
SUSPEND

SHUTDOWN/OE 16 Places outputs in three-state condition and shuts down chip when LOW. Optionally,

2 Power supply

14 Analog Power Supply

15 General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control

input.

only places outputs in tristate condition and does not shut down chip when LOW

Document #: 38-07013 Rev. *D Page 2 of 8

CY22392

Operation

The CY22392 is an upgrade to the existing CY2292. The new
device has a wider frequency range, greater flexibility,
improved performance, and incorporates many features that
reduce PLL sensitivity to external system issues.

The device has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.

Configurable PLLs

PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The output of PLL1 is also sent to a
/2, /3, or /4 synchronous post-divider that is output through
CLKE. The frequency of PLL1 can be changed by external
CMOS inputs, S0, S1, S2. See the following section on
General-Purpose Inputs for more details.

PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.

PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.

General-Purpose Inputs

S0, S1, and S2 are general-purpose inputs that can be
programmed to allow for eight different frequency settings.
Options that may be switched with these general purpose
inputs are as follows; the frequency of PLL1, the output divider
of CLKB, and the output divider of CLKA.

CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.

For example: the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.

Crystal Input

The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.

The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.

The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.

The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.

For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.

Output Configuration

Under normal operation there are four internal frequency
sources that may be routed via a programmable crosspoint
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. In
addition, many outputs have a unique capability for even
greater flexibility. The following is a description of each output.

CLKA’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
S2 controls which of the two programmable registers is loaded
into CLKA’s 7-bit post divider. See the section
“General-Purpose Inputs” for more information.

CLKB’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
and S2 controls which of the two programmable registers is
loaded into CLKA’s 7-bit post divider. See the section
“General-Purpose” Inputs for more information.

CLKC’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.

CLKD’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.

CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.

XBUF is simply the buffered reference.

The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.

Power Saving Features

The SHUTDOWN
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, the reference oscillator, and
all other active components. The resulting current on the V
pins will be less than 5 µA (typical). After leaving shutdown
mode, the PLLs will have to relock.

The S2/SUSPEND
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combi­nation. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.

/OE input three-states the outputs when

DD

input can be configured to shut down a

Document #: 38-07013 Rev. *D Page 3 of 8

CY22392

Improving Jitter

Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.

Power Supply Sequencing

For parts with multiple V
sequencing requirements. The part will not be fully operational

pins, there are no power supply

DD

until all VDD pins have been brought up to the voltages
specified in the “Operating Conditions” table.

All grounds should be connected to the same ground plane.

CyClocksRT™ Software

CyClocksRT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows
you to see the power consumption of your specific configu­ration. You can download a copy of CyClocksRT for free on
Cypress’s web site at www.cypress.com.

Operating Conditions

[1]

Junction Temperature Limitations

It is possible to program the CY22392 such that the maximum
Junction Temperature rating is exceeded. The package θ
115 C/W. Use the CyClocksRT power estimation feature to

JA

is

verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Supply Voltage ...............................................–0.5V to +7.0V

DC Input Voltage ............................–0.5V to + (AV

Storage Temperature ................................. –65°C to +125°C

Junction Temperature...................................................125°C

Data Retention @ Tj = 125°C.................................>10 years

Maximum Programming Cycles .......................................100

Package Power Dissipation...................................... 350 mW

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ..........................................

2000V

Latch up (per JEDEC 17) .................................... >

+ 0.5V)

DD

±200 mA

Parameter Description Min. Typ. Max. Unit

VDD/AV

T

A

DD

Supply Voltage 3.135 3.3 3.465 V

Commercial Operating Temperature, Ambient 0 – +70 °C

Industrial Operating Temperature, Ambient –40 – +85 °C

C

LOAD_OUT

f

REF

t

PU

Notes:

1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.

2. External input reference clock must have a duty cycle between 40% and 60%, measured at V

Max. Load Capacitance – – 15 pF

External Reference Crystal 8 – 30 MHz

External Reference Clock

External Reference Clock

Power-up time for all VDD's to reach minimum specified voltage

[2]

, Commercial 1 – 166 MHz

[2]

, Industrial 1 – 150 MHz

0.05 – 500 ms

(power ramps must be monotonic)

/2.

DD

Document #: 38-07013 Rev. *D Page 4 of 8

CY22392

Electrical Characteristics

Parameter Description Conditions Min. Typ. Max. Unit

I

OH

I

OL

C

XTAL_MIN

C

XTAL_MAX

C

LOAD_IN

V

IH

V

IL

I

IH

I

IL

I

OZ

I

DD

I

DDS

Output High Current

Output Low Current

Crystal Load Capacitance

Crystal Load Capacitance

Input Pin Capacitance

HIGH-Level Input Voltage CMOS levels,% of AV

LOW-Level Input Voltage CMOS levels,% of AV

Input HIGH Current VIN=AVDD–0.3V – <1 10 µA

Input LOW Current VIN=+0.3V – <1 10 µA

Output Leakage Current Three-state outputs – 10 µA

Total Power Supply Current 3.3V Power Supply; 2 outputs @

Total Power Supply Current in
Shutdown Mode

[3]

[3]

[3]

VOH=VDD– 0.5, VDD=3.3V 12 24 – mA

VOL=0.5V, VDD=3.3V 12 24 – mA

[3]

Capload at minimum setting – 6 – pF

[3]

Capload at maximum setting – 30 – pF

Except crystal pins – 7 – pF

DD

DD

70% – – AV

– – 30% AV

– 100 – mA

166 MHz; 4 outputs @ 83 MHz

3.3V Power Supply; 2 outputs @

– 50 – mA

20 MHz; 4 outputs @ 40 MHz

Shutdown active – 5 20 µA

DD

DD

Switching Characteristics

Parameter Name Description Min. Typ. Max. Unit

[3, 6]

[3, 4]

[3, 5]

Clock output limit, Commercial – – 200 MHz

Clock output limit, Industrial – – 166 MHz

Duty cycle for outputs, defined as t2÷ t1,
Fout < 100 MHz, divider >= 2, measured at V

Duty cycle for outputs, defined as t
Fout > 100 MHz or divider = 1, measured at V

[3]

Output clock rise time, 20% to 80% of V

Output clock fall time, 20% to 80% of V

2

÷ t1,

DD

DD

Time for output to enter or leave three-state mode
after SHUTDOWN

/OE switches

Peak-to-peak period jitter, CLK outputs measured
at V

/2

DD

45% 50% 55%

/2

DD

40% 50% 60%

/2

DD

0.75 1.4 – V/ns

0.75 1.4 – V/ns

– 150 300 ns

–400–ps

PLL Lock Time from Power-up – 1.0 3 ms

1/t

1

t

2

t

3

t

4

t

5

t

6

t

7

Notes:

3. Guaranteed by design, not 100% tested.

4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.

5. Reference Output duty cycle depends on XTALIN duty cycle.

6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.

Output Frequency

Output Duty Cycle

Rising Edge Slew Rate

Falling Edge Slew

[3]

Rate

Output three-state

[3]

Timing

Clock Jitter

Lock Time

[3]

Document #: 38-07013 Rev. *D Page 5 of 8

Switching Waveforms

All Outputs, Duty Cycle and Rise/Fall Time

t

2

OUTPUT

t

1

CY22392

t

3

Output Three-State Timing

OE

THREE-STATE

ALL

OUTPUTS

CLK Output Jitter

CLK

OUTPUT

Frequency Change

SELECT

OUTPUT

OLD SELECT NEW SELECT STABLE

F

old

t

4

t

5

t

6

t

7

F

new

t

5

Test Circuit

AV

DD

0.1 µF

V

DD

0.1 µF

Document #: 38-07013 Rev. *D Page 6 of 8

OUTPUTS

GND

CLK out

C

LOAD

CY22392

Ordering Information

Ordering Code Package Name Package Type Operating Range Operating Voltage

CY22392FC Z16 16-TSSOP Commercial (T

CY22392FI Z16 16-TSSOP Industrial (T

CY22392ZC-xxx

CY22392ZI-xxx

[7]

[7]

Z16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V

Z16 16-TSSOP Industrial (TA = –40°C to 85°C) 3.3V

= 0°C to 70°C) 3.3V

A

= –40°C to 85°C) 3.3V

A

CY3672 FTG Development Kit

Lead Free

CY22392FXC Z16 16-TSSOP Commercial (T

CY22392FXI Z16 16-TSSOP Industrial (T

CY22392ZXC-xxx

CY22392ZXI-xxx

Note:

7. The CY22392ZC-xxx and CY22392ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.

[7]

[7]

Z16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V

Z16 16-TSSOP Industrial (TA = –40°C to 85°C) 3.3V

= 0°C to 70°C) 3.3V

A

= –40°C to 85°C) 3.3V

A

Package Diagram

0.65[0.025]

0.85[0.033]

0.95[0.037]

BSC.

4.90[0.193]

5.10[0.200]

1

4.30[0.169]

4.50[0.177]

16

0.19[0.007]

0.30[0.012]

0.05[0.002]

0.15[0.006]

16-lead TSSOP 4.40 MM Body Z16.173

PIN1ID

DIMENSIONS IN MM[INCHES] MIN.

REFERENCE JEDEC MO-153

6.25[0.246]

6.50[0.256]

PACKAGE WEIGHT 0.05 gms

Z16.173 STANDARD PKG.

ZZ16.173 LEAD FREE PKG.

0.25[0.010]

GAUGE
PLANE

BSC

0°-8°

1.10[0.043] MAX.

0.076[0.003]

SEATING
PLANE

PART #

0.50[0.020]

0.70[0.027]

MAX.

0.09[[0.003]

0.20[0.008]

CyClocksRT is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.

Document #: 38-07013 Rev. *D Page 7 of 8

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges

51-85091-*A

CY22392

Document History Page

Document Title: CY22392 Three PLL General Purpose Flash Programmable Clock Generator
Document Number: 38-07013

REV. ECN NO.

** 106738 07/03/01 TLG New Data Sheet

*A 108515 08/23/01 JWK Updates based on characterization results. Removed “Preliminary” heading.

*B 110052 12/09/01 CKN Preliminary to Final.

*C 121864 12/14/02 RBI Power up requirements added to Operating Conditions Information

*D 237811 See ECN RGL Added Lead Free Devices

Issue
Date

Orig. of
Change Description of Change

Added paragraph on Junction Temperature limitations and part configura­tions. Removed soldering temperature rating. Split crystal load into two typical
specs representing digital settings range. Changed t
Changed t

typical to 1.0 ms.

7

max to 300 ns.

5

Document #: 38-07013 Rev. *D Page 8 of 8