Cypress CY2048WAF User Manual

CY2048WAF

Flash Programmable Capacitor Tuning Array Die

for Crystal Oscillator(XO)

Features

• Flash-programmable capacitor tuning array for low
ppm initial frequency clock output

• Low clock output jitter
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter

• Flash-programmable dividers

• Two-pin programming interface

• On-chip os cillator runs from 10–48-MHz crystal

• Five selectable post-divide options, using reference
oscillator output

• Programmable asynchronous or synchronous OE and
PWR_DWN modes

• 2.7V to 3.6V operation

• Controlled rise and fall times and output slew rate

Block Diagram

PD#/OE

(SDATA/VPP)

XIN

XOUT

CRYSTAL

OSCILLATOR

Benefits

• Enables fine-tuning of output clock frequency by
adjusting C

• Allows multiple programming opportunities to correct
errors, and control excess inventory

• Enables programming of output frequency after
packaging

• PPM clock output err or can be adjusted in package

• Provides flexibility in output configurations and testing

• Enables low-power operation or output enable function

• Provides flexibility for system applications through
selectable instantaneous or synchronous change in
outputs

• Enables encapsulation in small-size, surface-mount
packages

of the crystal

Load

CONFIGURATION

/ 1, 2, 4, 8, 16

VDD

VSS

OUT
(SCL)

Die Pad Description

Horizontal Scribe

1

2

3

4

VDD

XOUT

XIN

PD#/OE

Y (max)

7C80330A

X(max)

OUT

VSS

6

5

Vertical
Scribe

die#/rev

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-07738 Rev. *A Revised December 12, 2005

Notes:

X(max): 980 µm, Y(max): 988 µm
Scribe: X = 70 µm, Y = 86 µm
Bond pad opening: 85 µm x 85 µm

Pad pitch: 175 µm (min.)

Wafer thickness: 11 mils (T yp.)

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CY2048WAF

Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0))

Name Pad Number Description X coordinate (µm) Y coordinate (µm)

VDD 1 Voltage Supply –360.8 353.7
XOUT 2 Oscillator Drain –360.8 134.1
XIN 3 Oscillator Gate –360.8 –42.6
PD#/OE 4 Programmable power-down or output enable pin –360.8 –275.9
VPP High voltage for programming NV memory
SDATA Serial data pin used for programming in test mode
OUT 6 Clock output 360.0 353.7
SCL Serial clock for programming in te st mode
VSS 5 Ground 360.0 –354.5

Document #: 38-07738 Rev. *A Page 2 of 7

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CY2048WAF

Absolute Maximum Conditions

(Above which the useful life may be impaired.
For user guidelines, not tested.)

Supply Voltage (V

DC Input Voltage......................................–0.5V to V

Crystal Specifications

).................................. ......–0.5 to +7.0V

DD

[1]

DD

+ 0.5

Output Short Circuit Current.....................................± 50 mA

Storage Temperature (Non-condensing) .... –55°C to +125°C

Junction Temperature................................ –40°C to +125°C

Data Retention @ Tj = 125°C................................> 10 years

ESD (Human Body Model) MIL-STD-883.................> 2000V

Parameter Description Comments Min. Typ. Max. Unit

F
R
R

C
C

NOM

1
3/R1

0
1

Nominal crystal frequency Fundamental mode, AT cut 10 – 48 MHz
Equivalent series resistance (ESR) Fundamental mode – – 40 Ω
Ratio of third overtone mode ESR to

fundamental mode ESR

Ratio used because typical R1 values are
much less than the maximum spec

4.5 – – –

Crystal shunt capacitance – – 5 pF
Crystal motional capacitance 2 – – fF

Operating Conditions

Parameter Description Min. Typ. Max. Unit

V

DD

T

J

C

XIN

C

XOUT

C

L

C

OUT

t

RAMP

T

S

Operating Voltage 2.7 – 3.6 V
Junction Temperature –40 – 125 °C
Capacitance XIN, all tuning caps OFF – 10 – pF
Capacitance XOUT, all tuning caps OFF – 10 – pF
All tuning Caps OFF 4 5 6 pF
All tuning Caps ON 9.2 10 11.4 pF
Output Load Capacitance – – 15 pF
Power-up time for VDD to reach minimum specified

0.05 – 500 ms

voltage (power ramps must be monotonic)
Start up time, 90% VDD to valid frequency on output – – 10 ms

DC Electrical Specifications TJ = –40 to 125°C over the operating range

Parameter Description Condition Min. Typ. Max. Unit

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OZL

I

OZH

I

DD

I

PD

R

UP

R

DN

C

IN

R

F

Note:

1. Not 100% tested.

Input Low Voltage CMOS Levels – – 20 %VDD
Input High Voltage CMOS Levels 80 – – %VDD
Output Low Voltage VDD = 2.7V–3.6V, IOL = 8 mA – – 0.4 V
Output High Voltage VDD = 2.7V–3.6V, IOL = –8 mA VDD–0.4 – – V
Input Low Current Input = V
Input High Current Input = V
Output Leakage Current Output = V
Output Leakage Current Output = V

SS
DD

SS
DD

–110µA
–110µA
–110µA

––50µA
Power Supply Current No Load, VDD = 3.3V, 48 MHz – – 20 mA
Power Down Current PD# = 0V – – 25 µA
Input Pull-up resistor VIN = VSS 136MΩ

V

Output Pull-down resistor V

> = 0.8V

IN

= 0.5V

IN

DD

DD

80 120 150 kΩ

500 900 1500 kΩ
Input Pin Capacitance PD#/OE pin – – 7 pF
Crystal Feedback R XIN = 0 300 – 800 kΩ

Document #: 38-07738 Rev. *A Page 3 of 7

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