Cypress CY14E256L User Manual

CY14E256L

256 Kbit (32K x 8) nvSRAM

Features

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

Quantum Trap

512 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

OE

CE

WE

HSB

V

CC

V

CAP

A

13

-

A

0

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

■

25 ns, 35 ns, and 45 ns access times

■

Pin compatible with STK14C88

■

Hands off automatic STORE on power down with external 68
µF capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited READ, WRITE, and RECALL cycles

■

1,000,000 STORE cycles to QuantumTrap

■

100 year data retention to QuantumTrap

■

Single 5V+10% operation

■

Commercial and industrial temperature

■

32-pin SOIC and CDIP (300 mil) packages

■

RoHS compliance

Functional Description

The Cypress CY14E256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB

pin.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06968 Rev. *F Revised January 30, 2009

[+] Feedback

CY14E256L

Pin Configurations

Figure 1. Pin Diagram: 32-Pin SOIC/DIP

Pin Definitions

Pin Name Alt IO Type Description

A

DQ

0–A14

-DQ

0

WE

CE
OE

V

SS

V

CC

HSB

V

CAP

7

W

E
G

Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-06968 Rev. *F Page 2 of 18

[+] Feedback

CY14E256L

Device Operation

The CY14E256L nvSRAM is made up of two functional compo­nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14E256L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera­tions from the nonvolatile cells and up to one million STORE
operations.

SRAM Read

The CY14E256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until

determines the 32,768 data bytes accessed. When

0–14

(READ cycle 1). If the READ is initiated

or OE, the outputs are valid at t

AA

or at t

ACE

access time without the need for

AA

, whichever

DOE

another address change or until CE or OE is brought HIGH, or
WE

or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB
the WRITE cycle and must remain stable until either CE

or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE

are written into the memory if it has valid tSD, before

0–7

controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE
LOW, inte rnal circuitry turns off the output buffers t
goes LOW.

HZWE

is left

after WE

AutoStore Operation

The CY14E256L stores data to nvSRAM using one of three
storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.

During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V

pin drops below V

CC

pin from VCC. A STORE

CAP

pin. This stored

CAP

SWITCH

CAP

Figure 2 shows the proper connection of the storage capacitor

) for automatic store operation. A charge storage capacitor

(V

CAP

to

CC

, the part

capacitor.

having a capacitor of between 68uF and 220uF (+
6V should be provided. The voltage on the V
5V by a charge pump internal to the chip. A pull up is placed on
WE

to hold it inactive during power up.

20%) rated at

pin is driven to

CAP

Figure 2. AutoStore Mode

In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the

CC

and V

are connected to the

CAP

AutoStore function of the CY14E256L operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE

cycle.

does not drop below 3.6V during the 10 ms

CC

To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB

signal is monitored by the system to detect if an

AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc

reaches V
between V
of current between V

, then a 2.2 ohm resistor should be connected

SWITCH

and the system supply to avoid momentary excess

CC

CC

and V

CAP

.

AutoStore Inhibit mode

If an automatic STORE on power loss is not required, then V
is tied to ground and + 5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is

(Figure 3). This is

CAP

disabled. If the CY14E256L is operated in this configuration,
references to V
sheet. In this mode, STORE
software control or the HSB

are changed to V

CC

operations are triggered through

pin. To enable or disable Autostore

throughout this data

CAP

using an I/O port pin see “” on page 5. It is not permissible to
change between these three options” on the fly”.

CC

.

Document Number: 001-06968 Rev. *F Page 3 of 18

[+] Feedback

CY14E256L

Figure 3. AutoStore Inhibit Mode

Hardware STORE (HSB) Operation

The CY14E256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB

pin is used to

pin is driven
LOW, the CY14E256L conditionally initiates a STORE operation
after t
the SRAM takes place since the last STORE or RECALL cycle.

. An actual STORE cycle only begins if a WRITE to

DELAY

The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. Pull up this pi n with an
external 10K ohm resistor to V

if HSB is used as a driver.

CAP

SRAM READ and WRITE operations, that are in progress when

is driven LOW by any means, are given time to complete

HSB
before the STORE operation is initiated. After HSB
the CY14E256L continues SRAM operations for t

, multiple SRAM READ operations take place. If a WRITE

t

DELAY

is in progress when HSB

is pulled LOW, it allows a time, t

to complete. However, any SRAM WRITE cycles requested af ter

goes LOW are inhibited until HSB returns HIGH.

HSB

goes LOW,

. During

DELAY

DELAY

During any STORE operation, regardless of how it is initiated,
the CY14E256L continues to drive the HSB

pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14E256L remains disabled until the
HSB

pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

), an internal RECALL request is latched. When V

RESET

SWITCH

HRECALL

, a RECALL

to complete.

CC

If the CY14E256L is in a WRITE
RECALL, the SRAM

data is corrupted. To help avoid this

state at the end of power up

situation, a 10 Kohm resistor is connected either be tween WE
and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14E256L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ
sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE

controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the seque nce.
It is not necessary that OE
t

cycle time is fulfilled, the SRAM is again activated for

STORE

READ and WRITE operation.

is LOW for a valid sequence. After the

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.

controlled READ operations is

cycle time, the SRAM is once

RECALL

Document Number: 001-06968 Rev. *F Page 4 of 18

[+] Feedback

CY14E256L

Data Protection

The CY14E256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
mode (both CE

is less than V

CC

and WE are low) at power up after a RECALL or

. If the CY14E256L is in a WRITE

SWITCH

after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.

Noise Considerations

The CY14E256L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and V
as possible. As with all high speed CMOS ICs, careful routing of

using leads and traces that are as short

SS,

power, ground, and signals reduce circuit noise.

Hardware Protect

The CY14E256L offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage condi­tions. When V
operations and SRAM WRITEs are inhibited. AutoStore can be

CAP<VSWITCH

completely disabled by tying VCC to ground and applying + 5V
to V
STOREs are only initiated by explicit request using either the

. This is the AutoStore Inhibit mode; in this mode,

CAP

software sequence or the HSB pin.

, all externally initiated STORE

Figure 4. Current Versus Cycle Time (READ)

Figure 5. Current Versus Cycle Time (WRITE)

Low Average Active Power

CMOS technology provides the CY14E256L the benefit of
drawing significantly less c urrent when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper­ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14E256L depends on the
following items:

■

The duty cycle of chip enable

■

The overall cycle rate for accesses

■

The ratio of READs to WRITEs

■

CMOS versus TTL input levels

■

The operating temperature

■

The VCC level

■

IO loading

Preventing Store

The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it has to overpower the internal pull down device. This
device drives HSB

LOW for 20 μs at the onset of a STORE.
When the CY14E256L is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on V
and V
attempts to pull HSB
V
attempt.

crosses V

CC

, the part stops trying to pull HSB LOW and abort the STORE

IL

on the way down, the CY14E256L

SWITCH

LOW. If HSB does not actually get below

of at least 2.2V,

OH

CAP

)

Document Number: 001-06968 Rev. *F Page 5 of 18

[+] Feedback

CY14E256L

Best Practices

Notes

1. I/O state assumes OE

< VIL. Activation of nonvolatile cycles does not depend on state of OE.

2. HSB

STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into

standby mode, inhibiting all operations until HSB

rises.

3. CE

and OE LOW and WE HIGH for output behavior.

4. The six consecutive addresses must be in the order listed. WE

must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

5. While there are 15 addresses on the CY14E256L, only the lower 14 are used to control software modes.

nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:

■

The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system

manufacturing test to ensure these system routines work
consistently.

■

Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).

■

The V
and a maximum value size. Best practice is to meet this

value specified in this data sheet includes a minimum

CAP

requirement and not exceed the maximum V
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers that want to use a larger
V

value to make sure there is extra store charge should

CAP

discuss their V
any impact on the V
period.

size selection with Cypress to understand

CAP

voltage level at the end of a t

CAP

Table 1. Hardware Mode Selection

CE WE HSB A13–A0 Mode IO Power

H X H X Not Selected Output High Z Standby

L H H X Read SRAM Output Data Active
L L H X Write SRAM Input Data Active

X X L X Nonvolatile STORE Output High Z I

LHH0x0E38

0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0

LHH0x0E38

0x31C7
0x03E0
0x3C1F
0x303F
0x0C63

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile STORE

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile RECALL

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

value because

CAP

CC2

[1, 3, 4, 5]

Active

I

CC2

[1, 3, 4, 5]

Active

[1]

[2]

RECALL

Document Number: 001-06968 Rev. *F Page 6 of 18

[+] Feedback

CY14E256L

Maximum Ratings

Notes

6. V

CC

reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V

CAP

if VCC is connected to ground.

7. CE

> VIH does not produce standby current levels until any nonvolat ile cycle in progress has timed out.

Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied ............................................–55°C to +125°C

Supply Voltage on V
Voltage Applied to Outputs

in High Z State.......................................–0.5V to V

Input Voltage..................... ......................–0.5V to Vcc + 0.5V

Transient Voltage (<20 ns) on

Any Pin to Ground Potential..................–2.0V to V

Relative to GND..........–0.5V to 7.0V

CC

CC

CC

+ 0.5V

+ 2.0V

Package Power Dissipation
Capability (T

= 25°C) ...................................................1.0W

A

Surface Mount Lead Soldering

Temperature (3 Seconds)..........................................+260°C

DC output Current (1 output at a time, 1s duration) ....15 mA

Static Discharge Voltage.......................................... > 2001V

(MIL-STD-883, Method 3015)

Latch Up Current................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 4.5V to 5.5V
Industrial -40°C to +85°C 4.5V to 5.5V

CC

DC Electrical Characteristics

Over the operating range (VCC = 4.5V to 5.5V)

[6]

Parameter Description Test Conditions Min Max Unit

I

CC1

I

CC2

I

CC3

I

CC4

I

SB

[7]

Average VCC Current tRC = 25 ns

t

= 35 ns

RC

t

= 45 ns

RC

Dependent on output loading and cycle rate.
Values obtained without output loads.
I

= 0 mA.

OUT

Average VCC Current
during STORE

Average VCC Current at
t

= 200 ns, 5V, 25°C

RC

Typical
Average V

during AutoStore Cycle

CAP

Current

All Inputs Do Not Care, VCC = Max
Average current for duration t

WE

> (VCC – 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.

All Inputs Do Not Care, VCC = Max
Average current for duration t

VCC Standby Current CE > (VCC – 0.2V). All others V

Standby current level after nonvolatile cycle is complete.

Commercial 97

Industrial 100

STORE

STORE

< 0.2V or > (VCC – 0.2V).

IN

80
70

85
70

3mA

10 mA

2mA

1.5 mA

Inputs are static. f = 0 MHz.

[7]

I

SB1

VCC Standby Current
(Standby, Cycling TTL
Input Levels)

tRC = 25 ns, CE > V
tRC = 35 ns, CE > V
tRC = 45 ns, CE > V

IH
IH
IH

Commercial 30

25
22

Industrial 31

26
23

I

IX

I

OZ

V

IH

V

IL

V

OH

Input Leakage Current VCC = Max, VSS < V
Off State Output Leakage

VCC = Max, VSS < V

Current

< V

IN

CC

< VCC, CE or OE > V

IN

or WE < V

IH

-1 +1 μA

IL

-5 +5 μA

Input HIGH Voltage 2.2 VCC +

0.5

Input LOW Voltage VSS –

0.8 V

0.5

Output HIGH Voltage I

= –4 mA 2.4 V

OUT

mA
mA

mA
mA
mA

mA
mA
mA

mA
mA
mA

V

Document Number: 001-06968 Rev. *F Page 7 of 18

[+] Feedback

CY14E256L

DC Electrical Characteristics

5.0V

Output

30 pF

R1 963

Ω

R2

512

Ω

5.0V

Output

5 pF

R1 963

Ω

R2

512

Ω

For Tri-state Specs

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <

5 ns

Input and Output Timing Reference Levels.................... 1.5V

Note

8. These parameters are guaranteed by design and are not tested.

Over the operating range (continued)(VCC = 4.5V to 5.5V)

[6]

Parameter Description Test Conditions Min Max Unit

V
V

V

OL
BL

CAP

Output LOW Voltage I
Logic ‘0’ Voltage on HSB

Output

= 8 mA 0.4 V

OUT

I

= 3 mA 0.4 V

OUT

Storage Capacitor Between V

pin and Vss, 6V rated. 68 µF +20% nom. 54 260 uF

CAP

Data Retention and Endurance

Parameter Description Min Unit

DATA

R

NV

C

Capacitance

In the following table, the capacitance parameters are listed.

Parameter Description Test Conditions Max Unit

C

IN

C

OUT

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

Parameter Description Test Conditions 32-SOIC 32-CDIP Unit

Θ

JA

Θ

JC

Data Retention 100 Years
Nonvolatile STORE Op e r ations 1,000 K

[8]

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 0 to 3.0V

Output Capacitance 7 pF

Thermal Resistance
(Junction to Ambient)

Thermal Resistance

CC

[8]

Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.

5pF

35.45 TBD °C/W

13.26 TBD °C/W

(Junction to Case)

AC Test Conditions

Figure 6. AC Test Loads

Document Number: 001-06968 Rev. *F Page 8 of 18

[+] Feedback

CY14E256L

AC Switching Characteristics

W

5&

W

$$

W

2+$

$''5(66

'4'$7$287

'$7$9$/,'

$''5(66

W

5&

&(

W

$&(

W

/=&(

W

3'

W

+=&(

2(

W

'2(

W

/=2(

W

+=2(

'$7$9$/,'

$&7,9(

67$1'%<

W

38

'4'$7$287

,&&

Notes

9. WE

and HSB must be HIGH during SRAM Read cycles.

10.Device is continuously selected with CE

and OE both Low.

11.Measured ±200 mV from steady state output voltage.

SRAM Read Cycle

Parameter

Cypress

Parameter

t

ACE

[9]

t

RC

[10]

t

AA

t

DOE

[10]

t

OHA

[11]

t

LZCE

[11]

t

HZCE

[11]

t

LZOE

[11]

t

HZOE

[8]

t

PU

[8]

t

PD

Alt

t

ELQV

t

AVAV, tELEH

t

AVQV

t

GLQV

t

AXQX

t

ELQX

t

EHQZ

t

GLQX

t

GHQZ

t

ELICCH

t

EHICCL

Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 10 15 20 ns
Output Hold After Address Change 5 5 5 ns
Chip Enable to Output Active 5 5 5 ns
Chip Disable to Output Inactive 10 13 15 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled

Description

25 ns 35 ns 45 ns

Min Max Min Max Min Max

[9, 10]

Unit

Document Number: 001-06968 Rev. *F Page 9 of 18

Figure 8. SRAM Read Cycle 2: CE and OE Controlled

[9]

[+] Feedback

CY14E256L

SRAM Write Cycle

t

WC

t

SCE

t

HA

t

AW

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

t

WC

ADDRESS

t

SA

t

SCE

t

HA

t

AW

t

PWE

t

SD

t

HD

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

12.If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

13.HSB

must be high during SRAM WRITE cycles.

14.

CE

or WE must be greater than VIH during address transitions.

Parameter

Cypress

Parameter

t

WC

t

PWE

t

SCE

t

SD

t

HD

t

AW

t

SA

t

HA

[11,12]

t

HZWE

[11]

t

LZWE

t
t
t
t
t
t
t
t
t
t

Alt

AVAV
WLWH, tWLEH
ELWH, tELEH
DVWH, tDVEH
WHDX, tEHDX
AVWH, tAVEH
AVWL, tAVEL
WHAX, tEHAX
WLQZ
WHQX

Switching Waveforms

25 ns 35 ns 45 ns

Description

Min Max Min Max Min Max

Unit

Write Cycle Time 25 35 45 ns
Write Pulse Width 20 25 3 0 ns
Chip Enable To End of Write 20 25 30 ns
Data Setup to End of Write 10 12 15 ns
Data Hold After End of Write 0 0 0 ns
Address Setup to End of Write 20 25 30 ns
Address Setup to Start of Write 0 0 0 ns
Address Hold After End of Write 0 0 0 ns
Write Enable to Output Disable 10 13 15 ns
Output Active After End of Write 5 5 5 ns

Figure 9. SRAM Write Cycle 1: WE Controlled

[13, 14]

Document Number: 001-06968 Rev. *F Page 10 of 18

Figure 10. SRAM Write Cycle 2: CE Controlled

[13, 14]

[+] Feedback

CY14E256L

AutoStore or Power Up RECALL

WE

Notes

15.t

HRECALL

starts from the time VCC rises above V

SWITCH

.

16.CE

and OE low and WE high for output behavior.

17.HSB

is asserted low for 1us when V

CAP

drops through V

SWITCH

. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store

takes place.

Parameter Alt Description

[13]

[16]

[16]

[15]

t

RESTORE

t

HLHZ

t

HLQZ , tBLQZ

Power up RECALL Duration 550 μs
STORE Cycle Duration 10 ms
Time Allowed to Complete SRAM Cycle 1 μs
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.6 V
VCC Rise Time 150 μs
Low Voltage Trigger (V

t

HRECALL

t

STORE

t

DELAY

V

SWITCH

V

RESET

t

VCCRISE

t

VSBL

Switching Waveforms

Figure 11. AutoStore/Power Up RECALL

CY14E256L

Min Max

) to HSB low 300 ns

SWITCH

Unit

Document Number: 001-06968 Rev. *F Page 11 of 18

[+] Feedback

CY14E256L

Software Controlled STORE/RECALL Cycle

t

RC

t

RC

t

SA

t

SCE

t

HACE

t

STORE

/ t

RECALL

DATA VALID

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

CE

OE

DQ (DATA)

Notes

18.The software sequence is clocked on the falling edge of CE

without involving OE (double clocking aborts the sequence).

19.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

The software controlled STORE/RECALL cycle follows.

Parameter Alt Description

[16]

t

RC

[18, 19]

t

SA

[18, 19]

t

CW

t

HACE

t

RECALL

[18, 19]

t

AVAV

t

AVEL

t

ELEH

t

ELAX

STORE/RECALL Initiation Cycle Time 25 35 45 ns
Address Setup Time 0 0 0 ns
Clock Pulse Width 20 25 30 ns
Address Hold Time 20 20 20 ns
RECALL Duration 20 20 20 μs

[19]

25 ns 35 ns 45 ns

Min Max Min Max Min Max

Unit

Switching Waveforms

Figure 12. CE Controlled Software STORE/RECALL Cycle

[19]

Document Number: 001-06968 Rev. *F Page 12 of 18

[+] Feedback

CY14E256L

Hardware STORE Cycle

Note

20.t

DHSB

is only applicable after t

STORE

is complete.

Parameter Alt Description

[16, 20]

t

DHSB

t

PHSB

t

HLBL

t

RECOVER, tHHQX

t

HLHX

Hardware STORE High to Inhibit Off 700 ns
Hardware STORE Pulse Width 15 ns
Hardware STORE Low to STORE Busy 300 ns

Switching Waveforms

Figure 13. Hardware STORE Cycle

CY14E256L

Min Max

Unit

Document Number: 001-06968 Rev. *F Page 13 of 18

[+] Feedback

CY14E256L

Ordering Information

Option:
T-Tape and Reel
Blank - Std.

Speed:
25 - 25 ns
35 - 35 ns

Data Bus:
L - x8

Density:
256 - 256 Kb

Voltage:

Cypress

Part Numbering Nomenclature (Commercial and Industrial)
CY 14 E 256 L- SZ 25 X C T

E - 5.0V

nvSRAM

14 - AutoStore + Software Store + Hardware Store

Temperature:

C - Commercial (0 to 70°C)

Pb-Free

45 - 45 ns

I - Industrial (-40 to 85°C)

Package
SZ - 32-SOIC
D - 32-CDIP

Speed

(ns)

25 CY14E256L-SZ25XCT 51-85127 32-pin SOIC (300 mil) Commercial

35 CY14E256L-SZ35XCT 51-85127 32-pin SOIC (300 mil) Commercial

45 CY14E256L-SZ45XCT 51-85127 32-pin SOIC (300 mil) Commercial

All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts

Ordering Code Package Diagram Package Type

CY14E256L-SZ25XC 51-85127 32-pin SOIC (300 mil)
CY14E256L-SZ25XIT 51-85127 32-pin SOIC (300 mil) Industrial
CY14E256L-SZ25XI 51-85127 32-pin SOIC (300 mil)

CY14E256L-SZ35XC 51-85127 32-pin SOIC (300 mil)
CY14E256L-SZ35XIT 51-85127 32-pin SOIC (300 mil) Industrial
CY14E256L-SZ35XI 51-85127 32-pin SOIC (300 mil)

CY14E256L-SZ45XC 51-85127 32-pin SOIC (300 mil)
CY14E256L-SZ45XIT 51-85127 32-pin SOIC (300 mil) Industrial
CY14E256L-SZ45XI 51-85127 32-pin SOIC (300 mil)
CY14E256L-D45XI 001-51694 32-pin CDIP (300 mil)

Operating

Range

Document Number: 001-06968 Rev. *F Page 14 of 18

[+] Feedback

CY14E256L

Package Diagram

51-85058 *A

PIN 1 ID

SEATING PLANE

116

17 32

DIMENSIONS IN INCHES[MM]

MIN.
MAX.

0.292[7.416]

0.299[7.594]

0.405[10.287]

0.419[10.642]

0.050[1.270]
TYP.

0.090[2.286]

0.100[2.540]

0.004[0.101]

0.0100[0.254]

0.006[0.152]

0.012[0.304]

0.021[0.533]

0.041[1.041]

0.026[0.660]

0.032[0.812]

0.004[0.101]

REFERENCE JEDEC MO-119

PART #

S32.3 STANDARD PKG.

SZ32.3 LEAD FREE PKG.

0.014[0.355]

0.020[0.508]

0.810[20.574]

0.822[20.878]

51-85127-*A

Figure 14. 32-Pin (300 Mil) SOIC (51-85127)

Document Number: 001-06968 Rev. *F Page 15 of 18

[+] Feedback

CY14E256L

Package Diagram

001-51694 **

(continued)

Figure 15. 32-Pin (300 Mil) CDIP (001-51694)

Document Number: 001-06968 Rev. *F Page 16 of 18

[+] Feedback

CY14E256L

Document History Page

Document Title: CY14E256L 256 Kbit (32K x 8) nvSRAM
Document Number: 001-06968

Rev. ECN No.

Submission

Date

** 427789 See ECN TUP New data sheet
*A 437321 See ECN TUP Show data sheet on external Web
*B 472053 See ECN TUP Updated Part Numbering Nomenclature and Ordering Information
*C 503290 See ECN PCI Changed from “Advance” to “Preliminary”

*D 1349963 See ECN UHA/SFV Changed from “Preliminary” to “Final.” Updated AC Test Conditions

*E 2427986 See ECN GVCH Move to external web

*F 2606744 02/19/09 GVCH/PYRS Updated Feature Section

Orig. of
Change

Description of Change

Changed the term “Unlimited” to “Infinite”
Changed I
Removed Industrial Grade mention

value from 10mA to 15mA

CC3

Removed 35 ns speed bin
Removed I
Corrected V
Removed all references pertaining to OE

values from the DC table for 35 ns Industrial Grade

CC1

min specification from (VCC - 0.5) to (VSS - 0.5)

IL

controlled Software STORE and
RECALL operation
Changed the address locations of the software STORE/RECALL com­mand
Updated Part Nomenclature Table and Ordering Information Table

Updated Ordering Information Table

Added 35 ns access speed specs
Added CDIP package
Removed HSB

ganging feature
Added footnote 5
Updates all the notes
Added Best practices
Added Industrial specs
Changed Icc3 from 15 mA to 10 mA
Added I
Added parameter V
Changed V
Added footnote 6 and 7
Added t
Added Thermal resistance values
Changed parameter t
Renamed t
Renamed t
Updated Figure 13

spec

SB1

test conditions from -2 and 4 to -4 and 8mA

IH

and V

VSBL

GLAX
RESTORE

to t

BL

parameter to Autostore or Power-up Recall table

RESET

to t

AS

SA

HACE

to t

DHSB

Document Number: 001-06968 Rev. *F Page 17 of 18

[+] Feedback

CY14E256L

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales

Products

PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2006- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used fo r
medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express written agreement w ith Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify , crea te deri vative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress
integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-06968 Rev. *F Revised January 30, 2009 Page 18 of 18

AutoStore and Quant umTrap ar e registered tradem arks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be the trademarks of their respective
holders.

[+] Feedback