Cypress CY14E102L, CY14E102N User Manual
ADVANCE
CY14E102L, CY14E102N
2-Mbit (256K x 8/128K x 16) nvSRAM
Features
Note
1. Address A
0
- A17 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A16 and Data DQ0 - DQ15 for x16 configuration.
A0 - A
17
Address
WE
OE
CE
V
CC
V
SS
V
CAP
DQ0 - DQ7
HSB
CY14E102L
BHE
BLE
Logic Block Diagram
[1]
[1]
CY14E102N
Functional Description
■ 15 ns, 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16
(CY14E102N)
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap
software, device pin, or AutoStore
■ RECALL to SRAM initiated by software or power up
■ Infinite read, write, and recall cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 5V +10% operation
■ Commercial and Industrial temperatures
■ 48-pin FBGA, 44 and 54-pin TSOP II packages
■ Pb-free and RoHS compliance
™
nonvolatile elements initiated by
™
on power down
The Cypress CY14E102L/CY14E102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 256K words of 8 bits each or 128K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data reside in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-45755 Rev. *A Revised June 27, 2008
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ADVANCE
CY14E102L, CY14E102N
Pinouts
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ0
A
4
A
5
NC
DQ2
DQ3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
A
17
A
2
A
1
NC
V
CC
DQ4
NC
DQ5
DQ6
NC
DQ7
NC
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
DQ1
NC
[4]
[2]
[3]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ10
DQ8
DQ9
A
4
A
5
DQ13
DQ12
DQ14
DQ15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ0
BHE
NC
NC
A
2
A
1
BLE
V
CC
DQ2
DQ1
DQ3
DQ4
DQ5
DQ6
DQ7
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
NC
DQ11
[4]
[3]
[2]
(x8)
(Not to Scale)
(x16)
(Not to Scale)
Notes
2. Address expansion for 4 Mbit. NC pin not connected to die.
3. Address expansion for 8 Mbit. NC pin not connected to die.
4. Address expansion for 16 Mbit. NC pin not connected to die.
NC
A
8
NC
NC
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
(Not to Scale)
A
10
NC
WE
DQ7
HSB
NC
V
SS
V
CC
V
CAP
NC
(x8)
[4]
[2]
[3]
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
A
16
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
(Not to Scale)
WE
DQ7
A
0
V
SS
V
CC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
CAP
(x16)
[2]
Figure 1. Pin Diagram - 48 FBGA (Top View)
Figure 2. Pin Diagram - 44 TSOP II (Top View)
Document Number: 001-45755 Rev. *A Page 2 of 21
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ADVANCE
CY14E102L, CY14E102N
Pinouts (continued)
NC
DQ7
DQ6
DQ5
DQ4
V
CC
DQ3
DQ2
DQ1
DQ0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
(Not to Scale)
OE
CE
V
CC
NC
V
SS
NC
A
9
NC
NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
(x16)
[2]
[3]
[4]
Figure 3. Pin Diagram - 54 TSOP II (Top View)
Pin Definitions
Pin Name IO Type Description
A0 – A
17
A0 – A
16
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
DQ0 – DQ15
WE
CE
OE
BHE
BLE
V
SS
V
CC
HSB
V
CAP
NC No Connect No Connect. Do not connect this pin to the die.
Document Number: 001-45755 Rev. *A Page 3 of 21
Input Address Inputs. Used to select one of the 262, 144 bytes of the nvSRAM for x8 Configuration.
Address Inputs. Used to select one of the 131, 072 bytes of the nvSRAM for x16 Configuration.
operation.
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground Ground for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output
Power Supply AutoStore Capacitor . Supplies power to the nvSRAM during power loss to store data from the SRAM
cycles. IO pins are tri-stated on deasserting OE
Hardware Store Busy (HSB
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection is optional).
to nonvolatile elements.
). When LOW this output indicates that a hardware store is in progress.
.
high.
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ADVANCE
CY14E102L, CY14E102N
Device Operation
0.1uF
Vcc
10kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
The CY14E102L/CY14E102N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture all cells are stored and
recalled in parallel. During the STORE and RECALL operations
SRAM read and write operations are inhibited. The
CY14E102L/CY14E102N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
SRAM Read
The CY14E102L/CY14E102N performs a READ cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A
data bytes or 131, 072 words of 16 bits each is accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of t
outputs are valid at t
outputs repeatedly respond to address changes within the t
access time without the need for transitions on any control input
pins. This remains valid until another address change or until CE
or OE is brought HIGH, or WE or HSB is brought LOW.
or A
0-17
. If the read is initiated by CE or OE, the
AA
ACE
determines which of the 262, 144
0-16
or at t
, whichever is later. The data
DOE
AA
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. Monitor the HSB
signal by the system to detect if an
AutoStore cycle is in progress.
Figure 4. AutoStore Mode
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB
is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE
goes high at the end of the cycle. The data on the common IO
pins DQ
before the end of a WE controlled WRITE or before the end of
an CE
are written into the memory if the data is valid t
0–15
controlled WRITE. It is recommended that OE be kept
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE
the output buffers t
is left LOW , internal circuitry turns of f
after WE goes LOW.
HZWE
AutoStore Operation
The CY14E102L/CY14E102N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB,
sequence, and AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14E102L/CY14E102N.
During a normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 4 shows th e proper connection of the storage capacitor
(V
) for automatic store operation. Refer to the section DC
CAP
Electrical Characteristics on page 7 for the size of V
Software Store activated by an address
pin. This stored
CAP
SWITCH
pin from VCC. A STORE
CAP
, the part
capacitor.
CAP
CAP
or WE
CC
.
Hardware STORE Operation
The CY14E102L/CY14E102N provides the HSB pin for
controlling and acknowledging the STORE operations. Use the
HSB
pin to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14E102L/CY14E102N conditionally
initiates a STORE operation after t
SD
only begins if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
SRAM READ and WRITE operations that are in progress when
is driven LOW by any means are given time to complete
HSB
before the STORE operation is initiated. After HSB
the CY14E102LL/CY14E102N continues SRAM operations for
. During t
t
DELAY
place. If a WRITE is in progress when HSB
allowed a time, t
cycles requested after HSB
returns HIGH.
to
, multiple SRAM READ operations may take
DELAY
to complete. However, any SRAM WRITE
DELAY
goes LOW is inhibited until HSB
During any STORE operation, regardless of how it was initiated,
the CY14E102L/CY14E102N continues to drive the HSB
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14E102L/CY14E102N remains disabled until the HSB
returns HIGH. Leave the HSB
unconnected if it is not used.
. An actual STORE cycle
DELAY
is pulled low it is
goes LOW,
pin
pin
Document Number: 001-45755 Rev. *A Page 4 of 21
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ADVANCE
CY14E102L, CY14E102N
Hardware RECALL (Power Up)
Notes
5. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
6. While there are 18/17 address lines on the CY14E102L/CY14E102N, only the lower 16 lines are used to control software modes.
7. IO state depends on the state of OE
, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
During power up or after any low power condition
(V
CC<VSWITCH
V
again exceeds the sense voltage of V
CC
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When
, a RECALL
SWITCH
HRECALL
to complete.
Software ST OR E
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14E102L/CY14E102N
software STORE cycle is initiated by executing sequential
CE
-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed .
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ or WRITE accesses, the sequence is aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE
READs or OE
controlled READs. After the sixth address in the
controlled
sequence is entered, the STORE cycle commences and the chip
is disabled. It is important to use READ cycles and not WRITE
cycles in the sequence, although it is not necessary that OE
LOW for a valid sequence. After the t
the SRAM is activated again for the READ and WRITE operation.
cycle time is fulfilled,
STORE
be
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then, the nonvolatile information is transferred into
the SRAM cells. After the t
ready for READ and WRITE operations. The RECALL operation
does not alter the data in the nonvolatile elements.
controlled READ operations must
cycle time, the SRAM is again
RECALL
Table 1. Mode Selection
CE WE OE
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
L H L 0x4E38
A15 - A0 Mode IO Power
[5,6,7]
Active
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Disable
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[5,6,7]
Document Number: 001-45755 Rev. *A Page 5 of 21
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ADVANCE
CY14E102L, CY14E102N
Table 1. Mode Selection (continued)
CE WE OE
L H L 0x4E38
L H L 0x4E38
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
A15 - A0 Mode IO Power
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
If the AutoStore function is disabled or re-enabled a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state thr ough subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
Active
CC2
[5,6,7]
Data Protection
The CY14E102L/CY14E102N protects data from corruption
during low voltage conditions by inhibiting all externa lly initiated
STORE and write operations. The low voltage condition is
detected when V
is in a write mode (both CE and WE LOW) at power up, after a
RECALL or STORE, the write is inhibited until a negative
transition on CE
inadvertent writes during power up or brown out conditions.
< V
CC
or WE is detected. This protects against
. If the CY14E102L/CY14E102N
SWITCH
Noise Considerations
Refer CY Application Note AN1064.
[5,6,7]
Document Number: 001-45755 Rev. *A Page 6 of 21
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ADVANCE
CY14E102L, CY14E102N
Maximum Ratings
Notes
8. Outputs shorted for no more than one second. No more than one output shorted at a time.
9. Typical conditions for the active cu rrent shown on the front page of the data sheet are average values at 25°C (room temperature), and V
CC
= 5V. Not 100% tested.
10.The HSB
pin has I
OUT
=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .... ... ..........................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +150°C
Supply Voltage on V
Voltage Applied to Outputs
in High-Z State.......................................–0. 5V to V
Input Voltage.............................................–0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential..................–2.0V to V
Relative to GND..........–0.5V to 7.0V
CC
+ 0.5V
CC
+ 2.0V
CC
Package Power Dissipation
Capability (T
= 25°C) ...................................................1.0W
A
Surface Mount Pb Soldering
Temperature (3 Seconds)..........................................+260°C
[8]
Output Short Circuit Current
....................................15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current........................ ... ........................ > 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 4.5V to 5.5V
Industrial –40°C to +85°C 4.5V to 5.5V
CC
DC Electrical Characteristics
[10]
Over the Operating Range (VCC = 4.5V to 5.5V)
Parameter Description Test Conditions Min Max Unit
I
CC1
Average VCC Current tRC = 15 ns
t
= 20 ns
RC
t
= 25 ns
RC
= 45 ns
t
RC
Dependent on output loading and cycle
rate.Values obtained without output loads.
I
= 0 mA
OUT
I
CC2
I
CC3
I
CC4
I
SB
[9]
Average VCC Current
during STORE
Average VCC Current at
t
= 200 ns, 5V, 25°C
RC
typical
Average V
during AutoStore Cycle
CAP
Current
All Inputs Don’t Care, VCC = Max
Average current for duration t
> (VCC – 0.2). All other I/P cycling.
WE
Dependent on output loading and cycle rate. Values obtained
without output loads.
All Inputs Don’t Care, VCC = Max
Average current for duration t
VCC Standby Current CE > (VCC – 0.2). All others V
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
I
I
V
V
V
V
V
IX
OZ
IH
IL
OH
OL
CAP
Input Leakage Current
(except HSB
)
Input Leakage Current
(For HSB)
Off-State Output
= Max, VSS < V
V
CC
V
= Max, VSS < V
CC
VCC = Max, VSS < V
Leakage Current
Input HIGH Volt age 2.0 VCC + 0.5 V
Input LOW Voltage Vss – 0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I
= –2 mA 2.4 V
OUT
= 4 mA 0.4 V
OUT
Storage Capacitor B etween V
Commercial 70
65
65
50
Industrial 75
70
70
52
6mA
STORE
35 mA
6mA
STORE
< 0.2V or > (VCC – 0.2V).
IN
< V
IN
CC
< V
IN
CC
< VCC, CE or OE > V
IN
pin and VSS, 5V Rated 61 82 μF
CAP
IH
–1 +1 μA
–100 +1 μA
–1 +1 μA
3mA
mA
mA
mA
mA
mA
mA
Document Number: 001-45755 Rev. *A Page 7 of 21
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