Cypress CY14E102L, CY14E102N User Manual

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ADVANCE

CY14E102L, CY14E102N

2-Mbit (256K x 8/128K x 16) nvSRAM

Features

Note

1. Address A

- A17 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A16 and Data DQ0 - DQ15 for x16 configuration.

A0 - A

Address

CAP

DQ0 - DQ7

HSB

CY14E102L

BHE BLE

Logic Block Diagram

[1]

CY14E102N

Functional Description

■ 15 ns, 20 ns, 25 ns, and 45 ns access times

■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16

(CY14E102N)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap

software, device pin, or AutoStore

■ RECALL to SRAM initiated by software or power up

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 5V +10% operation

■ Commercial and Industrial temperatures

■ 48-pin FBGA, 44 and 54-pin TSOP II packages

■ Pb-free and RoHS compliance

™

nonvolatile elements initiated by

™

on power down

The Cypress CY14E102L/CY14E102N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 256K words of 8 bits each or 128K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data reside in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-45755 Rev. *A Revised June 27, 2008

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CY14E102L, CY14E102N

Pinouts

CAP

DQ0

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

HSB

DQ1

[4]

[2]

[3]

CAP

DQ10

DQ8

DQ9

DQ13

DQ12

DQ14

DQ15

DQ0

BHE

BLE

DQ2

DQ1

DQ3

DQ4

DQ5

DQ6

DQ7

HSB

DQ11

[4]

[3]

[2]

(x8)

(Not to Scale)

(x16)

(Not to Scale)

Notes

2. Address expansion for 4 Mbit. NC pin not connected to die.

3. Address expansion for 8 Mbit. NC pin not connected to die.

4. Address expansion for 16 Mbit. NC pin not connected to die.

NC NC

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

1 2

3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22

(Not to Scale)

DQ7

HSB

CAP

(x8)

[4]

[2]

[3]

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

BLE

BHE

1 2

3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22

(Not to Scale)

DQ7

DQ15 DQ14 DQ13 DQ12

DQ11 DQ10 DQ9

DQ8

CAP

(x16)

[2]

Figure 1. Pin Diagram - 48 FBGA (Top View)

Figure 2. Pin Diagram - 44 TSOP II (Top View)

Document Number: 001-45755 Rev. *A Page 2 of 21

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Pinouts (continued)

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

CAP

1 2

3 4 5 6 7 8 9

10 11

12 13 14 15 16 17 18 19 20

24 25

26 27

(Not to Scale)

NC NC

54 53 52 51

HSB

BHE BLE

DQ15 DQ14 DQ13 DQ12

DQ11

DQ10 DQ9 DQ8

(x16)

[2]

[3]

[4]

Figure 3. Pin Diagram - 54 TSOP II (Top View)

Pin Definitions

Pin Name IO Type Description

A0 – A

DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on

DQ0 – DQ15

BHE

BLE V

HSB

CAP

NC No Connect No Connect. Do not connect this pin to the die.

Document Number: 001-45755 Rev. *A Page 3 of 21

Input Address Inputs. Used to select one of the 262, 144 bytes of the nvSRAM for x8 Configuration.

Address Inputs. Used to select one of the 131, 072 bytes of the nvSRAM for x16 Configuration.

operation. Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on

operation.

Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address

location latched by the falling edge of CE Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

Input Byte High Enable, Active LOW. Controls DQ15 - DQ8. Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.

Ground Ground for the Device. Must be connected to the ground of the system.

Power Supply Power Supply Inputs to the Device.

Input/Output

Power Supply AutoStore Capacitor . Supplies power to the nvSRAM during power loss to store data from the SRAM

cycles. IO pins are tri-stated on deasserting OE

Hardware Store Busy (HSB

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull

up resistor keeps this pin HIGH if not connected (connection is optional).

to nonvolatile elements.

). When LOW this output indicates that a hardware store is in progress.

high.

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CY14E102L, CY14E102N

Device Operation

0.1uF

Vcc

10kOhm

CAP

Vcc

CAP

The CY14E102L/CY14E102N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14E102L/CY14E102N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations.

SRAM Read

The CY14E102L/CY14E102N performs a READ cycle when CE and OE are LOW, and WE and HSB are HIGH. The address specified on pins A data bytes or 131, 072 words of 16 bits each is accessed. When the read is initiated by an address transition, the outputs are valid after a delay of t outputs are valid at t outputs repeatedly respond to address changes within the t access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.

or A

0-17

. If the read is initiated by CE or OE, the

ACE

determines which of the 262, 144

0-16

or at t

, whichever is later. The data

DOE

To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Monitor the HSB

signal by the system to detect if an

AutoStore cycle is in progress.

Figure 4. AutoStore Mode

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and HSB

is HIGH. The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE goes high at the end of the cycle. The data on the common IO pins DQ before the end of a WE controlled WRITE or before the end of an CE

are written into the memory if the data is valid t

0–15

controlled WRITE. It is recommended that OE be kept HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE the output buffers t

is left LOW , internal circuitry turns of f

after WE goes LOW.

HZWE

AutoStore Operation

The CY14E102L/CY14E102N stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB, sequence, and AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E102L/CY14E102N.

During a normal operation, the device draws current from V charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below V automatically disconnects the V operation is initiated with power provided by the V

Figure 4 shows th e proper connection of the storage capacitor

) for automatic store operation. Refer to the section DC

CAP

Electrical Characteristics on page 7 for the size of V

Software Store activated by an address

pin. This stored

CAP

SWITCH

pin from VCC. A STORE

CAP

, the part

capacitor.

CAP

or WE

Hardware STORE Operation

The CY14E102L/CY14E102N provides the HSB pin for controlling and acknowledging the STORE operations. Use the HSB

pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14E102L/CY14E102N conditionally initiates a STORE operation after t

only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE (initiated by any means) is in progress.

SRAM READ and WRITE operations that are in progress when

is driven LOW by any means are given time to complete

HSB before the STORE operation is initiated. After HSB the CY14E102LL/CY14E102N continues SRAM operations for

. During t

DELAY

place. If a WRITE is in progress when HSB allowed a time, t cycles requested after HSB returns HIGH.

, multiple SRAM READ operations may take

DELAY

to complete. However, any SRAM WRITE

DELAY

goes LOW is inhibited until HSB

During any STORE operation, regardless of how it was initiated, the CY14E102L/CY14E102N continues to drive the HSB LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14E102L/CY14E102N remains disabled until the HSB returns HIGH. Leave the HSB

unconnected if it is not used.

. An actual STORE cycle

DELAY

is pulled low it is

goes LOW,

Document Number: 001-45755 Rev. *A Page 4 of 21

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CY14E102L, CY14E102N

Hardware RECALL (Power Up)

Notes

5. The six consecutive address locations must be in the order listed. WE

must be HIGH during all six cycles to enable a nonvolatile cycle.

6. While there are 18/17 address lines on the CY14E102L/CY14E102N, only the lower 16 lines are used to control software modes.

7. IO state depends on the state of OE

, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.

During power up or after any low power condition (V

CC<VSWITCH

again exceeds the sense voltage of V

cycle is automatically initiated and takes t

), an internal RECALL request is latched. When

, a RECALL

SWITCH

HRECALL

to complete.

Software ST OR E

Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14E102L/CY14E102N software STORE cycle is initiated by executing sequential CE

-controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed .

Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If there are intervening READ or WRITE accesses, the sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ sequence must be performed.

1. Read Address 0x4E38 Valid READ

2. Read Address 0xB1C7 Valid READ

3. Read Address 0x83E0 Valid READ

4. Read Address 0x7C1F Valid READ

5. Read Address 0x703F Valid READ

6. Read Address 0x8FC0 Initiate STORE Cycle

The software sequence may be clocked with CE READs or OE

controlled READs. After the sixth address in the

controlled

sequence is entered, the STORE cycle commences and the chip is disabled. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE LOW for a valid sequence. After the t the SRAM is activated again for the READ and WRITE operation.

cycle time is fulfilled,

STORE

Software RECALL

Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE be performed:

1. Read Address 0x4E38 Valid READ

2. Read Address 0xB1C7 Valid READ

3. Read Address 0x83E0 Valid READ

4. Read Address 0x7C1F Valid READ

5. Read Address 0x703F Valid READ

6. Read Address 0x4C63 Initiate RECALL Cycle

Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then, the nonvolatile information is transferred into the SRAM cells. After the t ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.

controlled READ operations must

cycle time, the SRAM is again

RECALL

Table 1. Mode Selection

CE WE OE

H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38

L H L 0x4E38

A15 - A0 Mode IO Power

[5,6,7]

Active

0xB1C7

0x83E0 0x7C1F 0x703F 0x8B45

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

AutoStore

Output Data Output Data Output Data Output Data Output Data Output Data

Disable

0xB1C7

0x83E0 0x7C1F 0x703F 0x4B46

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

AutoStore Enable

Output Data Output Data Output Data Output Data Output Data Output Data

Active

[5,6,7]

Document Number: 001-45755 Rev. *A Page 5 of 21

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Table 1. Mode Selection (continued)

CE WE OE

L H L 0x4E38

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x8B45 AutoStore Disable

The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x4B46 AutoStore Enable

A15 - A0 Mode IO Power

0xB1C7

0x83E0 0x7C1F 0x703F 0x8FC0

0xB1C7

0x83E0 0x7C1F 0x703F 0x4C63

If the AutoStore function is disabled or re-enabled a manual STORE operation (hardware or software) must be issued to save the AutoStore state thr ough subsequent power down cycles. The part comes from the factory with AutoStore enabled.

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

Nonvolatile Store

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

Nonvolatile

Recall

Output Data Output Data Output Data Output Data Output Data

Output High Z

Output Data Output Data Output Data Output Data Output Data

Output High Z

Active I

Active

CC2

[5,6,7]

Data Protection

The CY14E102L/CY14E102N protects data from corruption during low voltage conditions by inhibiting all externa lly initiated STORE and write operations. The low voltage condition is detected when V is in a write mode (both CE and WE LOW) at power up, after a RECALL or STORE, the write is inhibited until a negative transition on CE inadvertent writes during power up or brown out conditions.

< V

or WE is detected. This protects against

. If the CY14E102L/CY14E102N

SWITCH

Noise Considerations

Refer CY Application Note AN1064.

[5,6,7]

Document Number: 001-45755 Rev. *A Page 6 of 21

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Maximum Ratings

Notes

8. Outputs shorted for no more than one second. No more than one output shorted at a time.

9. Typical conditions for the active cu rrent shown on the front page of the data sheet are average values at 25°C (room temperature), and V

= 5V. Not 100% tested.

10.The HSB

pin has I

OUT

=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature .... ... ..........................–65°C to +150°C

Ambient Temperature with

Power Applied ............................................–55°C to +150°C

Supply Voltage on V Voltage Applied to Outputs

in High-Z State.......................................–0. 5V to V

Input Voltage.............................................–0.5V to Vcc+0.5V

Transient Voltage (<20 ns) on

Any Pin to Ground Potential..................–2.0V to V

Relative to GND..........–0.5V to 7.0V

+ 0.5V

+ 2.0V

Package Power Dissipation Capability (T

= 25°C) ...................................................1.0W

Surface Mount Pb Soldering

Temperature (3 Seconds)..........................................+260°C

[8]

Output Short Circuit Current

....................................15 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current........................ ... ........................ > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 4.5V to 5.5V Industrial –40°C to +85°C 4.5V to 5.5V

DC Electrical Characteristics

[10]

Over the Operating Range (VCC = 4.5V to 5.5V)

Parameter Description Test Conditions Min Max Unit

CC1

Average VCC Current tRC = 15 ns

= 20 ns

= 25 ns

= 45 ns

Dependent on output loading and cycle rate.Values obtained without output loads. I

= 0 mA

OUT

CC2

CC3

CC4

[9]

Average VCC Current during STORE

Average VCC Current at t

= 200 ns, 5V, 25°C

typical Average V

during AutoStore Cycle

CAP

Current

All Inputs Don’t Care, VCC = Max Average current for duration t

> (VCC – 0.2). All other I/P cycling.

WE Dependent on output loading and cycle rate. Values obtained without output loads.

All Inputs Don’t Care, VCC = Max Average current for duration t

VCC Standby Current CE > (VCC – 0.2). All others V

Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz.

V V V V V

IH IL OH OL CAP

Input Leakage Current (except HSB

)

Input Leakage Current (For HSB)

Off-State Output

= Max, VSS < V

VCC = Max, VSS < V

Leakage Current Input HIGH Volt age 2.0 VCC + 0.5 V Input LOW Voltage Vss – 0.5 0.8 V Output HIGH Voltage I Output LOW Voltage I

= –2 mA 2.4 V

OUT

= 4 mA 0.4 V

OUT

Storage Capacitor B etween V

Commercial 70

65 65 50

Industrial 75

70 70 52

6mA

STORE

35 mA

6mA

STORE

< 0.2V or > (VCC – 0.2V).

< V

< VCC, CE or OE > V

pin and VSS, 5V Rated 61 82 μF

CAP

–1 +1 μA

–100 +1 μA

–1 +1 μA

3mA

mA mA mA

Document Number: 001-45755 Rev. *A Page 7 of 21

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CY14E102L, CY14E102N

Capacitance

5.0V

OUTPUT

5 pF

512Ω

5.0V

OUTPUT

30 pF

512Ω

for tri-state specs

963Ω

Note

11.These parameters are guaranteed but not tested.

The following table lists the capacitance parameters.

Parameter Description Test Conditions Max Unit

C C

IN OUT

Input Capacitance TA = 25°C, f = 1 MHz,

= 0 to 3.0V

Output Capacita nce 7 pF

[11]

7pF

Thermal Resistance

The following table lists the thermal resistance parameters.

Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit

Thermal Resistance

(Junction to Ambient) Thermal Resistance

(Junction to Case)

T est conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.

[11]

28.82 31.11 30.73 °C/W

7.84 5.56 6.08 °C/W

AC Test Loads

AC Test Conditions

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <5 ns

Input and Output Timing Reference Levels....................1.5V

Document Number: 001-45755 Rev. *A Page 8 of 21

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AC Switching Characteristics

Notes

12.WE

must be HIGH during SRAM read cycles.

13.Device is continuously selected with CE

and OE both LOW.

14.Measured ±200 mV from steady state output voltage.

15.If WE

is LOW when CE goes LOW, the output goes into high impedance state.

The following table lists the AC switching characteristics.

Parameters

Cypress

Parameters

SRAM Read Cycle

ACE

DOE

OHA

LZCE

HZCE

LZOE

HZOE

DBE

LZBE

HZBE

[12]

[13]

[14]

[11] [11]

ACS

OLZ

OHZ

- Byte Enable to Dat a Valid 10 10 12 20 ns

- Byte Enable to Output Active 0 0 0 0 ns

- Byte Disable to Output Inactive 7 8 10 15 ns

SRAM Write Cycle

PWE

SCE

HZWE

LZWE

[14,15]

[14]

-Byte Enable to End of Write15152030ns

Alt

Chip Enable Access Time 15 20 25 45 ns Read Cycle Time 15 20 25 45 ns Address Access Time 15 20 25 45 ns Output Enable to Data Valid 10 10 12 20 ns Output Hold After Address

Change Chip Enable to Output Active 3 3 3 3 ns Chip Disable to Output Inactive 7 8 10 15 ns Output Enable to Output Active 0 0 0 0 ns Output Disable to Output

Inactive Chip Enable to Power Active 0 0 0 0 ns Chip Disable to Power Standby 15 20 25 45 ns

Write Cycle Time 15 20 25 45 ns Write Pulse Width 10152030ns Chip Enable To End of Write15152030ns Data Setup to End of Write 5 8 10 15 ns Data Hold After End of Write 0 0 0 0 ns Address Setup to End of Write 10 15 20 30 ns Address Setup to Start of Write 0 0 0 0 ns Address Hold After End of Write 0 0 0 0 ns Write Enable to Output Disable 7 8 10 15 ns Output Active after End of Write 3 3 3 3 ns

Description

15 ns 20 ns 25 ns 45 ns

Min Max Min Max Min Max Min Max

Unit

3333ns

7 8 10 15 ns

Document Number: 001-45755 Rev. *A Page 9 of 21

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AutoStore and Power Up RECALL

Notes

16.t

HRECALL

starts from the time VCC rises above V

SWITCH.

17.If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.

18.The software sequence is clocked with CE

controlled or OE controlled reads.

19.The six consecutive addresses must be read in the order listed in the mode selection table. WE

must be HIGH during all six consecutive cycles.

20.This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.

21.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command

22.On a hardware STORE initiation, SRAM operation continues to be enabled for time t

DELAY

to allow read and write cycles to complete.

Parameters Description

[16]

HRECALL

STORE

SWITCH

VCCRISE

Power Up RECALL Duration 20 ms

[17]

STORE Cycle Duration 15 ms Low Voltage Trigger Level 4.4 V VCC Rise Time 150 μs

CY14E102L/CY14E102N

Min Max

Unit

Software Controlled STORE and RECALL Cycle

The following table lists the software controlled STORE and RECALL cycle parameters.

Parameters Description

GHAX

RECALL

[20, 21]

STORE and RECALL Initiation Cycle Time 15 20 25 45 ns Address Setup Time 0 0 0 0 ns Clock Pulse Width 12 15 20 30 ns Address Hold Time 1 1 1 1 ns RECALL Duration 200 200 200 200 μs Soft Sequence Processing Time 70 70 70 70 μs

15ns 20 ns 25ns 45ns

Min Max Min Max Min Max Min Max

Hardware STORE Cycle

Parameters Description

[22]

DELAY

HLHX

Time allowed to complete SRAM cycle 1 70 μs Hardware STORE pulse width 15 ns

[18, 19]

CY14E102L/CY14E102N

Min Max

Unit

Document Number: 001-45755 Rev. *A Page 10 of 21

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OHA

ADDRESS

DQ (DATA OUT)

DATA VALID

ADDRESS

ACE

LZCE

HZCE

DOE

LZOE

DATA VALID

ACTIVE

STANDBY

DQ (DATA OUT)

ICC

LZBE

DBE

HZBE

HZOE

HZCE

BHE , BLE

Notes

23.HSB

must remain HIGH during READ and WRITE cycles.

24.CE

or WE must be >VIH during address transitions.

25.BHE

and BLE are applicable for x16 configuration only.

Switching Waveforms

Figure 5. SRAM Read Cycle #1: Address Controlled

[12, 13, 23]

Figure 6. SRAM Read Cycle #2: CE and OE Controlled

[12, 23, 25]

Document Number: 001-45755 Rev. *A Page 11 of 21

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Switching Waveforms (continued)

SCE

PWE

HZWE

LZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

BHE , BLE

ADDRESS

SCE

PWE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

BHE , BLE

Figure 7. SRAM Write Cycle #1: WE

Controlled

[13, 21, 22, 23]

Figure 8. SRAM Write Cycle #2: CE Controlled

Document Number: 001-45755 Rev. *A Page 12 of 21

[13, 21, 22, 23]

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Switching Waveforms (continued)

SWITCH

STORE

HRECALL

AutoStore

POWER-UP RECALL

Read & Write Inhibited

STORE occurs only if a SRAM write has happened

No STORE occurs without atleast one SRAM write

VCCRISE

Note

26.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V

SWITCH

Figure 9. AutoStore or Power Up RECALL

[26]

Figure 10. CE Controlled Software STORE/RECALL Cycle

Document Number: 001-45755 Rev. *A Page 13 of 21

[19]

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CY14E102L, CY14E102N

Switching Waveforms (continued)

ADDRESS # 1 ADDRESS # 6

ADDRESS

GHAX

STORE

/ t

RECALL

DATA VALID

HIGH IMPEDANCE

DQ (DATA)

Figure 11. OE

Controlled Software STORE/RECA L L Cy cle

[19]

Figure 12. Hardware STORE Cycle

Figure 13. Soft Sequence Processing

[22]

[20, 21]

Document Number: 001-45755 Rev. *A Page 14 of 21

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CY14E102L, CY14E102N

Ordering Information

Speed

(ns)

15 CY14B102L-ZS15XCT 51-85087 44-pin TSOP II Commercial

CY14E102L-ZS15XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS15XI 51-85087 44-pin TSOP II CY14E102L-BA15XCT 51-85128 48-ball FBGA Commercial CY14E102L-BA15XIT 51-85128 48-ball FBGA Industrial CY14E102L-BA15XI 51-85128 48-ball FBGA CY14E102L-ZSP15XCT 51-85160 54-pin TSOP II Commercial CY14E102L-ZSP15XIT 51-85160 54-pin TSOP II Industrial CY14E102L-ZSP15XI 51-85160 54-pin TSOP II CY14E102N-BA115XCT 51-85128 48-ball FBGA Commercial CY14E102N-BA15XIT 51-85128 48-ball FBGA Industrial CY14E102N-BA15XI 51-85128 48-ball FBGA CY14E102N-ZSP15XCT 51-85160 54-pin TSOP II Commercial CY14E102N-ZSP15XIT 51-85160 54-pin TSOP II Industrial CY14E102N-ZSP15XI 51-85160 54-pin TSOP II

20 CY14B102L-ZS20XCT 51-85087 44-pin TSOP II Commercial

CY14E102L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS20XI 51-85087 44-pin TSOP II CY14E102L-BA20XCT 51-85128 48-ball FBGA Commercial CY14E102L-BA20XIT 51-85128 48-ball FBGA Industrial CY14E102L-BA20XI 51-85128 48-ball FBGA CY14E102L-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14E102L-ZSP20XIT 51-85160 54-pin TSOP II Industrial CY14E102L-ZSP20XI 51-85160 54-pin TSOP II CY14E102N-BA20XCT 51-85128 48-ball FBGA Commercial CY14E102N-BA20XIT 51-85128 48-ball FBGA Industrial CY14E102N-BA20XI 51-85128 48-ball FBGA CY14E102N-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14E102N-ZSP20XIT 51-85160 54-pin TSOP II Industrial CY14E102N-ZSP20XI 51-85160 54-pin TSOP II

Ordering Code

Package

Diagram

Package Type

Operating

Range

Document Number: 001-45755 Rev. *A Page 15 of 21

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CY14E102L, CY14E102N

Ordering Information (continued)

Speed

(ns)

25 CY14E102L-ZS25XCT 51-85087 44-pin TSOP II Commercial

CY14E102L-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS25XI 51-85087 44-pin TSOP II CY14E102N-BA25XCT 51-85128 48-ball FBGA Commercial CY14E102L-BA25XIT 51-85128 48-ball FBGA Industrial CY14E102L-BA25XI 51-85128 48-ball FBGA CY14E102L-ZSP25XCT 51-85160 54-pin TSOP II Commercial CY14E102L-ZSP25XIT 51-85160 54-pin TSOP II Industrial CY14E102L-ZSP25XI 51-85160 54-pin TSOP II CY14E102N-BA25XCT 51-85128 48-ball FBGA Commercial CY14E102N-BA25XIT 51-85128 48-ball FBGA Industrial CY14E102N-BA25XI 51-85128 48-ball FBGA CY14E102N-ZSP25XCT 51-85160 54-pin TSOP II Commercial CY14E102N-ZSP25XIT 51-85160 54-pin TSOP II Industrial CY14E102N-ZSP25XI 51-85160 54-pin TSOP II

45 CY14E102L-ZS45XCT 51-85087 44-pin TSOP II Commercial

CY14E102L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS45XI 51-85087 44-pin TSOP II CY14E102L-BA45XCT 51-85128 48-ball FBGA Commercial CY14E102L-BA45XIT 51-85128 48-ball FBGA Industrial CY14E102L-BA45XI 51-85128 48-ball FBGA CY14E102L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14E102L-ZSP45XIT 51-85160 54-pin TSOP II Industrial CY14E102L-ZSP45XI 51-85160 54-pin TSOP II CY14E102N-BA45XCT 51-85128 48-ball FBGA Commercial CY14E102N-BA45XIT 51-85128 48-ball FBGA Industrial CY14E102N-BA45XI 51-85128 48-ball FBGA CY14E102N-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14E102N-ZSP45XIT 51-85160 54-pin TSOP II Industrial CY14E102N-ZSP45XI 51-85160 54-pin TSOP II

All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these p arts.

Ordering Code

Package

Diagram

Package Type

Operating

Range

Document Number: 001-45755 Rev. *A Page 16 of 21

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CY14E102L, CY14E102N

Part Numbering Nomenclature

Option: T - Tape & Reel Blank - Std.

Speed:

20 - 20 ns

25 - 25 ns

Data Bus: L - x8 N - x16

Density:

102 - 2 Mb

Voltage: E - 5.0V

Cypress

NVSRAM

14 - Auto Store + Software Store + Hardware Store

Temperature:

C - Commercial (0 to 70°C)

I - Industrial (–40 to 85°C)

Pb-Free

Package: BA - 48 FBGA ZS - TSOP II

P - 54 Pin Blank - 44 Pin

45 - 45 ns

CY 14 E 102 L - ZS P 15 X C T

15 - 15 ns

Document Number: 001-45755 Rev. *A Page 17 of 21

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CY14E102L, CY14E102N

Package Diagrams

MAX MIN.

DIMENSION IN MM(INCH)

11.938 (0.470)

PLANE

SEATING

PIN 1 I.D.

18.517 (0.729)

0.800 BSC

0°-5°

0.400(0.016)

0.300 (0.012)

EJECTOR PIN

OKE

11.735 (0.462)

10.058 (0.396)

10.262 (0.404)

1.194 (0.047)

0.991 (0.039)

0.150 (0.0059)

0.050 (0.0020)

(0.0315)

18.313 (0.721)

10.058 (0.396)

10.262 (0.404)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

BASE PLANE

0.10 (.004)

TOP VIEW BOTTOM VIEW

51-85087-*A

Figure 14. 44-Pin TSOP II

Document Number: 001-45755 Rev. *A Page 18 of 21

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CY14E102L, CY14E102N

Package Diagrams (continued)

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.20 MAX

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

A1 CORNER

TOP VIEW

BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

10.00±0.10

6.00±0.10

1.875

2.625

0.36

51-85128-*D

Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm

Document Number: 001-45755 Rev. *A Page 19 of 21

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CY14E102L, CY14E102N

Package Diagrams (continued)

51-85160-**

Figure 16. 54-Pin TSOP II

Document Number: 001-45755 Rev. *A Page 20 of 21

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CY14E102L, CY14E102N

Document History Page

Document Title: CY14E102L/CY14E102N 2-Mbit (256K x 8/128K x 16) nvSRAM Document Number: 001- 45755

REV. ECN NO.

Orig. of

Change

Submission

Date

Description of Change

** 2470086 GVCH New Data Sheet

*A 2522209 GVCH/

AESA

06/27/2008 Added 20 ns access speed information in “Features”.

Added I Updated Thermal resistance values for 48-FBGA, 44-TSOP II and 54-TSOP II

for tRC=20 ns for both industrial and Commercial temperature Grade.

CC1

Packages. Added AC Switching Characteristics specs for 20 ns access speed. Added software controlled STORE/RECALL cycle specs for 20 ns access speed. Updated ordering information and part numbering nomenclature. Updated data sheet template.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’ s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

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© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use o f any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for med ical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cy press does n ot assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-45755 Rev. *A Revised June 27, 2008 Page 21 of 21

AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.

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Cypress CY14E102L, CY14E102N User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Logic Block Diagram

Functional Description

Pinouts

Device Operation

SRAM Read

SRAM Write

AutoStore Operation

Hardware STORE Operation

Hardware RECALL (Power Up)

Software ST OR E

Software RECALL

Preventing AutoStore

Data Protection

Noise Considerations

Maximum Ratings

Operating Range

DC Electrical Characteristics

Capacitance

Thermal Resistance

AC Test Loads

AC Test Conditions

AC Switching Characteristics

AutoStore and Power Up RECALL

Software Controlled STORE and RECALL Cycle

Hardware STORE Cycle

Switching Waveforms

Ordering Information

Package Diagrams

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Products

PSoC Solutions