Cypress CY14B256L User Manual

CY14B256L

256 Kbit (32K x 8) nvSRAM

Features

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

Quantum Trap

512 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

OE

CE

WE

HSB

V

CC

V

CAP

A

13

-

A

0

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

■

25 ns, 35 ns, and 45 ns access times

■

Pin compatible with STK14D88

■

Hands off automatic STORE on power down with only a small
capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited READ, WRITE, and RECALL cycles

■

200,000 STORE cycles to QuantumTrap

■

20 year data retention at 55°C

■

Single 3V +20%, –10% operation

■

Commercial and industrial temperature

■

32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages

■

RoHS compliance

Functional Description

The Cypress CY14B256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB

pin.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06422 Rev. *H Revised January 30, 2009

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CY14B256L

Pin Configurations

Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP

Pin Definitions

Pin Name Alt IO Type Description

A

0–A14

DQ

-DQ

0

7

WE

W

CE E
OE

V

V

SS

CC

G

HSB

V

CAP

NC No Connect No Connect. This pin is not connected to the die.

Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input or Output Bidirectional Dat a IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.
Input Chip Enable Input, Active LOW . When LOW , selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-06422 Rev. *H Page 2 of 18

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CY14B256L

Device Operation

V

CC

V

CC

V

CAP

V

CAP

WE

10k Ohm

0.1 F

U

The CY14B256L nvSRAM is made up of two functional compo­nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B256L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera­tions from the nonvolatile cells and up to 200K STORE opera­tions.

SRAM Read

The CY14B256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until

determines the 32,768 data bytes accessed. When

0–14

(READ cycle 1). If the READ is initiated

or OE, the outputs are valid at t

AA

or at t

ACE

access time without the need for

AA

another address change or until CE or OE is brought HIGH, or
WE

or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB
the WRITE cycle and must remain stable until either CE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE

are written into the memory if it has valid tSD, before

0–7

controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE
LOW, inte rnal circuitry turns off the output buffers t
goes LOW.

AutoStore Operation

The CY14B256L stores data to nvSRAM using one of three
storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256L.

During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V

pin drops below V

CC

operation is initiated with power provided by the V

Figure 2 shows the proper connection of the storage capacitor

) for automatic store operation. Refer to the DC Electrical

(V

CAP

Characteristics on page 7 for the size of V

pin. This stored

CAP

pin from VCC. A STORE

CAP

CAP

, whichever

DOE

or WE

is left

after WE

HZWE

to

CC

, the part

SWITCH

capacitor.

CAP

. The voltage on

the V
A pull up is placed on WE

pin is driven to 5V by a charge pump internal to the chip.

CAP

to hold it inactive during power up.

Figure 2. AutoStore Mode

To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB

signal is monitored by the system to detect if an

AutoStore cycle is in progress.

Hardware STORE (HSB) Operation

The CY14B256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
LOW, the CY14B256L conditionally initiates a STORE operation
after t
the SRAM takes place since the last STORE or RECALL cycle.
The HSB

. An actual STORE cycle only begins if a WRITE to

DELAY

pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress.

SRAM READ and WRITE operations, that are in progress when
HSB

is driven LOW by any means, are given time to comple te
before the STORE operation is initiated. After HSB
the CY14B256L continues SRAM operations for t
t

, multiple SRAM READ operations take place. If a WRITE

DELAY

is in progress when HSB

is pulled LOW, it allows a time, t
to complete. However, any SRAM WRITE cycles requested after
HSB

goes LOW are inhibited until HSB returns HIGH.

is not used, it is left unconnected.

If HSB

pin is used to

pin is driven

goes LOW,

. During

DELAY

DELAY

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <
V

), an internal RECALL request is latched. When V

SWITCH

CC

.

Document Number: 001-06422 Rev. *H Page 3 of 18

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CY14B256L

once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

HRECALL

SWITCH

, a RECALL

to complete.

Software ST ORE

Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B256L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ
sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE
OE

controlled READs. When the sixth address in the sequence

controlled READs or

is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE
a valid sequence. After the t
SRAM is again activated for READ and WRITE operation.

cycle time is fulfilled, the

STORE

is LOW for

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.

controlled READ operations is

cycle time, the SRAM is once

RECALL

Data Protection

The CY14B256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
mode (both CE

is less than V

CC

and WE are low) at power up after a RECALL or

. If the CY14B256L is in a WRITE

SWITCH

after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.

Noise Considerations

The CY14B256L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and V
as possible. As with all high speed CMOS ICs, careful routing of

using leads and traces that are as short

SS,

power, ground, and signals reduce circuit noise.

Low Average Active Power

CMOS technology provides the CY14B256L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between I
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper­ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B256L depends on the
following items:

■

The duty cycle of chip enable

■

The overall cycle rate for accesses

■

The ratio of READs to WRITEs

■

CMOS versus TTL input levels

■

The operating temperature

■

The VCC level

■

IO loading

Figure 3. Current vs. Cycle Time

CC

and

Document Number: 001-06422 Rev. *H Page 4 of 18

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CY14B256L

Preventing Store

Best Practices

Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE

controlled or OE controlled READ operations:

1. Read Address 0x0E38 Valid READ

2. Read Address 0x31C7 Valid READ

3. Read Address 0x03E0 Valid READ

4. Read Address 0x3C1F Valid READ

5. Read Address 0x303F Valid READ

6. Read Address 0x03F8 AutoStore Disable

Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of

controlled or OE controlled READ operations:

CE

1. Read Address 0x0E38 Valid READ

2. Read Address 0x31C7 Valid READ

3. Read Address 0x03E0 Valid READ

4. Read Address 0x3C1F Valid READ

5. Read Address 0x303F Valid READ

6. Read Address 0x07F0 AutoStore Enable

If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.

nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:

■

The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.

■

Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).

■

If autostore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.

■

The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum V
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger V
to make sure there is extra store charge should discuss their
V

CAP

the V

value specified in this data sheet includes a minimum

CAP

value because

CAP

value

CAP

size selection with Cypress to understand any impact on

voltage level at the end of a t

CAP

RECALL

period.

Document Number: 001-06422 Rev. *H Page 5 of 18

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CY14B256L

Table 1. Hardware Mode Selection

Notes

1. The six consecutive address locations are in the order listed. WE

is HIGH during all six cycles to enable a nonvolatile cycle.

2. While there are 15 address lines on the CY14B256L, only the lower 14 lines are used to control software modes.

3. IO state depends on the state of OE

. The IO table shown is based on OE Low.

CE WE OE

H X X X Not Selected Output High Z Standby

L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
LHL0x0E38

LHL0x0E38

LHL0x0E38

LHL0x0E38

A14 – A

0x31C7
0x03E0

0x3C1F

0x303F
0x03F8

0x31C7
0x03E0

0x3C1F

0x303F
0x07F0

0x31C7
0x03E0

0x3C1F

0x303F

0x0FC0

0x31C7
0x03E0

0x3C1F

0x303F
0x0C63

0

Mode IO Power

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

AutoStore Disable

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

AutoStore Enable

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile Store

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile Recall

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Active

Active

Active I

Active

[1, 2, 3]

[1, 2, 3]

CC2

[1, 2, 3]

[1, 2, 3]

Document Number: 001-06422 Rev. *H Page 6 of 18

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CY14B256L

Maximum Ratings

Note

4. The HSB

pin has I

OUT

= –10 μA for VOH of 2.4 V. This parameter is characterized but not tested.

Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied ............................................–55°C to +125°C

Supply Voltage on V
Voltage Applied to Outputs

in High Z State.......................................–0.5V to V

Input Voltage..................... ......................–0.5V to Vcc + 0.5V

Transient Voltage (<20 ns) on

Any Pin to Ground Potential..................–2.0V to V

Relative to GND..........–0.5V to 4.1V

CC

CC

CC

+ 0.5V

+ 2.0V

Package Power Dissipation
Capability (T

= 25°C) ...................................................1.0W

A

Surface Mount Lead Soldering

Temperature (3 Seconds)..........................................+260°C

DC output Current (1 output at a time, 1s duration) ....15 mA

Static Discharge Voltage.......................................... > 2001V

(MIL-STD-883, Method 3015)

Latch Up Current................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 2.7V to 3.6V
Industrial -40°C to +85°C 2.7V to 3.6V

CC

DC Electrical Characteristics

Over the operating range (VCC = 2.7V to 3.6V)

[4]

Parameter Description Test Conditions Min Max Unit

I

CC1

I

CC2

I

CC3

I

CC4

I

SB

Average VCC Current tRC = 25 ns

t

= 35 ns

RC

= 45 ns

t

RC

Dependent on output loading and cycle rate.
Values obtained without output loads.
I

= 0 mA.

OUT

Average VCC Current
during STORE

Average VCC Current at
t

= 200 ns, 5V, 25°C

RC

Typical
Average V

during AutoStore Cycle

CAP

Current

All Inputs Do Not Care, VCC = Max
Average current for duration t

WE

> (VCC – 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.

All Inputs Do Not Care, VCC = Max
Average current for duration t

VCC Standby Current CE > (VCC – 0.2V). All others V

Standby current level after nonvolatile cycle is complete.

Commercial 65

Industrial 70

STORE

STORE

< 0.2V or > (VCC – 0.2V).

IN

55
50

60
55

3mA

10 mA

3mA

3mA

Inputs are static. f = 0 MHz.

I
I

V

V
V
V
V

IX
OZ

IH

IL
OH
OL
CAP

Input Leakage Current VCC = Max, VSS < V
Off State Output

VCC = Max, VSS < V

Leakage Current

< V

IN

CC

< VCC, CE or OE > V

IN

or WE < V

IH

-1 +1 μA

IL

-1 +1 μA

Input HIGH Voltage 2.0 VCC +

0.5
Input LOW Voltage VSS – 0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I
Storage Capacitor Between V

= –2 mA 2.4 V

OUT

= 4 mA 0.4 V

OUT

pin and Vss, 6V rated. 17 120 uF

CAP

Data Retention and Endurance

Parameter Description Min Unit

DATA
NV

C

R

Data Retention at 55°C 20 Years
Nonvolatile STORE Operations 200 K

mA
mA

mA
mA
mA

V

Document Number: 001-06422 Rev. *H Page 7 of 18

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CY14B256L

Capacitance

3.0V

Output

30 pF

R1 577Ω

R2

789Ω

3.0V

Output

5 pF

R1 577

Ω

R2

789

Ω

For Tri-state Specs

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <

5 ns

Input and Output Timing Reference Levels.................... 1.5V

Note

5. These parameters are guaranteed by design and are not tested.

In the following table, the capacitance parameters are listed.

Parameter Description Test Conditions Max Unit

C
C

IN
OUT

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

Parameter Description Test Conditions 32-SOIC 48-SSOP Unit

Θ

Θ

JA

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.

Figure 4. AC Test Loads

V

= 0 to 3.0V

CC

[5]

7pF

[5]

42.36 44.26 °C/W

21.41 25.56 °C/W

AC Test Conditions

Document Number: 001-06422 Rev. *H Page 8 of 18

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CY14B256L

AC Switching Characteristics

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Notes

6. WE

must be HIGH during SRAM Read cycles.

7. Device is continuously selected with CE

and OE both Low.

8. Measured ±200 mV from steady state output voltage.

9. HSB

must remain HIGH during SRAM Read and Write Cycles.

SRAM Read Cycle

Parameter

Cypress

Parameter

t

ACE

[6]

t

RC

[7]

t

AA

t

DOE

[7]

t

OHA

[8]

t

LZCE

[8]

t

HZCE

[8]

t

LZOE

[8]

t

HZOE

[5]

t

PU

[5]

t

PD

Alt

t

ELQV

t

AVAV, tELEH

t

AVQV

t

GLQV

t

AXQX

t

ELQX

t

EHQZ

t

GLQX

t

GHQZ

t

ELICCH

t

EHICCL

Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 12 15 20 ns
Output Hold After Address Change 3 3 3 ns
Chip Enable to Output Active 3 3 3 ns
Chip Disable to Output Inactive 10 13 15 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns

Switching Waveforms

Figure 5. SRAM Read Cycle 1: Address Controlled

Description

25 ns 35 ns 45 ns

Min Max Min Max Min Max

[6, 7, 9]

Unit

Document Number: 001-06422 Rev. *H Page 9 of 18

Figure 6. SRAM Read Cycle 2: CE Contro lled

[6, 9]

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CY14B256L

SRAM Write Cycle

t

WC

t

SCE

t

HA

t

AW

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

t

WC

ADDRESS

t

SA

t

SCE

t

HA

t

AW

t

PWE

t

SD

t

HD

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

10.If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

11.

CE

or WE must be greater than VIH during address transitions.

Parameter

Cypress

Parameter

t

WC

t

PWE

t

SCE

t

SD

t

HD

t

AW

t

SA

t

HA

[8,10]

t

HZWE

[8]

t

LZWE

t
t
t
t
t
t
t
t
t
t

Alt

AVAV
WLWH, tWLEH
ELWH, tELEH
DVWH, tDVEH
WHDX, tEHDX
AVWH, tAVEH
AVWL, tAVEL
WHAX, tEHAX
WLQZ
WHQX

Switching Waveforms

25 ns 35 ns 45 ns

Description

Min Max Min Max Min Max

Unit

Write Cycle Time 25 35 45 ns
Write Pulse Width 20 25 30 ns
Chip Enable To End of Write 20 25 30 ns
Data Setup to End of Write 10 12 15 ns
Data Hold After End of Write 0 0 0 ns
Address Setup to End of Write 20 25 30 ns
Address Setup to Start of Write 0 0 0 ns
Address Hold After End of Write 0 0 0 ns
Write Enable to Output Disable 10 13 15 ns
Output Active After End of Write 3 3 3 ns

Figure 7. SRAM Write Cycle 1: WE Controlled

[10, 11]

Document Number: 001-06422 Rev. *H Page 10 of 18

Figure 8. SRAM Write Cycle 2: CE Controlled

[10, 11]

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CY14B256L

AutoStore or Power Up RECALL

V

CC

V

SWITCH

t

STORE

t

STORE

t

HRECALL

t

HRECALL

AutoStore

POWER-UP RECALL

Read & Write Inhibited

STORE occurs only
if a SRAM write
has happened

No STORE occurs
without atleast one
SRAM write

t

VCCRISE

Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below V

SWITCH

Notes

12.t

HRECALL

starts from the time VCC rises above V

SWITCH

.

13.If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.

14.Industrial grade devices requires 15 ms max.

Parameter Alt Description

t

HRECALL

t

STORE

V

SWITCH

t

VCCRISE

[12]

[13, 14]

t

RESTORE

t

HLHZ

Power up RECALL Duration 20 ms
STORE Cycle Duration 12.5 ms
Low Voltage Trigger Level 2.65 V
VCC Rise Time 150

Switching Waveforms

Figure 9. AutoStore/Power Up RECALL

CY14B256L

Min Max

Unit

μ

s

Document Number: 001-06422 Rev. *H Page 11 of 18

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CY14B256L

Software Controlled STORE/RECALL Cycle

t

RC

t

RC

t

SA

t

SCE

t

HA

t

STORE

/ t

RECALL

DATA VALID

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

CE

OE

DQ (DATA)

t

RC

t

RC

6#SSERDDA1#SSERDDA

ADDRESS

t

SA

t

SCE

t

HA

t

STORE

/ t

RECALL

DATA VALID

DATA VALID

HIGH IMPEDANCE

CE

OE

DQ (DATA)

Notes

15.The software sequence is clocked on the falling edge of CE

controlled READs or OE controlled READs.

16.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

The software controlled STORE/RECALL cycle follows.

Parameter Alt Description

[16]

t

RC

t

SA

t

CW

t

HA

t

RECALL

t

AVAV

t

AVEL

t

ELEH

t

GHAX, tELAX

STORE/RECALL Initiation Cycle Time 25 35 45 ns
Address Setup Time 0 0 0 ns
Clock Pulse Width 20 25 30 ns
Address Hold Time 1 1 1 ns
RECALL Duration 120 120 120

[15, 16]

25 ns 35 ns 45 ns

Min Max Min Max Min Max

Unit

μ

s

Switching Waveforms

Figure 10. CE Controlled Software STORE/RECALL Cycle

Figure 11. OE Controlled Software STORE/RECALL Cycle

[16]

[16]

Document Number: 001-06422 Rev. *H Page 12 of 18

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CY14B256L

Hardware STORE Cycle

$GGUHVV $GGUHVV $GGUHVV $GGUHVV

6RIW6HTXHQFH

&RPPDQG

W

66

W

66

&(

$GGUHVV

9

&&

W

6$

W

&:

6RIW6HTXHQFH

&RPPDQG

W

&:

Notes

17.R ead and Write cycles in progress before HSB

are given this amount of time to complete.

18.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to eff ectively register command.

19.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.

Parameter Alt Description

t

PHSB

t

DELAY

[18, 19]

t

ss

[17]

t

HLHX

t

HLQZ , tBLQZ

Hardware STORE Pulse Width 15 ns
Time Allowed to Complete SRAM Cycle 1 70
Soft Sequence Processing Time 70 us

Switching Waveforms

Figure 12. Hardware STORE Cycle

CY14B256L

Min Max

Unit

μ

s

[18, 19]

Figure 13. Soft Sequence Processing

Document Number: 001-06422 Rev. *H Page 13 of 18

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CY14B256L

Ordering Information

Option:
T-Tape and Reel
Blank - Std.

Speed:
25 - 25 ns
35 - 35 ns

Data Bus:
L - x8

Density:
256 - 256 Kb

Voltage:

Cypress

Part Numbering Nomenclature
CY 14 B 256 L- SZ 25 X C T

E - 5.0V

nvSRAM

14 - AutoStore + Software Store + Hardware Store

Temperature:
C - Commercial (0 to 70°C)

Pb-Free

45 - 45 ns

I - Industrial (-40 to 85°C)

Package:
SZ - 32-SOIC
SP - 48-SSOP

Speed

(ns)

25 CY14B256L-SZ25XCT 51-85127 32-pin SOIC Commercial

35 CY14B256L-SZ35XCT 51-85127 32-pin SOIC Commercial

Ordering Code Package Diagram Package Type

CY14B256L-SZ25XC 51-85127 32-pin SOIC
CY14B256L-SP25XCT 51-85061 48-pin SSOP
CY14B256L-SP25XC 51-85061 48-pin SSOP
CY14B256L-SZ25XIT 51-85127 32-pin SOIC Industrial
CY14B256L-SZ25XI 51-85127 32-pin SOIC
CY14B256L-SP25XIT 51-85061 48-pin SSOP
CY14B256L-SP25XI 51-85061 48-pin SSOP

CY14B256L-SZ35XC 51-85127 32-pin SOIC
CY14B256L-SP35XCT 51-85061 48-pin SSOP
CY14B256L-SP35XC 51-85061 48-pin SSOP
CY14B256L-SZ35XIT 51-85127 32-pin SOIC Industrial
CY14B256L-SZ35XI 51-85127 32-pin SOIC
CY14B256L-SP35XIT 51-85061 48-pin SSOP
CY14B256L-SP35XI 51-85061 48-pin SSOP

Operating

Range

Document Number: 001-06422 Rev. *H Page 14 of 18

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CY14B256L

Ordering Information

51-85058 *A

PIN 1 ID

SEATING PLANE

116

17 32

DIMENSIONS IN INCHES[MM]

MIN.
MAX.

0.292[7.416]

0.299[7.594]

0.405[10.287]

0.419[10.642]

0.050[1.270]
TYP.

0.090[2.286]

0.100[2.540]

0.004[0.101]

0.0100[0.254]

0.006[0.152]

0.012[0.304]

0.021[0.533]

0.041[1.041]

0.026[0.660]

0.032[0.812]

0.004[0.101]

REFERENCE JEDEC MO-119

PART #

S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.

0.014[0.355]

0.020[0.508]

0.810[20.574]

0.822[20.878]

51-85127-*A

Speed

(ns)

Ordering Code Package Diagram Package Type

45 CY14B256L-SZ45XCT 51-85127 32-pin SOIC Commercial

CY14B256L-SZ45XC 51-85127 32-pin SOIC
CY14B256L-SP45XCT 51-85061 48-pin SSOP
CY14B256L-SP45XC 51-85061 48-pin SSOP
CY14B256L-SZ45XIT 51-85127 32-pin SOIC Industrial
CY14B256L-SZ45XI 51-85127 32-pin SOIC
CY14B256L-SP45XIT 51-85061 48-pin SSOP
CY14B256L-SP45XI 51-85061 48-pin SSOP

All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts

Operating

Range

Package Diagrams

Figure 14. 32-Pin (300 Mil) SOIC (51-85127)

Document Number: 001-06422 Rev. *H Page 15 of 18

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CY14B256L

Package Diagrams

51-85061-*C

(continued)

Figure 15. 48-Pin (300 mil) Shrunk Small Outline Package (51-85061)

Document Number: 001-06422 Rev. *H Page 16 of 18

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CY14B256L

Document History Page

Document Title: CY14B256L 256 Kbit (32K x 8) nvSRAM
Document Number: 001-06422

Rev. ECN No.

Submission

Date

** 425138 See ECN TUP New data sheet
*A 437321 See ECN TUP Show data sheet on External Web
*B 471966 See ECN TUP Changed V

*C 503277 See ECN PCI Changed from “Advance” to “Preliminary”

*D 597004 See ECN TUP Removed V

*E 696097 See ECN VKN Added footnote 6 related to HSB. Changed t
*F 1349963 See ECN SFV Changed from Preliminary to Final. Updated Ordering Information Table

*G 2483006 See ECN GVCH/PYRS Changed tolerance from +15%, -10% to +20%, -10%

*H 2625139 01/30/09 GVCH/PYRS Updated “features”

Orig. of
Change

Description of Change

from 2.2V to 2.0V
Changed t
Changed Endurance from one million cycles to 500K cycles

IH(min)

from 60 μs to 50 μs

RECALL

Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information

Changed the term “Unlimited” to “Infinite”
Changed endurance from 500K cycles to 200K cycles
Device operation: Tolerance limit changed from + 20% to + 15% in the
Features Section and Operating Range Table
Removed Icc
Changed V
Added temperature specification to data retention - 20 years at 55
Changed the max value of Vcap storage capacitor from 120

values from the DC table for 25 ns and 35 ns industrial grade

1

SWITCH(min)

from 2.55V to 2.45V

μ

F to 57 μF

Updated Part Nomenclature Table and Ordering Information Table

specification from the AutoStore/Power Up RECALL

specification of 70 μs in the Hardware STORE Cycle table

from 57 μF to 120 μF

to t

GLAX

GHAX

table
Changed t
Added t
Removed t

DELAY(max)

Changed t
Changed V

SWITCH(min)

specification from 20 ns to 1 ns

GLAX

specification

HLBL

specification from 70 μs (min) to 70 μs (max)

SS

CAP(max)

Changed Operating voltage range from 2.7V-3.45V to 2.7V-3.6V.

Updated WE
Added data retention at 55

pin description

o

C
Added best practices
Added I
Updated V
Removed footnote 4 and 5

spec for 25ns and 35ns access speed for industrial temperate

CC1

from Vcc+0.3 to Vcc+0.5

IH

Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter t
Changed t
Renamed t
Updated Figure 11 and 12
Renamed t
Updated Figure 12 and 13

RECALL

GLAX

HLHX

to t
to t

to t

AS

from 50us to 120us (Including tss of 70us)

HA

PHSB

SA

°

C

Document Number: 001-06422 Rev. *H Page 17 of 18

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CY14B256L

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales

Products

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USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2006- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used fo r
medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express written agreement w ith Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify , crea te deri vative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress
integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-06422 Rev. *H Revi sed January 30, 2009 Page 18 of 18

AutoStore and Quant umTrap ar e registered tradem arks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be the trademarks of their respective
holders.

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