Cypress CY14B256K User Manual
CY14B256K
256 Kbit (32K x 8) nvSRAM with Real Time Clock
Features
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
QuantumTrap
512 X 512
STORE
RECALL
COLUMN IO
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
13
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
RTC
MUX
A
14
-
A
0
x
1
x
2
INT
V
RTCbat
V
RTCcap
A
11
Logic Block Diagram
■ 25 ns, 35 ns, and 45 ns access times
■ Pin compatible with STK17T88
■ Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
❐ Low power, 350 nA RTC current
❐ Capacitor or battery backup for RTC
■ Watchdog timer
■ Clock alarm with programmable interrupts
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumT rap™ initiated by software, device pin, or
on power down
■ RECALL to SRAM initiated by software or on power up
■ Infinite READ, WRITE, and RECALL cycles
■ High reliability
❐ Endurance to 200K cycles
❐ Data retention: 20 years at 55°C
■ Single 3V operation with tolerance of +20%, -10%
■ Commercial and industrial temperature
■ 48-Pin SSOP (ROHS compliant)
Functional Description
The Cypress CY14B256K combines a 256 Kbit nonvolatile static
RAM with a full-featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvola tile data resides in
the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06431 Rev. *H Revised February 24, 2009
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CY14B256K
Pin Configurations
V
CAP
A
14
A
12
A
7
A
6
A
5
A
4
V
CC
HSB
WE
A
13
A
8
A
9
A
11
OE
A
10
DQ
DQ7
6
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
INT
NC
NC
NC
V
SS
NC
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
NC
NC
NC
NC
V
SS
NC
V
CC
48-SSOP
Top View
(Not To Scale)
NC
V
RTCbat
X
1
X
2
V
RTCcap
NC
Figure 1. 48-Pin SSOP
Pin Definitions
Pin Name Alt IO Type Description
A
0–A14
DQ0-DQ7 Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
NC No Connect No Connects. This pin is not connected to the die.
WE
CE
OE
X
1
X
2
V
RTCcap
V
RTCbat
INT Output Interrupt Output. It is programmed to respond to the clock alarm, the watchdog timer, and the
V
SS
V
CC
HSB
V
CAP
Document Number: 001-06431 Rev. *H Page 2 of 28
W
E
G
Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE
Output Crystal Connection. Drives crystal on start up.
Input Crystal Connection for 32.768 kHz Crystal.
Power Supply Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if V
Power Supply Battery Supplied Backup RTC Supply Voltage. (Left unconnected if V
power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain).
Ground Ground for the Device. It is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When low, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin HIGH if not connected (connection optional).
Power Supply AutoStore Capacitor . Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
high causes the IO pins to tri-state.
RTCbat
is used)
RTCcap
is used)
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CY14B256K
Device Operation
V
CC
V
CC
V
CAP
V
CAP
WE
10k Ohm
0.1 F
U
The CY14B256K nvSRAM consists of two functional
components paired in the same physical cell. The components
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2. AutoStore Mode
pin from VCC. A STORE
CAP
capacitor.
CAP
are SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM READ and WRITE operations are inhibited. The
CY14B256K supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the nonvolatile cells and up to 200K STORE operations.
See the “Truth Table For SRAM Operations” on page22 for a
complete description of read and write modes.
SRAM READ
The CY14B256K performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of t
8 on page 17). If the READ is initiated by CE
are valid at t
Figure 9 on page 17). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE
or HSB is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are LOW and
is HIGH. The address inputs are stable before entering the
HSB
WRITE cycle and must remain stable until either CE
HIGH at the end of the cycle. The data on the common IO pins
DQ
0–7
the end of a WE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE
LOW, internal circuitry turns off the output buffers t
goes LOW.
AutoStore® Operation
The CY14B256K stores data to nvSRAM using one of the three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256K.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
determines which of the 32,752 data bytes are
0-14
(see the section Figure
AA
or OE, the outputs
ACE
or at t
, whichever is later (see the section
DOE
access time without the need for
AA
or WE goes
is written into the memory if the data is valid t
controlled WRITE or before the end of a CE
HZWE
pin. This stored
pin drops below V
CC
CAP
SWITCH
before
SD
is left
after WE
to
CC
, the part
Figure 2 shows the proper connection of the storage capacitor
(V
) for automatic store operation. Refer to DC Electrical
CAP
Characteristics on page 15 for the size of the V
on the V
chip. A pull up should be placed on WE
pin is driven to 5V by a charge pump internal to the
CAP
to hold it inactive during
power up. This pull up is only effective if the WE
. The voltage
CAP
signal is tri-state
during power up. Many MPUs tri-state their controls on power up.
Verify this when using the pull up. When the nvSRAM comes out
of power-on-recall, the MPU must be active or the WE
held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB
signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B256K provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
low, the CY14B256K conditionally initiates a STORE operation
after t
the SRAM takes place since the last STORE or RECALL cycle.
. An actual STORE cycle only begins if a WRITE to
DELAY
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin is externally
pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven low by any means, are given time to complete
before the STORE operation is initiated. After HSB
the CY14B256K continues SRAM operations for t
pin is used to
pin is driven
goes LOW,
. During
DELAY
Document Number: 001-06431 Rev. *H Page 3 of 28
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CY14B256K
t
, multiple SRAM READ operations take place. If a WRITE
DELAY
is in progress when HSB
to complete. However, any SRAM WRITE cycles requested after
HSB
goes LOW are inhibited until HSB returns HIGH.
is pulled LOW, it allows a time, t
DELAY
During any STORE operation, regardless of how it is initiated,
the CY14B256K continues to drive the HSB
pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14B256K remains disabled until the
HSB
pin returns HIGH.
If HSB
is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC<VSWITCH
V
again exceeds the sense voltage of V
CC
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When
, a RECALL
SWITCH
HRECALL
to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B256K software
STORE cycle is initiated by executing sequential CE
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed, followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further READs and
WRITEs are inhibited untill the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If it intervenes, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F , Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE
controlled READs. After the sixth address in the sequence is
OE
controlled READs or
entered, the STORE cycle commences and the chip is disabled.
controlled
It is important to use READ cycles and not WRITE cycles in the
,
sequence, although it is not necessary that OE
valid sequence. After the t
is activated again for READ and WRITE operations.
cycle time is fulfilled, the SRAM
STORE
be LOW for a
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then the nonvolatile information is transferred into
the SRAM cells. After the t
ready for READ and WRITE operations. The RECALL operation
cycle time, the SRAM is again
RECALL
in no way alters the data in the nonvolatile elements.
Data Protection
The CY14B256K protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
is less than V
CC
SWITCH
.
If the CY14B256K is in a WRITE mode (both CE and WE are low)
at power up after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on CE or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The CY14B256K is a high speed memory and must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
and VSS using leads and traces that are as short
CC
Document Number: 001-06431 Rev. *H Page 4 of 28
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CY14B256K
Low Average Active Power
CMOS technology provides the CY14B256K the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ and/or WRITE cycle time. Worst case current
consumption is shown for commercial temperature range, V
3.6V, and chip enable at maximum frequency. Only standby
current is drawn when the chip is disabled. The overall average
current drawn by the CY14B256K depends on the following
items:
1. 1The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. The operating temperature
5. The V
CC
level
6. IO loading
Figure 3. Current versus Cycle Time
CC
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
=
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration and
cold or warm boot status must always program a unique NV
pattern (for example, complex 4-byte pattern of 46 E6 49 53
hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■ The OSCEN bit in the Calibration register at 0x7FF8 should be
set to 1 to preserve battery life when the system is in storage
(see Stopping and Starting the Oscillator on page 7).
■ The Vcap value specified in this data sheet includes a minimum
and a maximum value size. The best practice is to meet this
requirement and not exceed the maximum Vcap value because
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
Vcap value to make sure there is extra store charge should
discuss their Vcap size selection with Cypress.
Document Number: 001-06431 Rev. *H Page 5 of 28
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CY14B256K
Table 1. Mode Selection
Notes
1. The six consecutive address locations are in the order listed. WE
is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256K, only the lower 14 lines are used to control software modes.
3. IO state depends on the state of OE
. The IO table shown is based on OE Low.
CE WE OE
A13–A0 Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
Active
CC2
[1, 2, 3]
[1, 2, 3]
Document Number: 001-06431 Rev. *H Page 6 of 28
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CY14B256K
Real Time Clock Operation
nvTIME Operation
The CY14B256K consists of internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. RTC registers
use the last 16 address locations of the SRAM. Internal doubl e
buffering of the clock and the clock and timer information
registers prevent accessing transitional internal clock data
during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or clock accuracy of
the internal clock while accessing clock data. Clock and Alarm
registers store data in BCD format.
The RTC register addresses for CY14B256K range from 0x7FF0
to 0x7FFF. Refer to RTC Register Map[5, 6] on page 11 and
Register Map Detail on page 12 for detailed description.
Clock Operations
The Clock registers maintain time up to 9,999 years in one
second increments. The user sets the time to any calendar time
and the clock automatically keeps track of days of the week,
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions that are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user should stop
internal updates to the CY14B256K time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x7FF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while
the internal clock continues to run. After a ‘0’ is written to the read
bit (‘R’), all CY14B256K registers are simultaneously updated
within 20 ms.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x7FF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers in 24 hour BCD format. The time written is referred to
as the “Base Time”. This value is stored in nonvolatile registers
and used in the calculation of the current time. Resetting the
write bit to ‘0’ transfers the register values to the actual clock
counters, after which the clock resumes normal operation.
Backup Power
The RTC in the CY14B256K is intended for permanently
powered operation. The V
depending on whether a capacitor or battery is chosen for the
application. When the primary power, V
V
the device switches to the backup power supply.
SWITCH
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
RTCcap
or V
pin is connected
RTCbat
, fails and drops below
CC
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the no nvolatile
elements when power was lost.
During backup operation, the CY14B256K consumes a
maximum of 300 nanoamps at 2 volts. The user should choose
capacitor or battery values according to the application. Backup
time values based on maximum current specifications are shown
in the following table. Nominal backup times are approximately
three times longer.
T able 2. RTC Backup Time
Capacitor Value Backup Time
0.1F 72 hours
0.47F 14 days
1.0F 30 days
Using a capacitor has the advantage of recharging the backup
source each time the system is powered up. If a battery is used,
a 3V lithium is recommended and the CY14B256K sources
current only from the battery when the primary power is removed.
The battery is not, however, recharged at any time by the
CY14B256K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FF8 controls the
enable and disable of the oscillator. This active LOW bit is
nonvolatile and is shipped to customers in the “enabled” (set to
0) state. To preserve the battery life when the system is in
storage, OSCEN bit must be set to ‘1’. This turns off the oscillator
circuit, extending the battery life. If the OSCEN bit goes from
disabled to enabled, it takes approximately 5 seconds (10
seconds maximum) for the oscillator to start.
While system power is off, if the voltage on the backup supply
(V
the oscillator may fail.The CY14B256K has the ability to dete ct
oscillator failure when system power is restored. This is recorded
in the OSCF (Oscillator Failed bit) of the Flags register at
address 0x7FF0. When the device is powered on (V
above V
If the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to “1”. The system must check
for this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see “Setting the Clock” on page 7), which is
the value last written to the time keeping registers. The Control
or Calibration registers and the OSCEN bit are not affected by
the “oscillator failed” condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit “W” (in the flags register at
0x7FF0) to “1” to enable writes to the Flag register. Write a “0” to
the OSCF bit and then reset the write bit to “0” to disable writes.
RTCcap
or V
SWITCH
) falls below their respective minimum level,
RTCbat
), the OSCEN bit is checked for “enabled” status.
CC
goes
Document Number: 001-06431 Rev. *H Page 7 of 28
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CY14B256K
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystal oscillators typically
have an error of +
employs a calibration circuit that improves the accuracy to +1/–2
ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds
per month.
The
calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x7FF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.
Calibration occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the 64
minute cycle is modified. If a binary 6 is loade d, the first 12 ar e
affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x7FF0) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x7FF0) to “1” to enable writes to the Flag register. W rite a value
to CAL, and then reset the write bit to “0” to disable writes.
20ppm to +35ppm. However, CY14B256K
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x7FF1-5) with the corresponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding fie ld is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an a lar m ev ent: by re adi ng t he AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x7FF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags or
control register clears the alarm flag bit (and all others). A
hardware interrupt pin may also be used to detect an alarm
event.
Note CY14B256K requires the alarm match bit for seconds
(0x7FF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag
and Interrupt.
Alarm registers are not nonvolatile and, therefore, need to be
reinitialized by software on power up. To set, clear or enable an
alarm, set the ‘W’ bit (in Flags Register - 0x7FF0) to ‘1’ to enable
writes to Alarm Registers. After writing the alarm value, clear the
‘W’ bit back to “0” for the changes to take effect.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x7FF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDF flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 4. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. The flag is set upon a
watchdog time out and cleared when the user reads the Flags or
Control registers. If the watchdog time out occurs, the user also
enables an optional interrupt source to drive the INT pin.
Document Number: 001-06431 Rev. *H Page 8 of 28
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CY14B256K
Figure 4. Watchdog Timer Block Diagram
1 Hz
Oscillator
Clock
Divider
Counter
Zero
Compare
WDF
WDS
Load
Register
WDW
D
Q
Q
Watchdog
Register
write to
Watchdog
Register
32 Hz
32,768 KHz
Power Monitor
The CY14B256K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protect s the memory f rom low
V
access. The power monitor is based on an internal band gap
CC
reference circuit that compares the V
threshold.
voltage to V
CC
As described in the “AutoStore® Operation” on page 3, when
V
operation is initiated from SRAM to the nonvolatile elements,
is reached as VCC decays from power loss, a data store
SWITCH
securing the last SRAM data state. Power is also switched from
V
to the backup supply (battery or capacitor) to operate the
CC
RTC oscillator.
When operating from the backup source, read and write opera-
tions to nvSRAM are inhibited and the clock functions are not
available to the user. The clock continues to operate in the
background. The updated clock data is available to the user
t
HRECALL
“AutoStore or Power Up RECALL” on page 19).
delay after VCC is restored to the device (see
Interrupts
The CY14B256K has a Flags register, Interrupt register and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog ti mer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x7FF6). In addition, each has an associated flag bit in
the Flags register (0x7FF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised b y one of the
three sources and the respective interrupt enable bit in Interrupts
SWITCH
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the Flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupt Register
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in Flags register.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flagin Flags register.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in Flags
register.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when V
is active LOW and the drive mode is open drain. Active LOW
is greater than V
CC
. When set to a ‘0’, the INT pin
SWITCH
(open drain) is operational even in battery backup mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the Flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for Pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the Flags register is read. If the INT pin is used as a
host reset, then the Flags or Control register is not read during a
reset.
Flags Register
The Flag register has three flag bits: WDF , AF , and PF, which can
be used to generate an interrupt. These flags are set by the
watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable inter-
rupts to be informed when a flag is set. These flags are automatically reset once the register is read. The flags register is
automatically loaded with the value 00h on power up (except for
the OSCF bit. See “Stopping and Starting the Oscillator” on
page 7.)
Document Number: 001-06431 Rev. *H Page 9 of 28
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