Cypress CY14B104NA, CY14B104LA User Manual
PRELIMINARY
CY14B104LA, CY14B104NA
4 Mbit (512K x 8/256K x 16) nvSRAM
Features
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Logic Block Diagram
[1, 2, 3]
Notes
1. Address A
0
- A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ
0
- DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE
and BLE are applicable for x16 configuration only.
■
20 ns, 25 ns, and 45 ns access times
■
Internally organized as 512K x 8 (CY14B104LA) or 256K x 16
(CY14B104NA)
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap® nonvolatile elements initiated by
software, device pin, or AutoStore
■
RECALL to SRAM initiated by software or power up
■
Infinite Read, Write, and Recall cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention
■
Single 3V +20%, -10% operation
■
Commercial and industrial temperatures
■
48-ball FBGA and 44/54-pin TSOP-II packages
■
Pb-free and RoHS compliance
®
on power down
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
organized as 512K bytes of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-49918 Rev. *A Revised March 11, 2009
[+] Feedback
PRELIMINARY
CY14B104LA, CY14B104NA
Pinouts
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
A
17
A
2
A
1
NC
V
CC
DQ
4
NC
DQ
5
DQ
6
NC
DQ
7
NC
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
A
18
NC
DQ
1
Top View
(x8)
[4]
[5]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
BHE
NC
A
17
A
2
A
1
BLE
V
CC
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
NC
DQ
11
(not to scale)
Top View
(x16)
[4]
[5]
(not to scale)
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
6. HSB
pin is not available in 44-TSOP II (x16) package.
NC
A
8
NC
NC
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
A
18
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A
10
NC
WE
DQ
7
HSB
NC
V
SS
V
CC
V
CAP
NC
(x8)
[4]
[5]
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
WE
DQ
7
A
0
V
SS
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
(x16)
(x16)(x8)
[6]
Figure 1. Pin Diagram - 48 FBGA
Figure 2. Pin Diagram - 44 Pin TSOP II
Document #: 001-49918 Rev. *A Page 2 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
Pinouts
A
17
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
DQ
3
DQ
2
DQ
1
DQ
0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(
not to scale)
OE
CE
V
CC
NC
V
SS
NC
A
9
NC
NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
(x16)
[4]
[5]
(continued)
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
Pin Definitions
Pin Name I/O Type Description
A0 – A
18
A0 – A
17
DQ
– DQ7Input/Output Bidirectional Data I/O Lines for x8 Confi guration. Used as input or output lines depending on
0
DQ
– DQ
0
15
WE
CE
OE
BHE
BLE
V
SS
V
CC
[6]
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Document #: 001-49918 Rev. *A Page 3 of 23
Input Address Inputs Used to Select one of the 524,288 bytes of the n vSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
Input Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground Gr ound for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
is driven HIGH for short time with standard output high current.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
HIGH.
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PRELIMINARY
CY14B104LA, CY14B104NA
Device Operation
0.1uF
Vcc
10kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
The CY14B104LA/CY14B104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104LA/CY14B104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the Truth Table For SRAM Operations on page
16 for a complete description of read and write modes.
SRAM Read
The CY14B104LA/CY14B104NA performs a read cycle when
CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
data output repeatedly responds to address changes within the
ACE
tAA access time without the need for transitions on any control
input pins. This remains valid until another address chan ge or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0-18
or at t
or A
DOE
determines which of the 524,288
0-17
, whichever is later (read cycle 2). The
AA
Characteristics on page 8 for the size of V
the V
up should be placed on WE
pin is driven to V
CAP
This pull up is effective only if the WE
by a regulator on the chip. A pull
CC
to hold it inactive during power up.
signal is tri-state during
. The voltage on
CAP
power up. Many MPUs tri-state their controls on power up. This
should be verified when using the pull up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB
signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE
or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
are written into the memory if the dat a is valid tSD before the end
of a WE
write. The Byte Enable inputs (BHE
controlled write or before the end of an CE controlled
, BLE) determine which bytes
are written, in the case of 16-bit words. It is recommended that
OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE
circuitry turns off the output buffers t
is left LOW, internal
after WE goes LOW.
HZWE
AutoStore Operation
The CY14B104LA/CY14B104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
Store activated by HSB; Software Store activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104LA/CY14B104NA.
During a normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
pin drops below V
CC
pin from VCC. A STORE
CAP
Figure 4 shows the proper conne ction of the storage capacitor
) for automatic store operation. Refer to DC Electrical
(V
CAP
pin. This stored
CAP
, the part
SWITCH
capacitor.
CAP
0–15
CC
Hardware STORE Operation
The CY14B104LA/CY14B104NA provides the HSB
control and acknowledge the STORE operations. Use the HSB
pin to request a hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B104LA/CY14B104NA conditionally
initiates a STORE operation after t
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete be fore
the STORE operation is initiated. After HSB
CY14B104LA/CY14B104NA continues SRAM operations for
t
. If a write is in progress when HSB is pulled LOW it is
DELAY
enabled a time, t
cycles requested after HSB
returns HIGH. In case the write latch is not set, HSB is not driven
to
LOW by the CY14B104LA/CY14B104NA. But any SRAM read
to complete. However, any SRAM write
DELAY
goes LOW are inhibited until HSB
and write cycles are inhibited until HSB
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B104LA/CY14B104NA continues to drive the HSB
LOW, releasing it only when the STORE is complete. When the
STORE operation is completed, the CY14B104LA/CY14B104NA
. An actual STORE cycle
DELAY
pin also acts as an open
goes LOW, the
is returned HIGH by MPU
[6]
pin to
pin
Document #: 001-49918 Rev. *A Page 4 of 23
[+] Feedback
PRELIMINARY
CY14B104LA, CY14B104NA
remains disabled until the HSB
Notes
7. While there are 19 address lines on the CY14B104LA (18 address lines on the CY14B104NA) , only the 13 address lines (A
14
- A2) are used to control software modes.
Rest of the address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC<VSWITCH
again exceeds the sense voltage of V
V
CC
cycle is automatically initiated and takes t
During this time, HSB
), an internal RECALL request is latched. When
, a RECALL
SWITCH
is driven LOW by the HSB driver.
HRECALL
to complete.
Software ST ORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B104LA/CY14B104NA
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
The software sequence may be clocked with CE
controlled reads. After the sixth address in the sequence
or OE
controlled reads
is entered, the STORE cycle commences and the chip is
disabled. HSB
is driven LOW. It is important to use read cycles
and not write cycles in the sequence, although it is not necessary
that OE be LOW for a valid sequence. After the t
is fulfilled, the SRAM is activated again for the read and w rite
STORE
cycle time
operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
controlled read operations must be
cycle time, the SRAM is again
RECALL
CE WE OE, BHE, BLE
[3]
A15 - A
[7]
0
Mode I/O Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Document #: 001-49918 Rev. *A Page 5 of 23
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[8]
[+] Feedback
PRELIMINARY
CY14B104LA, CY14B104NA
Table 1. Mode Selection (continued)
CE WE OE, BHE, BLE
[3]
L H L 0x4E38
L H L 0x4E38
L H L 0x4E38
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
0
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
[7]
AutoStore Enable
Nonvolatile Store
Mode I/O Power
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active I
Output High Z
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
A15 - A
Recall
Data Protection
The CY14B104LA/CY14B104NA protects data from corruption
during low voltage conditions by inhibiting all externa lly initiated
STORE and write operations. The low voltage condition is
detected when V
CY14B104LA/CY14B104NA is in a write mode (both CE
< V
CC
SWITCH
. If the
are LOW) at power up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after t
active). This protects against inadvertent writes during power up
(HSB to output
LZHSB
or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Active
Active
[8]
[8]
CC2
[8]
and WE
Document #: 001-49918 Rev. *A Page 6 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The V
CAP
value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum V
the nvSRAM internal algorithm calculates V
discharge time based on this max V
CAP
want to use a larger V
value to make sure there is extra
CAP
store charge and store time should discuss their V
CAP
value because
CAP
charge and
value. Customers that
CAP
size
selection with Cypress to understand any impact on the V
voltage level at the end of a t
RECALL
period.
CAP
Document #: 001-49918 Rev. *A Page 7 of 23
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