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CY14B104LA
User Manual
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Cypress CY14B104NA, CY14B104LA User Manual

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PRELIMINARY
CY14B104LA, CY14B104NA
4 Mbit (512K x 8/256K x 16) nvSRAM
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Logic Block Diagram
[1, 2, 3]

Notes
1. Address A
0
- A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ
0
- DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE
and BLE are applicable for x16 configuration only.
■
20 ns, 25 ns, and 45 ns access times
■
Internally organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA)
■
Hands off automatic STORE on power down with only a small capacitor
■
STORE to QuantumTrap® nonvolatile elements initiated by software, device pin, or AutoStore
■
RECALL to SRAM initiated by software or power up
■
Infinite Read, Write, and Recall cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention
■
Single 3V +20%, -10% operation
■
Commercial and industrial temperatures
■
48-ball FBGA and 44/54-pin TSOP-II packages
■
Pb-free and RoHS compliance
®
on power down

Functional Description

The Cypress CY14B104LA/CY14B104NA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600 Document #: 001-49918 Rev. *A Revised March 11, 2009
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PRELIMINARY
CY14B104LA, CY14B104NA
Pinouts
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
A
17
A
2
A
1
NC
V
CC
DQ
4
NC
DQ
5
DQ
6
NC
DQ
7
NC
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
A
18
NC
DQ
1
Top View
(x8)
[4]
[5]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
BHE
NC
A
17
A
2
A
1
BLE
V
CC
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
NC
DQ
11
(not to scale)
Top View
(x16)
[4]
[5]
(not to scale)
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
6. HSB
pin is not available in 44-TSOP II (x16) package.
NC
A
8
NC NC
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
A
18
NC
1 2
3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A
10
NC
WE
DQ
7
HSB
NC
V
SS
V
CC
V
CAP
NC
(x8)
[4]
[5]
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
A
16
A
17
1
2 3
4 5 6
7
8
9 10
11 12 13 14
15 16 17 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
WE
DQ
7
A
0
V
SS
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
(x16)
(x16)(x8)
[6]
Figure 1. Pin Diagram - 48 FBGA
Figure 2. Pin Diagram - 44 Pin TSOP II
Document #: 001-49918 Rev. *A Page 2 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
Pinouts
A
17
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
DQ
3
DQ
2
DQ
1
DQ
0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1 2
3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(
not to scale)
OE
CE
V
CC
NC
V
SS
NC
A
9
NC
NC
NC
NC NC
NC
54 53 52 51
49
50
HSB
BHE BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
(x16)
[4]
[5]
(continued)
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
Pin Definitions
Pin Name I/O Type Description
A0 – A
18
A0 – A
17
DQ
– DQ7Input/Output Bidirectional Data I/O Lines for x8 Confi guration. Used as input or output lines depending on
0
DQ
– DQ
0
15
WE
CE OE
BHE BLE
V
SS
V
CC
[6]
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Document #: 001-49918 Rev. *A Page 3 of 23
Input Address Inputs Used to Select one of the 524,288 bytes of the n vSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
operation. Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
Input Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location. Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE Input Byte High Enable, Active LOW. Controls DQ15 - DQ8. Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground Gr ound for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
is driven HIGH for short time with standard output high current.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
HIGH.
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PRELIMINARY
CY14B104LA, CY14B104NA

Device Operation

0.1uF
Vcc
10kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
The CY14B104LA/CY14B104NA nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B104LA/CY14B104NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the Truth Table For SRAM Operations on page 16 for a complete description of read and write modes.

SRAM Read

The CY14B104LA/CY14B104NA performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address specified on pins A data bytes or 262,144 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of t (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at t data output repeatedly responds to address changes within the
ACE
tAA access time without the need for transitions on any control input pins. This remains valid until another address chan ge or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0-18
or at t
or A
DOE
determines which of the 524,288
0-17
, whichever is later (read cycle 2). The
AA
Characteristics on page 8 for the size of V
the V up should be placed on WE
pin is driven to V
CAP
This pull up is effective only if the WE
by a regulator on the chip. A pull
CC
to hold it inactive during power up.
signal is tri-state during
. The voltage on
CAP
power up. Many MPUs tri-state their controls on power up. This should be verified when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and hardware store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB
signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE
or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ are written into the memory if the dat a is valid tSD before the end of a WE write. The Byte Enable inputs (BHE
controlled write or before the end of an CE controlled
, BLE) determine which bytes are written, in the case of 16-bit words. It is recommended that OE
be kept HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE circuitry turns off the output buffers t
is left LOW, internal
after WE goes LOW.
HZWE

AutoStore Operation

The CY14B104LA/CY14B104NA stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB; Software Store activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104LA/CY14B104NA.
During a normal operation, the device draws current from V charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation. If the voltage on the V automatically disconnects the V operation is initiated with power provided by the V
pin drops below V
CC
pin from VCC. A STORE
CAP
Figure 4 shows the proper conne ction of the storage capacitor
) for automatic store operation. Refer to DC Electrical
(V
CAP
pin. This stored
CAP
, the part
SWITCH
capacitor.
CAP
0–15
CC

Hardware STORE Operation

The CY14B104LA/CY14B104NA provides the HSB control and acknowledge the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B104LA/CY14B104NA conditionally initiates a STORE operation after t only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time to complete be fore the STORE operation is initiated. After HSB CY14B104LA/CY14B104NA continues SRAM operations for t
. If a write is in progress when HSB is pulled LOW it is
DELAY
enabled a time, t cycles requested after HSB returns HIGH. In case the write latch is not set, HSB is not driven
to
LOW by the CY14B104LA/CY14B104NA. But any SRAM read
to complete. However, any SRAM write
DELAY
goes LOW are inhibited until HSB
and write cycles are inhibited until HSB or other external source.
During any STORE operation, regardless of how it is initiated, the CY14B104LA/CY14B104NA continues to drive the HSB LOW, releasing it only when the STORE is complete. When the STORE operation is completed, the CY14B104LA/CY14B104NA
. An actual STORE cycle
DELAY
pin also acts as an open
goes LOW, the
is returned HIGH by MPU
[6]
pin to
pin
Document #: 001-49918 Rev. *A Page 4 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
remains disabled until the HSB
Notes
7. While there are 19 address lines on the CY14B104LA (18 address lines on the CY14B104NA) , only the 13 address lines (A
14
- A2) are used to control software modes.
Rest of the address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
pin returns HIGH. Leave the HSB
unconnected if it is not used.

Hardware RECALL (Power Up)

During power up or after any low power condition (V
CC<VSWITCH
again exceeds the sense voltage of V
V
CC
cycle is automatically initiated and takes t During this time, HSB
), an internal RECALL request is latched. When
, a RECALL
SWITCH
is driven LOW by the HSB driver.
HRECALL
to complete.

Software ST ORE

Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B104LA/CY14B104NA software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
The software sequence may be clocked with CE
controlled reads. After the sixth address in the sequence
or OE
controlled reads
is entered, the STORE cycle commences and the chip is disabled. HSB
is driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the t is fulfilled, the SRAM is activated again for the read and w rite
STORE
cycle time
operation.

Software RECALL

Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the t ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
controlled read operations must be
cycle time, the SRAM is again
RECALL
CE WE OE, BHE, BLE
[3]
A15 - A
[7]
0
Mode I/O Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38
0xB1C7 0x83E0 0x7C1F
0x703F
0x8B45
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
AutoStore
Disable
Document #: 001-49918 Rev. *A Page 5 of 23
Output Data Output Data Output Data Output Data Output Data Output Data
Active
[8]
[+] Feedback
PRELIMINARY
CY14B104LA, CY14B104NA
Table 1. Mode Selection (continued)
CE WE OE, BHE, BLE
[3]
L H L 0x4E38
L H L 0x4E38
L H L 0x4E38

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
0
0xB1C7 0x83E0 0x7C1F
0x703F
0x4B46
0xB1C7 0x83E0 0x7C1F
0x703F
0x8FC0
0xB1C7 0x83E0 0x7C1F
0x703F
0x4C63
[7]
AutoStore Enable
Nonvolatile Store
Mode I/O Power
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
Output Data Output Data Output Data Output Data Output Data Output Data
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
Output Data Output Data Output Data Output Data Output Data
Active I
Output High Z
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
Nonvolatile
Output Data Output Data Output Data Output Data Output Data
Output High Z
A15 - A
Recall

Data Protection

The CY14B104LA/CY14B104NA protects data from corruption during low voltage conditions by inhibiting all externa lly initiated STORE and write operations. The low voltage condition is detected when V CY14B104LA/CY14B104NA is in a write mode (both CE
< V
CC
SWITCH
. If the
are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after t active). This protects against inadvertent writes during power up
(HSB to output
LZHSB
or brown out conditions.

Noise Considerations

Refer to CY application note AN1064.
Active
Active
[8]
[8]
CC2
[8]
and WE
Document #: 001-49918 Rev. *A Page 6 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Best Practices

nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufac­turing test to ensure these system routines work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines.
■
The V
CAP
value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum V the nvSRAM internal algorithm calculates V discharge time based on this max V
CAP
want to use a larger V
value to make sure there is extra
CAP
store charge and store time should discuss their V
CAP
value because
CAP
charge and
value. Customers that
CAP
size selection with Cypress to understand any impact on the V voltage level at the end of a t
RECALL
period.
CAP
Document #: 001-49918 Rev. *A Page 7 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Maximum Ratings

Notes
9. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V
CC
= 3V. Not 100% tested.
10.The HSB
pin has I
OUT
= -2 uA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
11. V
CAP
(storage capacitor) nominal value is 68 uF.
Exceeding maximum ratings may impair the useful life of the device. These user guidelines ar e no t tested.
Storage Temperature ..................................–65°C to +150°C
Maximum Accumulated Storage T ime
At 150°C Ambient Temperature..........................1000h
At 85°C Ambient Temperature.................... ..20 Years
Ambient Temperature with
Power Applied.............................................–55°C to +150°C
Supply Voltage on V Voltage Applied to Outputs
in High-Z State...................................... –0.5V to V
Input Voltage..........................................–0.5V to Vcc + 0.5V
Relative to GND..........–0.5V to 4.1V
CC
+ 0.5V
CC
Transient Vo ltage (<20 ns) on
Any Pin to Ground Potential................ ..–2.0V to V
+ 2.0V
CC
Package Power Dissipation Capability (T
= 25°C)....................................................1.0W
A
Surface Mount Pb Soldering
Temperature (3 Seconds)...........................................+260°C
DC Output Current (1 output at a time, 1s duration)....15 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA

Operating Range

Range Ambient Temperature V
Commercial 0°C to +70°C 2.7V to 3.6V
CC
Industrial –40°C to +85°C 2.7V to 3.6V

DC Electrical Characteristics

Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter Description Test Conditions Min Max Unit
I
CC1
I
CC2
I
CC3
I
CC4
I
SB
[9]
Average VCC Current tRC = 20 ns
t
RC
t
RC
Values obtained without output loads (I
Average VCC Current during STORE
Average VCC Current at t
= 200 ns, 3V, 25°C
RC
typical Average V
during AutoStore Cycle
CAP
Current
All Inputs Don’t Care, VCC = Max Average current for duration t
All I/P cycling at CMOS levels. Values obtained without output loads (I
All Inputs Don’t Care, VCC = Max Average current for duration t
VCC Standby Current CE > (VCC – 0.2V). All others V
current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz.
I
I
V
V V V V
IX
OZ
[10]
IH
IL OH OL CAP
Input Leakage Current (except HSB
)
Input Leakage Current (for HSB
)
Off-State Output Leakage Current
Input HIGH Voltage 2.0 VCC +
Input LOW Voltage Vss – 0.5 0.8 V Output HIGH Voltage I Output LOW Voltage I
[11]
Storage Capacitor Between V
V
CC
V
CC
VCC = Max, VSS < V or WE < V
OUT OUT
Commercial 65 = 25 ns = 45 ns
OUT
= 0 mA)
Industrial 70
65 50
70 52
10 mA
STORE
35 mA
= 0 mA).
OUT
5mA
STORE
= Max, VSS < V
= Max, VSS < V
IL
< 0.2V or > (VCC – 0.2V). Standby
IN
< V
IN
CC
< V
IN
CC
< VCC, CE or OE > V
OUT
or BHE/BLE > V
IH
–1 +1 μA
–100 +1 μA
–1 +1 μA
IH
5mA
0.5
= –2 mA 2.4 V = 4 mA 0.4 V
pin and VSS, 5V Rated 61 180 μF
CAP
mA mA mA
mA mA mA
V
Document #: 001-49918 Rev. *A Page 8 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Data Retention and Endurance

3.0V
OUTPUT
5 pF
R1
R2
789Ω
3.0V
OUTPUT
30 pF
R1
R2
789Ω
for tri-state specs
577Ω
577Ω
Note
12.These parameters are guaranteed but not tested.
Parameter Description Min Unit
DATA NV
C
R
Data Retention 20 Years Nonvolatile STORE Operation 200 K

Capacitance

In the following table, the capacitance parameters are listed.
Parameter Description Test Conditions Max Unit
C C
IN OUT
Input Capacitance TA = 25°C, f = 1 MHz, Output Capacitance 7 pF
[12]
V
= 0 to 3.0V
CC
7pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.
Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient) Thermal Resistance
JC
(Junction to Case)
Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.
Figure 5. AC Test Loads
[12]
28.82 31.11 30.73 °C/W
7.84 5.56 6.08 °C/W

AC Test Conditions

Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <
Input and Output Timing Reference Levels....................1.5V
Document #: 001-49918 Rev. *A Page 9 of 23
3 ns
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PRELIMINARY
CY14B104LA, CY14B104NA

AC Switching Characteristics

Address
Data Output
Address Valid
Previous Data Valid
Output Data Valid
t
RC
t
AA
t
OHA
Notes
13.WE
must be HIGH during SRAM read cycles.
14.Device is continuously selected with CE
, OE and BHE / BLE LOW.
15.Measured ±200 mV from steady state output voltage.
16.If WE
is LOW when CE goes LOW, the outputs remain in the high impedance state.
17.HSB
must remain HIGH during read and write cycles.
Parameters
Cypress
Parameters
SRAM Read Cycle
t
ACE
[13]
t
RC
[14]
t
AA
t
DOE
[14]
t
OHA
[12, 15]
t
LZCE
[12, 15]
t
HZCE
[12, 15]
t
LZOE
[12, 15]
t
HZOE
[12]
t
PU
[12]
t
PD
t
DBE
[12]
t
LZBE
[12]
t
HZBE
SRAM Write Cycle
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
[12, 15,16]
t
HZWE
[12, 15]
t
LZWE
t
BW
20 ns 25 ns 45 ns
Alt
Parameters
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Description
Min Max Min Max Min Max
Chip Enable Access Time 20 25 45 ns Read Cycle Time 20 25 45 ns Address Access Time 20 25 45 ns Output Enable to Data Valid 10 12 2 0 ns Output Hold After Address Change 3 3 3 ns Chip Enable to Output Active 3 3 3 ns Chip Disable to Output Inactive 8 10 15 ns Output Enable to Output Active 0 0 0 ns Output Disable to Output Inactive 8 10 15 ns Chip Enable to Power Active 0 0 0 ns Chip Disable to Power Standby 20 25 45 ns
Unit
- Byte Enable to Data Valid 10 12 20 ns
- Byte Enable to Output Active 0 0 0 ns
- Byte Disable to Output Inactive 8 10 15 ns
t t t t t t t t t t
WC WP CW DW DH AW AS WR WZ OW
Write Cycle Time 20 25 45 ns Write Pulse Width 15 20 30 ns Chip Enable To End of Write 15 20 30 ns Data Setup to End of Write 8 10 15 ns Data Hold After End of Write 0 0 0 ns Address Setup to End of Write 15 20 30 ns Address Setup to Start of Write 0 0 0 ns Address Hold After End of Write 0 0 0 ns Write Enable to Output Disable 8 10 15 ns Output Active after End of Write 3 3 3 ns
- Byte Enable to End of Write 15 20 30 ns

Switching Waveforms

Document #: 001-49918 Rev. *A Page 10 of 23
Figure 6. SRAM Read Cycle #1: Address Controlled
[13, 14, 17]
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PRELIMINARY
CY14B104LA, CY14B104NA
CE
Note
18.CE
or WE must be >VIH during address transitions.
OE
BHE, BLE
Data Output
I
CC
Figure 7. SRAM Read Cycle #2: CE
t
LZCE
t
LZOE
t
LZBE
High Impedance
t
PU
Standby
and OE Controlled
[3, 13, 17]
Address ValidAddress
t
RC
t
ACE
t
AA
t
DOE
t
DBE
t
HZCE
t
t
HZBE
HZOE
Output Data Valid
t
PD
Active
CE
BHE, BLE
WE
Data Input
Data Output
Figure 8. SRAM Write Cycle #1: WE Controlled
t
WC
Address ValidAddress
t
SCE
t
BW
t
AW
t
PWE
t
SA
t
SD
Input Data Valid
t
Previous Data
t
HZWE
High Impedance
[3, 16, 17, 18]
t
HA
t
HD
LZWE
Document #: 001-49918 Rev. *A Page 11 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
Figure 9. SRAM Write Cycle #2: CE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input
Input Data Valid
High Impedance
Address ValidAddress
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
Controlled
[3, 16, 17, 18]
Figure 10. SRAM Write Cycle #3: BHE a nd BLE Controlled
Document #: 001-49918 Rev. *A Page 12 of 23
[3, 16, 17, 18]
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PRELIMINARY
CY14B104LA, CY14B104NA

AutoStore/Power Up RECALL

V
SWITCH
V
HDIS
V
VCCR ISE
t
STORE
t
STORE
t
HHHD
t
HHHD
t
DELAY
t
DELAY
t
LZHSB
t
LZHSB
t
HRECALL
t
HRECALL
HSB OUT
Autostore
POWER-
UP
RECALL
Read & Write
Inhibited
(
RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
Autostore
POWER-UP
RECALL
Read & Write
POWER
DOWN
Autostore
Note
20
Note
20
Note
23
Notes
19.t
HRECALL
starts from the time VCC rises above V
SWITCH.
20.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
21.On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
22.Read and write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
23.HSB pin is driven HIGH to VCC only by internal 100 kOhm resistor, HSB driver is disabled.
Parameters Description
[19]
t
HRECALL
t
STORE
t
DELAY
V
SWITCH
t
VCCRISE
[12]
V
HDIS
t
LZHSB
t
HHHD
Power Up RECALL Duration 20 20 20 ms
[20]
STORE Cycle Duration 8 8 8 ms
[21]
Time Allowed to Complete SRAM Cycle 20 25 25 ns Low Voltage Trigger Level 2.65 2.65 2.65 V VCC Rise Time 150 150 150 μs HSB Output Driver Disable Voltage 1.9 1.9 1.9 V HSB To Output Active Time 5 5 5 μs HSB High Active Time 500 500 500 ns
20 ns 25 ns 45 ns
Min Max Min Max Min Max
Unit

Switching Waveforms

Figure 11. AutoStore or Power Up RECALL
[22]
Document #: 001-49918 Rev. *A Page 13 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Software Controlled STORE/RECALL Cycle

W
5&
W
5&
W
6$
W
&:
W
&:
W
6$
W
+$
W
/=&(
W
+=&(
W
+$
W
+$
W
+$
W
'(/$<
W
6725(W5(&$//
W
+++'
W
/=+6%
+LJK,PSHGDQFH
$GGUHVV $GGUHVV$GGUHVV
&(
2(
+6%6725(RQO\
'4'$7$
5:,
W
5&
W
5&
W
6$
W
&:
W
&:
W
6$
W
+$
W
/=&(
W
+=&(
W
+$
W
+$
W
+$
W
'(/$<
$GGUHVV $GGUHVV$GGUHVV
&(
2(
'4'$7$
5:,
W
66
Notes
24.The software sequence is clocked with CE
controlled or OE controlled reads.
25.The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE
must be HIGH during all six consecutive cycles.
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
Parameters Description
t
RC
t
SA
t
CW
t
HA
t
RECALL
STORE/RECALL Initiation Cycle Time 20 25 45 ns Address Setup Time 0 0 0 ns Clock Pulse Width 152030 ns Address Hold Time 0 0 0 ns RECALL Duration 200 200 200 μs
20 ns 25 ns 45 ns
Min Max Min Max Min Max
[24, 25]
Unit

Switching Waveforms

Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
[25]
Figure 13. AutoStore Enable/Disable Cycle
Document #: 001-49918 Rev. *A Page 14 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Hardware STORE Cycle

t
PHSB
t
PHSB
t
DELAY
t
DHSB
t
DELAY
t
STORE
t
HHHD
t
LZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to V
CC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low.
HSB driver is disabled
t
DHSB
100kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
t
SS
t
SS
CE
Address
V
CC
t
SA
t
CW
Soft Sequence
Command
t
CW
Notes
26.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to eff ectively register command.
27.Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Parameters Description
t
DHSB
t
PHSB
t
SS
[26, 27]
HSB To Output Active Time when write latch not set 20 25 25 ns Hardware STORE Pulse Width 15 15 15 ns Soft Sequence Processing Time 100 100 100 μs
20 ns 25 ns 45 ns
Min Max Min Max Min Max
Unit

Switching Waveforms

Figure 14. Hardware STORE Cycle
[20]
Figure 15. Soft Sequence Processing
[26, 27]
Document #: 001-49918 Rev. *A Page 15 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Truth Table For SRAM Operations

HSB should remain HIGH for SRAM Operations.

For x8 Configuration

CE WE OE Inputs/Outputs
H X X High Z Deselect/Power down Standby
L H L Data Out (DQ
–DQ7); Read Active
0
L H H High Z Output Disabled Active L L X Data in (DQ
–DQ7); Write Active
0
For x16 Configuration
CE WE OE BHE
[3]
H X X X X High-Z Deselect/Power down Standby L X X H H High-Z Output Disabled Active L H L L L Data Out (DQ LHLHLData Out (DQ
L H L L H Data Out (DQ
L H H L L High-Z Output Disabled Active L H H H L High-Z Output Disabled Active L H H L H High-Z Output Disabled Active L L X L L Data In (DQ L L X H L Data In (DQ
L L X L H Data In (DQ
BLE
[3]
Inputs/Outputs
DQ
–DQ
8
DQ
–DQ7 in High-Z
0
–DQ
DQ
8
DQ
–DQ7 in High-Z
0
[2]
[2]
–DQ15) Read Active
0
–DQ7);
0
in High-Z
15
–DQ15);
8
–DQ15) Write Active
0
–DQ7);
0
in High-Z
15
–DQ15);
8
Read Active
Read Active
Write Active
Write Active
Mode Power
Mode Power
Document #: 001-49918 Rev. *A Page 16 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Ordering Information

Speed
(ns)
20 CY14B104LA-ZS20XCT 51 -85087 44-pin TSOP II Commercial
CY14B104LA-ZS20XC 51-85087 44-pin TSOP II CY14B104LA-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104LA-ZS20XI 51-85087 44-pin TSOP II CY14B104LA-BA20XCT 51-85128 48-ball FBGA Commercial CY14B104LA-BA20XC 51-85128 48-ball FBGA CY14B104LA-BA20XIT 51-85128 48-ball FBGA Industrial CY14B104LA-BA20XI 51-85128 48-ball FBGA CY14B104NA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104NA-ZS20XC 51-85087 44-pin TSOP II CY14B104NA-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104NA-ZS20XI 51-85087 44-pin TSOP II CY14B104NA-BA20XCT 51-85128 48-ball FBGA Commercial CY14B104NA-BA20XC 51-85128 48-ball FBGA CY14B104NA-BA20XIT 51-85128 48-ball FBGA Industrial CY14B104NA-BA20XI 51-85128 48-ball FBGA CY14B104NA-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14B104NA-ZSP20XC 51-85160 54-pin TSOP II CY14B104NA-ZSP20XIT 51-85160 54-pin TSOP II Industrial CY14B104NA-ZSP20XI 51-85160 54-pin TSOP II
25 CY14B104LA-ZS25XCT 51 -85087 44-pin TSOP II Commercial
CY14B104LA-ZS25XC 51-85087 44-pin TSOP II CY14B104LA-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14B104LA-ZS25XI 51-85087 44-pin TSOP II CY14B104LA-BA25XCT 51-85128 48-ball FBGA Commercial CY14B104LA-BA25XC 51-85128 48-ball FBGA CY14B104LA-BA25XIT 51-85128 48-ball FBGA Industrial CY14B104LA-BA25XI 51-85128 48-ball FBGA CY14B104NA-ZS25XCT 51-85087 44-pin TSOP II Commercial CY14B104NA-ZS25XC 51-85087 44-pin TSOP II CY14B104NA-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14B104NA-ZS25XI 51-85087 44-pin TSOP II CY14B104NA-BA25XCT 51-85128 48-ball FBGA Commercial CY14B104NA-BA25XC 51-85128 48-ball FBGA CY14B104NA-BA25XIT 51-85128 48-ball FBGA Industrial CY14B104NA-BA25XI 51-85128 48-ball FBGA CY14B104NA-BA25I 51-85128 48-ball FBGA CY14B104NA-ZSP25XCT 51-85160 54-pin TSOP II Commercial CY14B104NA-ZSP25XC 51-85160 54-pin TSOP II CY14B104NA-ZSP25XIT 51-85160 54-pin TSOP II Industrial CY14B104NA-ZSP25XI 51-85160 54-pin TSOP II
Ordering Code
Package Diagram
Package Type
Operating
Range
Document #: 001-49918 Rev. *A Page 17 of 23
[+] Feedback
PRELIMINARY
CY14B104LA, CY14B104NA
Ordering Information
Speed
(ns)
45 CY14B104LA-ZS45XCT 51 -85087 44-pin TSOP II Commercial
CY14B104LA-ZS45XC 51-85087 44-pin TSOP II CY14B104LA-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104LA-ZS45XI 51-85087 44-pin TSOP II CY14B104LA-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104LA-BA45XC 51-85128 48-ball FBGA CY14B104LA-BA45XIT 51-85128 48-ball FBGA Industrial CY14B104LA-BA45XI 51-85128 48-ball FBGA CY14B104NA-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104NA-ZS45XC 51-85087 44-pin TSOP II CY14B104NA-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104NA-ZS45XI 51-85087 44-pin TSOP II CY14B104NA-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104NA-BA45XC 51-85128 48-ball FBGA CY14B104NA-BA45XIT 51-85128 48-ball FBGA Industrial CY14B104NA-BA45XI 51-85128 48-ball FBGA CY14B104NA-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14B104NA-ZSP45XC 51-85160 54-pin TSOP II CY14B104NA-ZSP45XIT 51-85160 54-pin TSOP II Industrial CY14B104NA-ZSP45XI 51-85160 54-pin TSOP II
The above table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code
(continued)
Package Diagram
Package Type
Operating
Range
Document #: 001-49918 Rev. *A Page 18 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Part Numbering Nomenclature

Option: T - Tape & Reel Blank - Std.
Speed:
20 - 20 ns
25 - 25 ns
Data Bus:
L - x8
N - x16
Density: 104 - 4 Mb
Voltage: B - 3.0V
Cypress
CY 14 B 104 L A -ZS P 20 X C T
NVSRAM
14 - Auto Store + Software Store + Hardware Store
Temperature: C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Package: BA - 48 FBGA
ZS - TSOP II
45 - 45 ns
X - Pb-Free Blank -
SnPb
P - 54 Pin Blank - 44 Pin/48 Ball
Die Revision: Blank - No Rev
A - 1
st
Rev
Document #: 001-49918 Rev. *A Page 19 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Package Diagrams

MAX MIN.
DIMENSION IN MM (INCH)
11.938 (0.470)
PLANE
SEATING
PIN 1 I.D.
44
1
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
EJECTOR PIN
R
G
OKE
A
X
S
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
BASE PLANE
0.10 (.004)
22
23
TOP VIEW BOTTOM VIEW
51-85087-*A
Figure 16. 44-Pin TSOP II (51-85087)
Document #: 001-49918 Rev. *A Page 20 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
Package Diagrams
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
10.00±0.10
A
10.00±0.10
6.00±0.10
B
1.875
2.625
0.36
51-85128-*D
(continued)
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
Document #: 001-49918 Rev. *A Page 21 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA
Package Diagrams
51-85160-**
(continued)
Figure 18. 54-Pin TSOP II (51-85160)
Document #: 001-49918 Rev. *A Page 22 of 23
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PRELIMINARY
CY14B104LA, CY14B104NA

Document History Page

Document Title: CY14B104LA/CY14B104NA 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-49918
Rev. ECN No. Orig. of Change
Submission
Date
Description of Change
** 2606696 GVCH/PYRS 11/13/08 New Data Sheet
*A 2672700 GVCH/PYRS 03/12/09 Added best practices
Added CY14B104NA-BA25I part number Added footnote12 for HZ/LZ parameters

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© Cypress Semiconductor Corporation, 2008- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be us ed for medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express wr i tte n ag reement with Cypress. Furthermore, Cypress does not auth or iz e its products for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-49918 Rev. *A Revised March 11, 2009 Page 23 of 23
AutoStore and Quantum T rap are r egistered trad emarks of Cypr ess Semicondu ctors. All oth er product s and comp any nam es mentioned in this document are the trademarks of their respective holders.
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