CY14B104L, CY14B104N
4 Mbit (512K x 8/256K x 16) nvSRAM
Features
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Logic Block Diagram
[1, 2, 3]
Notes
1. Address A
0
- A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ
0
- DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE
and BLE are applicable for x16 configuration only.
Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times
■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16
(CY14B104N)
■ Hands off Automatic STORE on power down with only a small
Capacitor
■ STORE to QuantumTrap
software, device pin, or AutoStore
■ RECALL to SRAM initiated by software or power up
■ Infinite Read, Write, and Recall Cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20% to –10% operation
■ Commercial and Industrial Temperatures
■ 48-ball FBGA and 44/54-pin TSOP II packages
■ Pb-free and RoHS compliance
®
nonvolatile elements initiated by
®
on power down
The Cypress CY14B104L/CY14B104N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 512K bytes of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-07102 Rev. *L Revised December 19, 2008
[+] Feedback
CY14B104L, CY14B104N
Pinouts
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
A
17
A
2
A
1
NC
V
CC
DQ
4
NC
DQ
5
DQ
6
NC
DQ
7
NC
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
A
18
NC
DQ
1
48-FBGA
(not to scale)
Top View
(x8)
[4]
[5]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
BHE
NC
A
17
A
2
A
1
BLE
V
CC
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
NC
DQ
11
48-FBGA
(not to scale)
Top View
(x16)
[4]
[5]
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
6. HSB
pin is not available in 44-TSOP II (x16) package.
NC
A
8
NC
NC
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
A
18
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A
10
NC
WE
DQ
7
HSB
NC
V
SS
V
CC
V
CAP
NC
(x8)
[4]
[5]
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
WE
DQ
7
A
0
V
SS
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
(x16)
44-TSOP II
(x16)
44-TSOP II
(x8)
[6]
Figure 1. Pin Diagram - 48 FBGA
Figure 2. Pin Diagram - 44 Pin TSOP II
Document #: 001-07102 Rev. *L Page 2 of 25
[+] Feedback
CY14B104L, CY14B104N
Pinouts (continued)
A
17
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
DQ
3
DQ
2
DQ
1
DQ
0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(
not to scale)
OE
CE
V
CC
NC
V
SS
NC
A
9
NC
NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
(x16)
[4]
[5]
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
Pin Definitions
Pin Name IO Type Description
A0 – A
18
A0 – A
17
DQ
– DQ7Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
0
DQ
– DQ
0
15
WE
CE
OE
BHE
BLE
V
SS
V
CC
[6]
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Document #: 001-07102 Rev. *L Page 3 of 25
Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
operation.
Bidirectional Data IO Lines for x16 Configuratio n. Used as input or output lines depending on
operation.
Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific
address location.
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground Gr ound for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
will be driven HIGH for short time with standard output high current.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
HIGH.
[+] Feedback
CY14B104L, CY14B104N
Device Operation
0.1uF
Vcc
10kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
The CY14B104L/CY14B104N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104L/CY14B104N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the “Truth Table For SRAM Operations” on
page 15 for a complete description of read and write modes.
SRAM Read
The CY14B104L/CY14B104N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
data output repeatedly responds to address changes within the
ACE
tAA access time without the need for transitions on any control
input pins. This remains valid until another address chan ge or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0-18
or at t
or A
DOE
determines which of the 524,288
0-17
, whichever is later (read cycle 2). The
AA
Figure 4 shows the proper connecti on of the storage capacitor
(V
) for automatic store operation. Refer to DC Electrical
CAP
Characteristics on page 7 for the size of V
the V
up should be placed on WE
This pull up is only effective if the WE
pin is driven to V
CAP
by a regulator on the chip. A pull
CC
to hold it inactive during power up.
signal is tri-state during
. The voltage on
CAP
power up. Many MPU’s will tri-state their controls on power up.
This should be verified when using the pull up. When the
nvSRAM comes out of power-on-recall, the MPU must be active
or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB
signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE
or WE goes HIGH at
the end of the cycle. The data on the common IO pins DQ
are written into the memory if the data is valid tSD before the end
of a WE
write. The Byte Enable inputs (BHE
controlled write or before the end of an CE controlled
, BLE) determine which bytes
are written, in the case of 16bit words. It is recommended that
OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common IO lines. If OE
circuitry turns off the output buffers t
is left LOW, internal
after WE goes LOW.
HZWE
AutoStore Operation
The CY14B104L/CY14B104N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB;
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104L/CY14B104N.
During a normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below V
automatically disconnects the V
operation is initiated with power provided by the V
Software Store activated by an address
pin. This stored
CAP
CAP
, the part
pin from VCC. A STORE
SWITCH
CAP
capacitor.
0–15
CC
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB
and acknowledge the STORE operations. Use the HSB
request a hardware STORE cycle. When the HSB
LOW, the CY14B104L/CY14B104N conditionally initiates a
STORE operation after t
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
When HSB
is driven LOW by any means, SRAM read and write
operations that are in progress are given time to complete before
the STORE operation is initiated. After HSB
CY14B104L/CY14B104N continues SRAM operations for
t
.
DELAY
During any STORE operation, regardless of how it is initiated,
the CY14B104L/CY14B104N continues to drive the HSB
to
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14B104L/CY14B104N remains disabled until the HSB
returns HIGH. Leave the HSB
. An actual STORE cycle only
DELAY
goes LOW, the
unconnected if it is not used.
[6]
pin to control
pin to
pin is driven
pin
pin
Document #: 001-07102 Rev. *L Page 4 of 25
[+] Feedback
CY14B104L, CY14B104N
Hardware RECALL (Power Up)
Notes
7. While there are 19 address lines on the CY14B104L (18 address lines on the CY14B104N), only the 13 address lines (A
14
- A2) are used to control software modes.
The rest of the address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
9. IO state depends on the state of OE
, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
During power up or after any low power condition
(V
CC<VSWITCH
again exceeds the sense voltage of V
V
CC
cycle is automatically initiated and takes t
During this time, HSB
), an internal RECALL request is latched. When
, a RECALL
SWITCH
is driven LOW by the HSB driver.
HRECALL
to complete.
Software ST OR E
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B104L/CY14B104N
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed .
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence. Further, no read or write
operations must be done after the sixth address read for a
duration of soft-sequence processing time (tSS). If these conditions are not met, the sequence is aborted and no STORE or
RECALL takes place.
To initiate the software STORE cycle, the following addresses
and read sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
controlled reads. After the sixth address in the sequence
or OE
is entered, the STORE cycle commences and the chip is
disabled. HSB
will be driven LOW. It is important to use read
cycles and not write cycles in the sequence, although it is not
necessary that OE be LOW for a valid sequence. After the
t
cycle time is fulfilled, the SRAM is activated again for the
STORE
read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
controlled read operations must be
cycle time, the SRAM is again
RECALL
Table 1. Mode Selection
CE WE OE, BHE, BLE
[3]
A15 - A
[7]
0
Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Document #: 001-07102 Rev. *L Page 5 of 25
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[8, 9]
[+] Feedback
CY14B104L, CY14B104N
Table 1. Mode Selection (continued)
CE WE OE, BHE, BLE
[3]
L H L 0x4E38
L H L 0x4E38
L H L 0x4E38
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
0
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
[7]
AutoStore Enable
Nonvolatile Store
Mode IO Power
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active I
Output High Z
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
A15 - A
Recall
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state thr ough subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14B104L/CY14B104N protects data from corruption
during low voltage conditions by inhibiting all externa lly initiated
STORE and write operations. The low voltage condition is
detected when V
is in a write mode (both CE
CC
< V
. If the CY14B104L/CY14B104N
SWITCH
and WE are LOW) at power up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after t
inadvertent writes during power up or brown out conditions.
(HSB to output active). This protects against
LZHSB
Noise Considerations
Refer to CY application note AN1064.
Active
Active
[8, 9]
CC2
[8, 9]
[8, 9]
Document #: 001-07102 Rev. *L Page 6 of 25
[+] Feedback
CY14B104L, CY14B104N
Maximum Ratings
Notes
10.Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V
CC
= 3V. Not 100% tested.
11.The HSB
pin has I
OUT
= -2 μA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested .
12.V
CAP
(Storage capacitor) nominal va lue is 68 μF.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Maximum Accumulated Storage Time
At 150°C Ambient Temperature ........................ 1000h
At 85°C Ambient Temperature...................... 20 Years
Ambient Temperature with
Power Applied ............................................–55°C to +150°C
Supply Voltage on V
Voltage Applied to Outputs
in High-Z State.......................................–0. 5V to V
Input Voltage..........................................–0.5V to V
Relative to GND..........–0.5V to 4.1V
CC
CC
CC
+ 0.5V
+ 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential..................–2.0V to V
CC
+ 2.0V
Package Power Dissipation
Capability (T
= 25°C) ...................................................1.0W
A
Surface Mount Pb Soldering
Temperature (3 Seconds)..........................................+260°C
DC Output Current (1 output at a time, 1s duration).... 15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial –40°C to +85°C 2.7V to 3.6V
CC
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter Description Test Conditions Min Max Unit
I
CC1
I
CC2
I
CC3
I
CC4
I
SB
[10]
Average VCC Current tRC = 20 ns
t
= 25 ns
RC
= 45 ns
t
RC
Values obtained without output loads (I
Average VCC Current
during STORE
Average VCC Current at
t
= 200 ns, 3V, 25°C
RC
typical
Average V
during AutoStore Cycle
CAP
Current
All Inputs Don’t Care, VCC = Max
Average current for duration t
All inputs cycling at CMOS levels.
Values obtained without output loads (I
All Inputs Don’t Care, VCC = Max
Average current for duration t
VCC Standby Current CE > (VCC – 0.2V). All others V
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
I
I
V
V
V
V
V
IX
OZ
[11]
IH
IL
OH
OL
CAP
Input Leakage Current
(except HSB
)
Input Leakage Current
(for HSB
)
Off-State Output
Leakage Current
Input HIGH Voltage 2.0 V
Input LOW Voltage VSS – 0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I
[12]
Storage Capacitor Betwe en V
V
CC
V
CC
VCC = Max, VSS < V
or WE < V
OUT
OUT
Commercial 65
65
50
= 0 mA)
OUT
Industrial 70
70
52
10 mA
STORE
35 mA
= 0 mA).
OUT
5mA
STORE
= Max, VSS < V
= Max, VSS < V
IL
< 0.2V or > (VCC – 0.2V). Standby
IN
< V
IN
CC
< V
IN
CC
< VCC, CE or OE > V
OUT
or BHE/BLE > V
IH
–1 +1 μA
–100 +1 μA
–1 +1 μA
IH
5mA
+
CC
0.5
= –2 mA 2.4 V
= 4 mA 0.4 V
pin and VSS, 5V Rated 61 180 μF
CAP
mA
mA
mA
mA
mA
mA
V
Document #: 001-07102 Rev. *L Page 7 of 25
[+] Feedback
CY14B104L, CY14B104N
Data Retention and Endurance
3.0V
OUTPUT
5 pF
R1
R2
789Ω
3.0V
OUTPUT
30 pF
R1
R2
789Ω
for tri-state specs
577Ω
577Ω
Note
13.These parameters are guaranteed but not tested.
Parameter Description Min Unit
DATA
NV
C
R
Data Retention 20 Years
Nonvolatile STORE Operations 200 K
Capacitance
In the following table, the capacitance parameters are listed.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF
[13]
V
= 0 to 3.0V
CC
7pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
Figure 5. AC Test Loads
[13]
28.82 31.11 30.73 °C/W
7.84 5.56 6.08 °C/W
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <
Input and Output Timing Reference Levels.................... 1.5V
Document #: 001-07102 Rev. *L Page 8 of 25
3 ns
[+] Feedback
CY14B104L, CY14B104N
AC Switching Characteristics
$GGUHVV
'DWD2XWSXW
$GGUHVV9DOLG
3UHYLRXV'DWD9DOLG
2XWSXW'DWD9DOLG
W
5&
W
$$
W
2+$
Notes
14.WE
must be HIGH during SRAM read cycles.
15.Device is continuously selected with CE
, OE and BHE / BLE LOW.
16.Measured ±200 mV from steady state output voltage.
17.If WE
is LOW when CE goes LOW, the outputs remain in the high impedance state.
18.HSB
must remain HIGH during READ and WRITE cycles.
Parameters
Cypress
Parameters
SRAM Read Cycle
t
ACE
[14]
t
RC
[15]
t
AA
t
DOE
[15]
t
OHA
[16]
t
LZCE
[16]
t
HZCE
[16]
t
LZOE
[16]
t
HZOE
[13]
t
PU
[13]
t
PD
t
DBE
t
LZBE
t
HZBE
SRAM Write Cycle
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
[16,17]
t
HZWE
[16]
t
LZWE
t
BW
Alt
Parameters
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 20 25 45 ns
Read Cycle Time 20 25 45 ns
Address Access Time 20 25 45 ns
Output Enable to Data Valid 10 12 20 ns
Output Hold After Address Change 3 3 3 ns
Chip Enable to Output Active 3 3 3 ns
Chip Disable to Output Inactive 8 10 15 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 8 10 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 20 25 45 ns
- Byte Enable to Data Valid 10 12 20 ns
- Byte Enable to Output Active 0 0 0 ns
- Byte Disable to Output Inactive 8 10 15 ns
t
t
t
t
t
t
t
t
t
t
WC
WP
CW
DW
DH
AW
AS
WR
WZ
OW
Write Cycle Time 20 25 45 ns
Write Pulse Width 15 20 30 ns
Chip Enable To End of Write 15 20 30 ns
Data Setup to End of Write 8 10 15 ns
Data Hold After End of Write 0 0 0 ns
Address Setup to End of Write 15 20 30 ns
Address Setup to Start of Write 0 0 0 ns
Address Hold After End of Write 0 0 0 ns
Write Enable to Output Disable 8 10 15 ns
Output Active after End of Write 3 3 3 ns
- Byte Enable to End of Write 15 20 30 ns
Description
20 ns 25 ns 45 ns
Min Max Min Max Min Max
Unit
Switching Waveforms
Document #: 001-07102 Rev. *L Page 9 of 25
Figure 6. SRAM Read Cycle #1: Address Controlled
[14, 15, 18]
[+] Feedback
CY14B104L, CY14B104N
Figure 7. SRAM Read Cycle #2: CE
$GGUHVV9DOLG$GGUHVV
'DWD2XWSXW
2XWSXW'DWD9DOLG
6WDQGE\
$FWLYH
+LJK,PSHGDQFH
&(
2(
%+(%/(
,
&&
W
+=&(
W
5&
W
$&(
W
$$
W
/=&(
W
'2(
W
/=2(
W
'%(
W
/=%(
W
38
W
3'
W
+=%(
W
+=2(
'DWD2XWSXW
'DWD,QSXW
,QSXW'DWD9DOLG
+LJK,PSHGDQFH
$GGUHVV9DOLG$GGUHVV
3UHYLRXV'DWD
W
:&
W
6&(
W
+$
W
%:
W
$:
W
3:(
W
6$
W
6'
W
+'
W
+=:(
W
/=:(
:(
%+(%/(
&(
Notes
19.CE
or WE must be >VIH during address transitions.
and OE Controlled
[3, 14, 18]
Document #: 001-07102 Rev. *L Page 10 of 25
Figure 8. SRAM Write Cycle #1: WE Controlled
[3, 17, 18, 19]
[+] Feedback
CY14B104L, CY14B104N
Figure 9. SRAM Write Cycle #2: CE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
'DWD2XWSXW
'DWD,QSXW
,QSXW'DWD9DOLG
+LJK,PSHGDQFH
$GGUHVV9DOLG$GGUHVV
W
:&
W
6'
W
+'
%+(%/(
:(
&(
W
6&(
W
6$
W
%:
W
+$
W
$:
W
3:(
Controlled
[3, 17, 18, 19]
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled
Document #: 001-07102 Rev. *L Page 11 of 25
[3, 17, 18, 19]
[+] Feedback
CY14B104L, CY14B104N
AutoStore/Power Up RECALL
W
6725(
9
&&
9
6:,7&+
W
9&&5,6(
W
6725(
$XWR6WRUH
32:(583
5(&$//
W
+5(&$//
W
+5(&$//
5HDG:ULWH
,QKLELWHG
32:(583
5(&$//
5HDG:ULWH
%52:1287
$XWR6WRUH
32:(583
5(&$//
5HDG:ULWH
32:(5'2:1
$XWR6WRUH
1RWH
+6%
9
+',6
9
5(6(7
1RWH
W
'(/$<
W
'(/$<
W
/=+6%
W
/=+6%
287
W
385++
W
+++'
W
+++'
1RWH
Notes
20.t
HRECALL
starts from the time VCC rises above V
SWITCH.
21.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
22.On a Hardware STORE, Software STORE/RECALL, AutoStore Enable/Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
23.Read and Write cycles are ignored during STORE, RECALL, and while V
CC
is below V
SWITCH.
24.HSB pin is driven HIGH to VCC only by internal 100 kΩ resistor, HSB driver is disabled.
Parameters Description
[13]
[21]
[22]
[20]
Power Up RECALL Duration 20 ms
STORE Cycle Duration 8 ms
Time Allowed to Complete SRAM Cycle 1 70 μs
Low Voltage Trigger Level 2.65 V
VCC Rise Time 150 μs
HSB Output Driver Disable Voltage 1.9 V
HSB High Active Time 500 ns
HSB Hold Time after Power-Up Recall Start 70 μs
HSB To Output Active Time 5 μs
t
HRECALL
t
STORE
t
DELAY
V
SWITCH
t
VCCRISE
V
HDIS
t
HHHD
t
PURHH
t
LZHSB
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL
CY14B104L/CY14B104N
Min Max
[23]
Unit
Document #: 001-07102 Rev. *L Page 12 of 25
[+] Feedback
CY14B104L, CY14B104N
Software Controlled ST ORE/RECALL Cycle
W
5&
W
5&
W
6$
W
&:
W
&:
W
6$
W
+$
W
/=&(
W
+=&(
W
+$
W
+$
W
'(/$<
W
6725(W5(&$//
W
+++'
W
/=+6%
+LJK
,PSHGDQFH
$GGUHVV $GGUHVV$GGUHVV
&(
2(
+6%6725(RQO\
'4'$7$
5:,
W
66
W
+$
W
5&
W
5&
W
6$
W
&:
W
&:
W
6$
W
+$
W
/=&(
W
+=&(
W
+$
W
+$
W
+$
W
'(/$<
$GGUHVV $GGUHVV$GGUHVV
&(
2(
'4'$7$
5:,
W
66
Notes
25.The software sequence is clocked with CE
controlled or OE controlled reads.
26.The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE
must be HIGH during all six consecutive cycles. After the sixth addr ess read
cycle, no further read or write operation must be performed for tSS duration. If these conditions are not met, the software sequence is aborted.
In the following table, the software controlled STORE/RECALL cycle parameters are listed.
Parameters Description
t
RC
t
SA
t
CW
t
HA
t
RECALL
[27, 28]
t
SS
STORE/RECALL Initiation Cycle Time 20 25 45 ns
Address Setup Time 0 0 0 ns
Clock Pulse Width 15 20 30 ns
Address Hold Time 0 0 0 ns
RECALL Duration 200 200 200 μs
Soft Sequence Processing Time 100 100 100 μs
20 ns 25 ns 45 ns
Min Max Min Max Min Max
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
[25, 26]
Unit
[26]
Figure 13. Autostore Enable / Disable Cycle
Document #: 001-07102 Rev. *L Page 13 of 25
[+] Feedback
CY14B104L, CY14B104N
Hardware STORE Cycle
W
3+6%
W
3+6%
W
+/%/
W
6725(
W
+++'
W
/=+6%
:ULWHODWFKVHW
:ULWHODWFKQRWVHW
+6%,1
+6%287
'4'DWD2XW
+6%,1
W
'(/$<
W
+/%/
W
+++'
W
/=+6%
+6%287
'4'DWD2XW
W
'(/$<
$GGUHVV $GGUHVV $GGUHVV $GGUHVV
6RIW6HTXHQFH
&RPPDQG
W
66
W
66
&(
$GGUHVV
9
&&
W
6$
W
&:
6RIW6HTXHQFH
&RPPDQG
W
&:
Notes
27.This is the amount of time it takes to take action on a soft sequence command. V
CC
power must remain HIGH to effectively register command.
28.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Parameters Description
t
PHSB
t
HLBL
Hardware STORE Pulse Width 15 ns
Hardware STORE LOW to STORE Busy 500 ns
Switching Waveforms
Figure 14. Hardware STORE Cycle
[21]
CY14B104L/CY14B104N
Min Max
Unit
Figure 15. Soft Sequence Processing
[27, 28]
Document #: 001-07102 Rev. *L Page 14 of 25
[+] Feedback
CY14B104L, CY14B104N
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE WE OE Inputs/Outputs
H X X High Z Deselect/Power down Standby
L H L Data Out (DQ
–DQ7); Read Active
0
L H H High Z Output Disabled Active
L L X Data in (DQ
–DQ7); Write Active
0
For x16 Configuration
CE WE OE BHE BLE Inputs/Outputs
H X X X X High-Z Deselect/Power down Standby
L X X H H High-Z Output Disabled Active
L H L L L Data Out (DQ
LHLHLData Out (DQ
DQ
L H L L H Data Out (DQ
DQ
L H H L L High-Z Output Disabled Active
L H H H L High-Z Output Disabled Active
L H H L H High-Z Output Disabled Active
L L X L L Data In (DQ
L L X H L Data In (DQ
L L X L H Data In (DQ
DQ
DQ
[2]
–DQ15) Read Active
0
–DQ7);
–DQ
8
–DQ7 in High-Z
0
–DQ
8
–DQ7 in High-Z
0
0
in High-Z
15
–DQ15);
8
–DQ15) Write Active
0
–DQ7);
0
in High-Z
15
–DQ15);
8
[2]
Mode Power
Mode Power
Read Active
Read Active
Write Active
Write Active
Document #: 001-07102 Rev. *L Page 15 of 25
[+] Feedback
CY14B104L, CY14B104N
Ordering Information
Speed
(ns)
20 CY14B104L-ZS20XCT 51-85087 44-pin TSOP II Commercial
CY14B104L-ZS20XIT 51-85087 44-pin TSOP II Industrial
CY14B104L-ZS20XI 51-85087 44-pin TSOP II
CY14B104L-BA20XCT 51-85128 48-ball FBGA Commercial
CY14B104L-BA20XIT 51-85128 48-ball FBGA Industrial
CY14B104L-BA20XI 51-85128 48-ball FBGA
CY14B104L-ZSP20XCT 51-85160 54-pin TSOP II Commercial
CY14B104L-ZSP20XIT 51-85160 54-pin TSOP II Industrial
CY14B104L-ZSP20XI 51-85160 54-pin TSOP II
CY14B104N-ZS20XCT 51-85087 44-pin TSOP II Commercial
CY14B104N-ZS20XIT 51-85087 44-pin TSOP II Industrial
CY14B104N-ZS20XI 51-85087 44-pin TSOP II
CY14B104N-BA20XCT 51-85128 48-ball FBGA Commercial
CY14B104N-BA20XIT 51-85128 48-ball FBGA Industrial
CY14B104N-BA20XI 51-85128 48-ball FBGA
CY14B104N-ZSP20XCT 51-85160 54-pin TSOP II Commercial
CY14B104N-ZSP20XIT 51-85160 54-pin TSOP II Industrial
CY14B104N-ZSP20XI 51-85160 54-pin TSOP II
25 CY14B104L-ZS25XCT 51-85087 44-pin TSOP II Commercial
CY14B104L-ZS25XIT 51-85087 44-pin TSOP II Industrial
CY14B104L-ZS25XI 51-85087 44-p in TSOP II
CY14B104L-BA25XIT 51-85128 48-ball FBGA Industrial
CY14B104L-BA25XI 51-85128 48-ball FBGA
CY14B104N-BA25XCT 51-85128 48-ball FBGA Commercial
CY14B104L-ZSP25XCT 51-85160 54-pin TSOP II Commercial
CY14B104L-ZSP25XIT 51-85160 54-pin TSOP II Industrial
CY14B104L-ZSP25XI 51-85160 54-pin TSOP II
CY14B104N-ZS25XCT 51-85087 44-pin TSOP II Commercial
CY14B104N-ZS25XIT 51-85087 44-pin TSOP II Industrial
CY14B104N-ZS25XI 51-85087 44-pin TSOP II
CY14B104N-BA25XCT 51-85128 48-ball FBGA Commercial
CY14B104N-BA25XIT 51-85128 48-ball FBGA Industrial
CY14B104N-BA25XI 51-85128 48-ball FBGA
CY14B104N-ZSP25XCT 51-85160 54-pin TSOP II Commercial
CY14B104N-ZSP25XIT 51-85160 54-pin TSOP II Industrial
CY14B104N-ZSP25XI 51-85160 54-pin TSOP II
Ordering Code
Package
Diagram
Package Type
Operating
Range
Document #: 001-07102 Rev. *L Page 16 of 25
[+] Feedback
CY14B104L, CY14B104N
Ordering Information (continued)
Speed
(ns)
45 CY14B104L-ZS45XCT 51-85087 44-pin TSOP II Commercial
CY14B104L-ZS45XIT 51-85087 44-pin TSOP II Industrial
CY14B104L-ZS45XI 51-85087 44-p in TSOP II
CY14B104L-BA45XCT 51-85128 48-ball FBGA Commercial
CY14B104L-BA45XIT 51-85128 48-ball FBGA Industrial
CY14B104L-BA45XI 51-85128 48-ball FBGA
CY14B104L-ZSP45XCT 51-85160 54-pin TSOP II Commercial
CY14B104L-ZSP45XIT 51-85160 54-pin TSOP II Industrial
CY14B104L-ZSP45XI 51-85160 54-pin TSOP II
CY14B104N-ZS45XCT 51-85087 44-pin TSOP II Commercial
CY14B104N-ZS45XIT 51-85087 44-pin TSOP II Industrial
CY14B104N-ZS45XI 51-85087 44-pin TSOP II
CY14B104N-BA45XCT 51-85128 48-ball FBGA Commercial
CY14B104N-BA45XIT 51-85128 48-ball FBGA Industrial
CY14B104N-BA45XI 51-85128 48-ball FBGA
CY14B104N-ZSP45XCT 51-85160 54-pin TSOP II Commercial
CY14B104N-ZSP45XIT 51-85160 54-pin TSOP II Industrial
CY14B104N-ZSP45XI 51-85160 54-pin TSOP II
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availab ility of these parts.
Ordering Code
Package
Diagram
Package Type
Operating
Range
Document #: 001-07102 Rev. *L Page 17 of 25
[+] Feedback
CY14B104L, CY14B104N
Part Numbering Nomenclature
Option:
T - Tape & Reel
Blank - Std.
Speed:
20 - 20 ns
25 - 25 ns
Data Bus:
L - x8
N - x16
Density:
104 - 4 Mb
Voltage:
B - 3.0V
Cypress
CY 14 B 104 L - ZS P 20 X C T
NVSRAM
14 - Auto Store + Software Store + Hardware Store
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Package:
BA - 48 FBGA
ZS - TSOP II
P - 54 Pin
Blank - 44 Pin
45 - 45 ns
Document #: 001-07102 Rev. *L Page 18 of 25
[+] Feedback
CY14B104L, CY14B104N
Package Diagrams
MAX
MIN.
DIMENSION IN MM(INCH)
11.938 (0.470)
PLANE
SEATING
PIN 1 I.D.
44
1
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
EJECTOR PIN
R
G
OKE
A
X
S
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
BASE PLANE
0.10 (.004)
22
23
TOP VIEW BOTTOM VIEW
51-85087-*A
Figure 16. 44-Pin TSOP II (51-85087)
Document #: 001-07102 Rev. *L Page 19 of 25
[+] Feedback
CY14B104L, CY14B104N
Package Diagrams (continued)
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
10.00±0.10
A
10.00±0.10
6.00±0.10
B
1.875
2.625
0.36
51-85128-*D
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
Document #: 001-07102 Rev. *L Page 20 of 25
[+] Feedback
CY14B104L, CY14B104N
Package Diagrams (continued)
51-85160-**
Figure 18. 54-Pin TSOP II (51-85160)
Document #: 001-07102 Rev. *L Page 21 of 25
[+] Feedback
CY14B104L, CY14B104N
Document History Page
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-07102
Rev . ECN No.
Submission
Date
** 431039 See ECN TUP New Data Sheet
*A 489096 See ECN TUP Removed 48 SSOP Package
*B 499597 See ECN PCI Removed 35 ns speed bin
*C 517793 See ECN TUP Removed 55ns speed bin
*D 774001 See ECN UHA Changed the data sheet from Advance information to Preliminary
*E 914220 See ECN UHA Included all the information for 45 ns part in this data sheet
Orig. of
Change
Description of Change
Added 48 FBGA and 54 TSOPII Packages
Updated Part Numbering Nomenclature and Ordering Information
Added Soft Sequence Processing Time Waveform
Added 55 ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical I
Changed STORE cycles from 500K to 200K cycles
at 200-ns cycle time to 8 mA
CC
Shaded Commercial grade in operating range table
Modified Icc/Is specs
48 FBGA package nomenclature changed from BW to BV
Modified part nomenclature table. Changes reflected in ordering information
table
Changed pinout for 44TSOPII and 54TSOPII packages
Changed I
Changed I
Changed V
Changed V
Changed t
Changed t
Changed t
Changed t
Changed t
Removed t
Added Timing Parameters for BHE and BLE - t
Removed min specification for Vswitch
Changed t
Added t
Changed t
to 1mA
SB
to 3mA
CC4
min to 35μF
CAP
max to Vcc + 0.5V
IH
to 15ms
STORE
to 10ns
PWE
to 15ns
SCE
to 5ns
SD
to 10ns
AW
HLBL
to 1ns
GLAX
max of 70us
DELAY
specification from 70us min to 70us max
SS
DBE
, t
LZBE
, t
HZBE
48 FBGA package code changed from BV to BA
Removed 48 FBGA package in X8 configuration in ordering information.
Changed t
Changed t
Changed t
Changed t
Changed the value of I
Changed the value of t
Changed A
to 10ns in 15ns part
DBE
in 15ns part to 7ns and in 25ns part to10ns
HZBE
in 15ns part to 15ns and in 25ns part to 20ns
BW
to t
GLAX
and A19 Pins in FBGA Pin Configuration to NC
18
GHAX
to 25mA
CC3
in 15ns part to15ns
AW
, t
BW
Document #: 001-07102 Rev. *L Page 22 of 25
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CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-07102
Rev . ECN No.
Submission
Date
Orig. of
Change
Description of Change
*F 1889928 See ECN vsutmp8/AE-SAAdded Footnotes 1, 2 and 3.
Updated logic block diagram
Added 48-FBGA (X8) Pin Diagram
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8).
Updated pin definitions table.
Corrected typo in V
Changed the value of I
Changed I
Rearranging of Footnotes.
value from 1mA to 2mA
SB
min spec
IL
from 25mA to 13mA
CC3
Updated ordering information table
*G 2267286 See ECN GVCH/PYRS Added BHE
and BLE Information in Pin Definitions Table
Updated Figure 4 (Autostore mode)
Updated footnote 6
Changed I
Changed I
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max
& I
CC2
CC3
from 3 mA to 6 mA
CC4
from 13 mA to 15 mA
value
Changed I
Added input leakage current (I
Corrected typo in t
Corrected typo in t
Corrected typo in t
Changed t
Added footnotes 9 and 25; Reframed footnote 14 and 21
from 2 mA to 3 mA
SB
value from 22 ns to 20 ns for 45 ns part
DBE
value from 22 ns to 15 ns for 45 ns part
HZBE
value from 15 ns to 10ns for 15 ns part
AW
from 100 to 200 us
RECALL
) for HSB in DC Electrical Characteristics table
IX
Added footnote 14 to figure 7 (SRAM WRITE Cycle #1)
*H 2483627 See ECN GVCH/PYRS Removed 8 mA typical I
Referenced footnote 8 to I
Changed I
Changed Vcap minimum value from 54 uF to 61 uF
Changed t
Figure 11:Changed tSA to t
from 15 mA to 35 mA
CC3
to t
AVAV
RC
at 200 ns cycle time in Feature section
CC
in DC Characteristics table
CC3
and t
AS
SCE to tCW
*I 2519319 06/20/08 GVCH/PYRS Added 20 ns access speed in “Features”
Added I
Grade
for tRC=20 ns for both industrial and Commercial temperature
CC1
updated Thermal resistance table values for 48-FBGA, 44-TSOP II and
54-TSOP II Packages
Added AC Switching Characteristics specs for 20 ns access speed
Added software controlled STORE/RECALL cycle specs for 20 ns access
speed
Updated ordering information and part numbering nomenclature
Document #: 001-07102 Rev. *L Page 23 of 25
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CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-07102
Rev . ECN No.
Submission
Date
Orig. of
Change
Description of Change
*J 2600941 11/04/08 GVCH/PYRS Removed 15 ns access speed
Updated Logic block diagram
Updated footnote 1
Added footnote 2 and 5
Pin definition: Updated WE
, HSB and NC pin description
Page 4:Updated SRAM READ, SRAM WRITE, Autostore operation description
Page 4:Updated Hardware store operation and Hardware RECALL (Power-up)
description
Footnote 1 referenced for Mode selection Table
Page 6:updated Data protection description
Maximum Ratings: Added Max. Accumulated storage time
Changed I
Changed I
Changed I
Updated I
Changed V
Updated footnote 10 and 11
from 6mA to 10mA
CC2
from 6mA to 5mA
CC4
from 3mA to 5mA
SB
CC1, ICC3 , ISB
max value from 82uf to 180uF
CAP
and I
OZ
Added footnote 12
Added Data retention and Endurance Table
Updated Input Rise and Fall time in AC test Conditions
Referenced footnote 15 to t
Updated All switching waveforms
OHA
Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled)
Changed t
Changed t
Added V
Updated footnote 21
DELAY
STORE
HDIS
to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
from 15ms to 8ms
, t
and t
HHHD
LZHSB
Added footnote 24
Software controlled STORE/RECALL cycle table: Changed t
Changed t
Added t
Changed t
DHSB
Updated tSS from 70us to 100us
to t
GHAX
parameter
to t
HLHX
HA
PHSB
Added Truth table for SRAM operations
Updated ordering information and part numbering nomenclature
*K 2612931 11/26/08 AESA Removed Preliminary form header.
*L 2625431 12/19/08 GVCH/DSG Changed t
Page 4: Removed the text relating to write requested after HSB
to 1us (min) and 70us (max) for all three access time
DELAY
inhibited.
Page 5: modified software store description to indicate no further read/writes
permitted for t
Added parameter t
Updated Figures 11, 12 and 13.
Added t
Removed t
HLBL
Updated Figure 14;Hardware store cycle
duration after sixth read cycle.
SS
PURHH to
AutoStore power-Up recall table
parameter
parameter
DHSB
Changed Simtek trademarks to Cypress
Test conditions
parameter
parameters
to t
AS
SA
goes LOW are
Document #: 001-07102 Rev. *L Page 24 of 25
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CY14B104L, CY14B104N
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© Cypress Semiconductor Corporation, 2006- 2008. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used fo r
medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an exp re ss wr itten agreement with Cypress. Furthermore, Cypress doe s not author i ze its products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypres s
integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Code except as specifi ed above is prohib ited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does n ot
assume any liability arising out of the app licati on or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot auth orize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07102 Rev. *L Revised December 19, 2008 Page 25 of 25
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the tr adem arks of th eir res pect ive
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