Cypress CY14B104K, CY14B104M User Manual
PRELIMINARY
CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with
Real Time Clock
Features
STATIC RAM
ARRAY
2048 X 2048
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum
Trap
2048 X 2048
STORE
RECALL
V
CC
V
CA
P
HSB
A9A
10
A
11
A12A13A14A15A
16
SOFTWARE
DETECT
A14-A
2
OE
CE
WE
BHE
BLE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
RTC
MUX A18-A
0
X
1
X
2
INT
V
RTCbat
V
RTCcap
Logic Block Diagram
[1, 2, 3]
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap
software, device pin, or AutoStore
■ RECALL to SRAM initiated by software or power up
■ High reliability
■ Infinite Read, Write, and RECALL cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20%, –10% operation
■ Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
®
nonvolatile elements is initiated by
®
on power down
■ Watchdog timer
■ Clock alarm with programmable interrupts
■ Capacitor or battery backup for RTC
■ Commercial and industrial temperatures
■ 44 and 54-pin TSOP II package
■ Pb-free and RoHS compliance
Functional Description
The Cypress CY14B104K/CY14B104M combines a 4-Mbit
nonvolatile static RAM with a full featured Real Time Clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days or months alarms. There is also a programmable watchdog
timer for process control.
Notes
1. Address A
2. Data DQ
3. BHE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-07103 Rev. *K Revised January 29, 2009
- A18 for x8 configuration and Address A0 - A17 for x16 configuration.
0
- DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
0
and BLE are applicable for x16 configuration only.
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Pinouts
NC
A
8
X2
X1
V
SS
DQ
6
DQ5
DQ4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A
10
V
RTCbat
WE
DQ
7
HSB
INT
V
SS
V
CC
V
CAP
V
RTCcap
(x8)
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
DQ
3
DQ
2
DQ
1
DQ
0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(not to scale)
OE
CE
V
CC
INT
V
SS
NC
A
9
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
(x16)
V
RTCcap
V
RTCbat
X2
X1
[4]
[4]
[5]
[5]
A
17
A
18
A
16
A
17
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Table 1. Pin Definitions
Pin Name I/O Type Description
– A
A
0
18
– A
A
0
17
– DQ7Input/Output Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
DQ
0
DQ0 – DQ
15
NC No Connect No Connects. This pin is not connected to the die.
WE
CE
OE
BHE
BLE
X
1
X
2
V
RTCcap
V
RTCbat
Document #: 001-07103 Rev. *K Page 2 of 31
Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
Input Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Output Crystal Connection. Drives crystal on start up.
Input Crystal Connection. For 32.768 KHz crystal.
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if V
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if V
cycles. Deasserting OE
Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II
HIGH causes the I/O pins to tri-state.
RTCcap
RTCbat
is used.
is used.
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Table 1. Pin Definitions (continued)
0.1uF
Vcc
10kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
Pin Name I/O Type Description
INT
V
V
SS
CC
Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground Ground for the Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
HSB
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation
HSB
is driven HIGH for short time with standard output high current.
V
CAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
The CY14B104K/CY14B104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B104K/CY14B104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the “Truth Table For SRAM Operations” on
page 23 for a complete description of read and write modes.
SRAM Read
The CY14B104K/CY14B104M performs a read cycle whenever
and OE are LOW, and WE and HSB are HIGH. The address
CE
specified on pins A
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE
, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
data output repeatedly responds to address changes within the
ACE
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE
or OE is brought HIGH, or WE or HSB is brought LOW.
0-18
or at t
or A
DOE
determines which of the 524,288
0-17
, whichever is later (read cycle 2). The
AA
AutoStore Operation
The CY14B104K/CY14B104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device power
down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104K/CY14B104M.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below V
automatically disconnects the V
operation is initiated with power provided by the V
pin from VCC. A STORE
CAP
pin. This stored
CAP
SWITCH
capacitor.
CAP
Figure 2. AutoStore Mode
to
CC
, the part
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE
the end of the cycle. The data on the common I/O pins DO
are written into the memory if it is valid tSD before the end of a
WE
The Byte Enable inputs (BHE
written, in the case of 16-bit words. Keep OE
entire write cycle to avoid data bus contention on common I/O
lines. If OE
buffers t
Document #: 001-07103 Rev. *K Page 3 of 31
or WE goes HIGH at
controlled write or before the end of a CE controlled write.
, BLE) determine which bytes are
0-15
HIGH during the
is left LOW, internal circuitry turns off the output
HZWE
after WE goes LOW.
Figure 2 shows the proper connection of the storage capacitor
(V
) for automatic STORE operation. Refer to DC Electrical
CAP
Characteristics on page 14 for the size of the V
on the V
up should be placed on WE
This pull up is only effective if the WE
pin is driven to V
CAP
by a regulator on the chip. A pull
CC
to hold it inactive during power up.
signal is tri-state during
CAP
power up. Many MPUs tri-state their controls on power up. Verify
this when using the pull up. When the nvSRAM comes out of
. The voltage
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
power-on-recall, the MPU must be active or the WE
until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
held inactive
Hardware STORE (HSB) Operation
The CY14B104K/CY14B104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB
to request a Hardware STORE cycle. When the HSB
LOW, the CY14B104K/CY14B104M conditionally initiates a
STORE operation after t
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM read and write operations, that are in progress when HSB
is driven LOW by any means, are given time t
before the STORE operation is initiated. However, any SRAM
write cycles requested after HSB
returns HIGH. In case the write latch is not set, HSB is not
HSB
driven LOW by the CY14B104K/CY14B104M but any SRAM
read and write cycles are inhibited until HSB
MPU or external source.
During any STORE operation, regardless of how it is initiated,
the CY14B104KA/CY14B104MA continues to drive the HSB
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14B104K/CY14B104M remains disabled until the HSB
returns HIGH. Leave the HSB
. An actual STORE cycle begins
DELAY
goes LOW are inhibited until
is returned HIGH by
unconnected if it is not used.
DELAY
pin is used
pin is driven
to complete
pin
pin
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC<VSWITCH
again exceeds the V
V
CC
is automatically initiated and takes t
this time, the HSB
reads and writes to nvSRAM are inhibited.
), an internal RECALL request is latched. When
pin is driven LOW by the HSB driver and all
on powerup, a RECALL cycle
SWITCH
HRECALL
to complete. During
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE
reads. Both CE
executed. After the sixth address in the sequence is entered, the
STORE cycle starts and the chip is disabled. It is important to use
read cycles and not write cycles in the sequence. The SRAM is
activated again for read and write operations after the t
cycle time.
and OE must be toggled for the sequence to be
or OE controlled
STORE
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE
operations:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
cycle time, the SRAM is again
RECALL
or OE controlled read
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B104K/CY14B104M
Software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
OE
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Document #: 001-07103 Rev. *K Page 4 of 31
or
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Table 2. Mode Selection
Notes
6. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only the 13 address lines (A
14
- A2) are used to control software modes.
Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
CE WE OE, BHE, BLE
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
L H L 0x4E38
L H L 0x4E38
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
[6]
0
Mode I/O Power
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[7]
[3]
A15 - A
Disable
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[7]
Enable
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
CC2
[7]
STORE
[7]
Active
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
RECALL
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
Document #: 001-07103 Rev. *K Page 5 of 31
or OE
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Data Protection
The CY14B104K/CY14B104M protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when V
CY14B104K/CY14B104M is in a write mode (both CE
are LOW) at power up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after t
active). This protects against inadvertent writes during power up
or brown out conditions.
is less than V
CC
SWITCH
(HSB to output
LZHSB
. If the
and WE
Noise Considerations
Refer to CY application note AN1064.
Real Time Clock Operation
nvTIME Operation
The CY14B104K/CY14B104M offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
RTC registers use the last 16 address locations of the SRAM.
Internal double buffering of the clock and timer information
registers prevents accessing transitional internal clock data
during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
RTC functionality is described with respect to CY14B104K in the
following sections. The same description applies to
CY14B104M, except for the RTC register addresses. The RTC
register addresses for CY14B104K range from 0x7FFF0 to
0x7FFFF, while those for CY14B104M range from 0x3FFF0 to
0x3FFFF. Refer to Table 4 on page 10 and Tab l e 5 on page 11
for a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user must stop
internal updates to the CY14B104K time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x7FFF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while
the internal clock continues to run. After a ‘0’ is written to the read
bit (‘R’), all RTC registers are simultaneously updated within
20 ms
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers and must be in 24 hour BCD format. The time written is
referred to as the “Base Time”. This value is stored in nonvolatile
registers and used in the calculation of the current time.
Resetting the write bit to ‘0’ transfers the values of timekeeping
registers to the actual clock counters, after which the clock
resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note The values entered in the timekeeping, alarm, calibration,
and interrupt registers need a STORE operation to be saved in
nonvolatile memory. Therefore, while working in AutoStore
disabled mode, the user must perform a STORE operation after
writing into the RTC registers for the RTC to work correctly.
Backup Power
The RTC in the CY14B104K is intended for permanently
powered operation. The V
depending on whether a capacitor or battery is chosen for the
application. When the primary power, V
V
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B104K consumes a
maximum of 300 nanoamps at room temperature. User must
choose capacitor or battery values according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
Table 3. RTC Backup Time
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3V lithium is recommended and the CY14B104K
sources current only from the battery when the primary power is
removed. However the battery is not recharged at any time by
the CY14B104K. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
the device switches to the backup power supply.
SWITCH
Capacitor Value Backup Time
0.1F 72 hours
0.47F 14 days
1.0F 30 days
RTCcap
or V
pin is connected
RTCbat
, fails and drops below
CC
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls
the enable and disable of the oscillator. This bit is nonvolatile and
is shipped to customers in the “enabled” (set to 0) state. To
preserve the battery life when the system is in storage, OSCEN
Document #: 001-07103 Rev. *K Page 6 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, If the voltage on the backup supply
(V
the oscillator may fail.The CY14B104K has the ability to detect
oscillator failure when system power is restored. This is recorded
in the OSCF (Oscillator Failed bit) of the flags register at the
address 0x7FFF0. When the device is powered on (V
above V
If the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to “1”. The system must check
for this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see Setting the Clock on page 6), which is
the value last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit “W” (in the Flags register at
0x7FFF0) to a “1” to enable writes to the Flag register. Write a
“0” to the OSCF bit and then reset the write bit to “0” to disable
writes.
RTCcap
or V
SWITCH
) falls below their respective minimum level,
RTCbat
) the OSCEN bit is checked for “enabled” status.
CC
goes
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in market
typically have an error of +
CY14B104K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5
seconds to -5 seconds per month.
The
calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x7FFF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x7FFF0) must be set to ‘1’. This causes the INT pin to
20 ppm to +35 ppm. However,
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x7FFF0) to “1” to enable writes to the Flag register. Write a
value to CAL, and then reset the write bit to “0” to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x7FFF1-5) with the corresponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x7FFF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags
register clears the alarm flag bit (and all others). A hardware
interrupt pin may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register
- 0x7FFF0) to ‘1’ to enable writes to Alarm Registers. After writing
the alarm value, clear the ‘W’ bit back to “0” for the changes to
take effect.
Note CY14B104K requires the alarm match bit for seconds
(0x7FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag
and Interrupt.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x7FFF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDT flag never occur.
Document #: 001-07103 Rev. *K Page 7 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
New time out values are written by setting the watchdog write bit
1 Hz
Oscillator
Clock
Divider
Counter
Zero
Compare
WDF
WDS
Load
Register
WDW
D
Q
Q
Watchdog
Register
write to
Watchdog
Register
32 Hz
32,768 KHz
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 3. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the Watchdog Interrupt
Enable (WIE) bit in the Interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the Flags registers.
Figure 3. Watchdog Timer Block Diagram
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in Interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the Flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
Note CY14B104K generates valid interrupts only after the
Powerup Recall sequence is completed. All events on INT pin
must be ignored for t
HRECALL
duration after powerup.
Interrupt Register
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in Flags register.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF Flags register.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
.
Power Monitor
The CY14B104K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
V
access. The power monitor is based on an internal band gap
CC
reference circuit that compares the V
threshold.
As described in the section “AutoStore Operation” on page 3,
when V
STORE operation is initiated from SRAM to the nonvolatile
is reached as VCC decays from power loss, a data
SWITCH
elements, securing the last SRAM data state. Power is also
switched from V
operate the RTC oscillator.
to the backup supply (battery or capacitor) to
CC
When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not
available to the user. The clock continues to operate in the
background. The updated clock data is available to the user
t
HRECALL
“AutoStore/Power Up RECALL” on page 20)
Interrupts
The CY14B104K has Flags register, Interrupt register, and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
delay after VCC is restored to the device (see
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x7FFF6). In addition, each has an associated flag bit
in the Flags register (0x7FFF0) that the host processor uses to
Document #: 001-07103 Rev. *K Page 8 of 31
voltage to V
CC
SWITCH
to ‘0’, the power fail monitor only affects the PF flag in Flags
register.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when V
is active LOW and the drive mode is open drain. The INT pin
is greater than V
CC
. When set to a ‘0’, the INT pin
SWITCH
must be pulled up to Vcc by a 10k resistor while using the
interrupt in active LOW mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the Flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for Pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the Flags register is read. If the INT pin is used as a
host reset, the Flags register is not read during a reset
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can
be used to generate an interrupt. They are set by the watchdog
timeout, alarm match, or power fail monitor respectively. The
processor can either poll this register or enable interrupts when
a flag is set. These flags are automatically reset once the register
is read. The flags register is automatically loaded with the value
0x00 on power up (except for the OSCF bit. See “Stopping and
Starting the Oscillator” on page 6.)
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Figure 4. RTC Recommended Component Configuration
Recommended Values
Y
1
= 32.768 KHz (6 pF)
C
1
= 21 pF
C2 = 21 pF
X
1
X
2
Y1
C2
C1
Note: The recommended values for C1 and C2 include
board trace capacitance.
Watchdog
Timer
Power
Monitor
Clock
Alarm
VINT
WDF
WIE
PF
PFE
AF
AIE
P/L
Pin
Driver
H/L
INT
V
CC
V
SS
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Enable
Figure 5. Interrupt Block Diagram
Document #: 001-07103 Rev. *K Page 9 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Table 4. RTC Register Map
Note
8. Upper Byte D
15-D8
(CY14B104MA) of RTC registers are reserved for future use
9. ( ) designates values shipped from the factory.
10. This is a binary value, not a BCD value.
Register BCD Format Data
CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 D0
[8]
[9]
Function/Range
0x7FFFF 0x3FFFF 10s Years Years Years: 00–99
0x7FFFE 0x3FFFE 0 0 0 10s
Months Months: 01–12
Months
0x7FFFD 0x3FFFD 0 0 10s Day of Month Day Of Month Day of Month: 01–31
0x7FFFC 0x3FFFC 0 0 0 0 0 Day of week Day of week: 01–07
0x7FFFB 0x3FFFB 0 0 10s Hours Hours Hours: 00–23
0x7FFFA 0x3FFFA 0 10s Minutes Minutes Minutes: 00–59
0x7FFF9 0x3FFF9 0 10s Seconds Seconds Seconds: 00–59
0x7FFF8 0x3FFF8 OSCEN
(0)
0x7FFF7 0x3FFF7 WDS
0Cal Sign
Calibration (00000) Calibration Values
(0)
WDW (0) WDT (000000) Watchdog
(0)
0x7FFF6 0x3FFF6 WIE (0) AIE (0) PFE (0) 0 H/L
P/L (0) 0 0 Interrupts
(1)
0x7FFF5 0x3FFF5 M (1) 0 10s Alarm Date Alarm Day Alarm, Day of Month:
01–31
0x7FFF4 0x3FFF4 M (1) 0 10s Alarm Hours Alarm Hours Alarm, Hours: 00–23
0x7FFF3 0x3FFF3 M (1) 10 Alarm Minutes Alarm Minutes Alarm, Minutes:
00–59
0x7FFF2 0x3FFF2 M (1) 10 Alarm Seconds Alarm, Seconds Alarm, Seconds:
00–59
0x7FFF1 0x3FFF1 10s Centuries Centuries Centuries: 00–99
0x7FFF0 0x3FFF0 WDF AF PF OSCF 0 CAL (0) W (0) R (0) Flags
[10]
[10]
[10]
[10]
Document #: 001-07103 Rev. *K Page 10 of 31
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