Cypress CY14B101Q1, CY14B101Q2, CY14B101Q3 User Manual

PRELIMINARY

1 Mbit (128K x 8) Serial SPI nvSRAM

CY14B101Q1 CY14B101Q2 CY14B101Q3

Features

Instruction

Address Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction d ecode

Write protect Control logic

Quantum Trap

STORE

RECALL

SCK

CAP

HSB

128K X 8

SRAM ARRAY

128K X 8

A0-A16

D0-D7

HOLD

Logic Block Diagram

■ 1 Mbit NonVolatile SRAM ❐ Internally organized as 128K x 8

❐ STORE to QuantumTrap

tomatically on power down (AutoStore®) or by user using HSB pin (Hardware Store) or SPI instruction (Software Store)

❐ RECALL to SRAM initiated on power up (Power Up Recall

or by SPI Instruction (Software RECALL)

❐ Automatic STORE on power down with a small capacitor

■ High Reliability ❐ Infinite Read, Write, and RECALLl cycles

❐ 200,000 STORE cycles to QuantumTrap ❐ Data Retention: 20 Years

■ High Speed Serial Peripheral Interface (SPI) ❐ 40 MHz Clock rate ❐ Supports SPI Modes 0 (0,0) and 3 (1,1)

■ Write Protection ❐ Hardware Protection using Write Protect (WP) Pin

❐ Software Protection using Write Disable Instruction ❐ Software Block Protection for 1/4,1/2, or entire Array

nonvolatile elements initiated au-

■ Low Power Consumption ❐ Single 3V +20%, –10% operation ❐ Average Vcc current of 10 mA at 40 MHz operation

■ Industry Standard Configurations ❐ Commercial and industrial temperatures

)

❐ CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐ 8-pin DFN and 16-pin SOIC Packages ❐ RoHS compliant

Functional Overview

The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3 combines a 1 Mbit nonvolatile static RAM with a nonvolatile element in each memory cell. The memory is organized as 128K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cell provides highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). Both STORE and RECALL operations can also be triggered by the user.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 001-50091 Rev. *A Revised February 2, 2009

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PRELIMINARY

CY14B101Q1 CY14B101Q2 CY14B101Q3

Pinouts

CY14B101Q2

To p Vi e w

not to scale

CAP

GND

HOLD

SCK

CY14B101Q1

To p Vi e w

not to scale

GND

HOLD

SCK

GND

CAP

SCK

HSB

HOLD

CY14B101Q3

To p Vi e w

not to scale

1. HSB

pin is not available in 8 DFN packages.

2. CY14B101Q1A part does not have WP

pin.

3. CY14B101Q2A part does not have V

CAP

pin and does not support AutoStore.

Figure 1. Pin Diagram - 8-Pin DFN

Figure 2. Pin Diagram - 16-Pin SOIC

[1, 2, 3]

Table 1. Pin Definitions

Pin Name I/O Type Description

SCK Input Serial Clock. Runs at speeds up to max 40 MHz. All inputs are latched at the rising edge of this

SI Input Serial Input. Pin for input of all SPI instructions and data.

SO Output Serial Output. Pin for output of data through SPI.

HOLD

HSB

CAP

Input/Output Hardware STORE Busy: A weak internal pull up keeps this pin pulled high. If not used, this pin is

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the

NC No Connect No Connect: This pin is not connected to the die.

Document #: 001-50091 Rev. *A Page 2 of 22

GND Power Supply Ground

Power Supply Power Supply (2.7 to 3.6V)

Input Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low

power standby mode.

clock. Outputs are driven at the falling edge of the clock.

Input Write Protect. Implements hardware write protection in SPI.

Input HOLD Pin. Suspends Serial Operation.

left as No Connect. Output: Indicates busy status of nvSRAM when LOW. Input: Hardware STORE implemented by pulling this pin LOW externally.

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It must never be connected to GND.

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CY14B101Q1 CY14B101Q2 CY14B101Q3

Device Operation

CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence which transfers the data in parallel to the nonvolatile Quantum Trap cells. A small capacitor (V SRAM data in nonvolatile cells when power goes down providing power down data security. The Quantum Trap nonvolatile elements built in the reliable SONOS technology make nvSRAM the ideal choice for secure data storage.

The 1 Mbit memory array is organized as 128K words x 8 bits. The memory can be accessed through a standard SPI interface that enables very high clock speeds upto 40 MHz with zero cycle delay read and write cycles. This device supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 & 1, 1) and operates as SPI slave. The device is enabled using the Chip Select pin ( accessed through Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins.

This device provides the feature for hardware and software write protection through WP along with mechanisms for block write protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the status register. Further, the HOLD

pin can be used to suspend any serial communication

without resetting the serial sequence.

CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard SPI opcodes for memory access. In addition to the general SPI instructions for read and write, it provides four special instructions which enable access to four nvSRAM specific functions: STORE, RECALL, AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).

The major benefit of nvSRAM SPI over serial EEPROMs is that all reads and writes to nvSRAM are performed at the speed of SPI bus with zero delay. Therefore, no wait time is required after any of the memory accesses. The STORE and RECALL operations need finite time to complete and all memory accesses are inhibited during this time. While a STORE or RECALL operation is in progress, the busy status of the device is indicated by the Hardware STORE Busy (HSB the RDY

The Device is available in three different pin configurations that enable the user to choose a part which fits in best in their application

Table 2. Feature Summary

HSB

AutoStore No Yes Yes

Power Up RECALL

Hardware STORE

Software STORE

bit of the Status Register.

. The Feature summary is given in Table 2.

Feature CY14B101Q1 CY14B101Q2 CY14B101Q3

CAP

pin and WRDI instruction respectively

Yes No Ye s

No Yes Yes

No No Yes

Yes Yes Yes

No No Yes

Yes Yes Yes

) is used to AutoStore the

CAP

) pin and also reflected on

) and

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not use up any endurance cycles of the nonvolatile memory. This enables user to perform infinite write operations. A Write cycle is performed through the SPI WRITE instruction. The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode, three bytes of address, and one byte of data. Write to nvSRAM is done at SPI bus speed with zero cycle delay.

The device allows burst mode writes to be performed through SPI. This enables write operations on consecutive addresses without issuing a new WRITE instruction. When the last address in memory is reached, the address rolls over to 0x0000 and the device continues to write.

The SPI write cycle sequence is defined explicitly in the Memory Access section of SPI Protocol Description.

SRAM Read

A read cycle is performed at the SPI bus speed and the data is read out with zero cycle delay after the READ instruction is performed. The READ instruction is issued through the SI pin of the nvSRAM and consists of the READ opcode and 3 bytes of address. The data is read out on the SO pin.

This device allows burst mode reads to be performed through SPI. This enables reads on consecutive addresses without issuing a new READ instruction. When the last address in memory is reached in burst mode read, the address rolls over to 0x0000 and the device continues to read.

The SPI read cycle sequence is defined explicitly in the Memory Access section of SPI Protocol Description.

STORE Operation

STORE operation transfers the data from the SRAM to the nonvolatile Quantum Trap cells. The device stores data to the nonvolatile cells using one of three STORE operations: AutoStore, activated on device power down; Software STORE, activated by a STORE instruction in the SPI; Hardware STORE, activated by the HSB previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.

The HSB signal or the RDY bit in the Status register can be monitored by the system to detect if a STORE cycle is in progress. The busy status of nvSRAM is indicated by HSB pulled LOW or RDY nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place.

. During the STORE cycle, an erase of the

being

bit being set to ‘1’. To avoid unnecessary

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap during power down. This Store mechanism is implemented using a

Document #: 001-50091 Rev. *A Page 3 of 22

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PRELIMINARY

CY14B101Q1 CY14B101Q2 CY14B101Q3

capacitor (V

0.1uF

Vcc

10kOhm

CAP

Vcc

CAP

data in the nonvolatile memory when power goes down.

During normal operation, the device draws current from V charge the capacitor connected to the V voltage on the V the device inhibits all memory accesses to nvSRAM and

) and enables the device to safely STORE the

CAP

pin. When the

pin drops below V

CAP

during power down,

SWITCH

Figure 3. AutoStore Mode

automatically performs a conditional STORE operation using the charge from the V initiated if no write cycle has been performed since last RECALL.

capacitor. The AutoStore operation is not

CAP

During power down, the memory accesses are inhibited after the voltage on V writes, it must be ensured that CS

pin drops below V

. To avoid inadvertent

SWITCH

is not left floating prior to this event. Therefore, during power down the device must be deselected and CS must be allowed to follow VCC.

Figure 3 shows the proper connection of the storage capacitor

) for AutoStore operation. Refer to DC Electrical Charac-

CAP

teristics on page 13 for the size of the V

Note CY14B101Q1 does not support AutoStore operation. The user must perform Software STORE operation by using the SPI STORE instruction to secure the data.

CAP

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile Quantum Trap elements to the SRAM. A RECALL may be

Software Store Operation

Software STORE enables the user to trigger a STORE operation through a special SPI instruction. This operation is initiated irrespective of whether a write has been performed since last nv operation.

A STORE cycle takes t memory accesses to nvSRAM are inhibited. The RDY Status register or the HSB or Busy status of the nvSRAM. After the t completed, the SRAM is activated again for read and write operations.

to complete, during which all the

STORE

bit of the

pin may be polled to find the Ready

cycle time is

STORE

initiated in two ways: Hardware RECALL, initiated on power up; and Software RECALL, initiated by a SPI RECALL instruction.

Internally, RECALL is a two-step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. All memory accesses are inhibited while a RECALL cycle is in progress. The RECALL operation does not alter the data in the nonvolatile elements.

Hardware Recall (Power Up)

During power up, when VCC crosses V RECALL sequence is initiated which transfers the content of

SWITCH

nonvolatile memory on to the SRAM. The data would previously

Hardware STORE and HSB pin Operation

The HSB pin in CY14B101Q3 is used to control and acknowledge STORE operations. If no STORE or RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB initiates a STORE operation after t STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for t as HSB

The HSB

pin is LOW.

pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, when a STORE cycle (initiated by any means) or Power up RECALL is in progress. Upon completion of the STORE operation, the nvSRAM remains disabled until the HSB unconnected if not used.

Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY of the SPI status register may be probed to determine the Ready or Busy status of nvSRAM

pin is driven LOW, nvSRAM conditionally

duration. An actual

DELAY

duration or as long

STORE

pin returns HIGH. Leave the HSB pin

have been stored on the nonvolatile memory through a STORE sequence.

A Power Up Recall cycle takes t memory access is disabled during this time. HSB

time to complete and the

used to detect the Ready status of the device. user

Software RECALL

Software RECALL enables the user to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM. A Software RECALL is issued by using the SPI instruction for RECALL.

A Software RECALL takes t memory accesses to nvSRAM are inhibited. The controller must provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions.

Disabling and Enabling AutoStore

bit

If the application does not require the AutoStore feature, it can be disabled by using the ASDISB instruction. If this is done, the nvSRAM does not perform a STORE operation at power down.

to complete during which all

RECALL

AutoStore can be re-enabled by using the ASENB instruction. However, these operations are not nonvolatile and if the user needs this setting to survive power cycle, a STORE operation must be performed following Autostore Disable or Enable operation.

Document #: 001-50091 Rev. *A Page 4 of 22

, an automatic

pin can be

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CY14B101Q1 CY14B101Q2 CY14B101Q3

Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from

the factory. In CY14B101Q1, V AutoStore option is not available. The Autostore Enable and Disable instructions to CY14B101Q1 are ignored.

Note If AutoStore is disabled and V open. V Recall operation cannot be disabled in any case.

pin must never be connected to GND. Power Up

CAP

pin is not present and

CAP

is not required, leave it

CAP

Serial Peripheral Interface

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO) and Serial Clock (SCK) pins. CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial access to nvSRAM through SPI interface. The SPI bus on this device can run at speeds up to 40 MHz

The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on SPI bus is activated using a chip select pin.

The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both these modes, data is clocked into nvSRAM on rising edge of SCK starting from the first rising edge after CS

The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS master is the opcode. Following the opcode, any addresses and data are then transferred. The CS operation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are given below:

SPI Master

The SPI Master device controls the operations on a SPI bus. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and master may select any of the slave devices using the Chip Select pin. All the operations must be initiated by the master activating a slave device by pulling the CS also generates the Serial Clock (SCK) and all the data transmission on SI and SO lines are synchronized with this clock.

SPI Slave

SPI slave device is activated by the master through the Chip Select line. A slave device gets the Serial Clock (SCK) as an input from the SPI master and all the communication is synchronized with this clock. SPI slave never initiates a communication on the SPI bus and acts on the instruction from the master.

CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI slave and may share the SPI bus with other SPI slave devices.

Chip Select (CS

For selecting any slave device, the master needs to pull down the corresponding CS slave device only while the CS

is activated the first byte transferred from the bus

must go inactive after an

pin of the slave LOW. The master

)

pin. Any instruction can be issued to a

pin is LOW. When the device is

goes active.

not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high impedance state.

Note A new instruction must begin with the falling edge of Chip Select (CS active Chip Select cycle.

Serial Clock (SCK)

Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS

CY14B101Q1/CY14B101Q2/CY14B101Q3 enables SPI modes 0 and 3 for data communication. In both these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK.

Data Transmission - SI and SO

SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as MOSI (Master Out Slave In) and SO is referred to as MISO (Master In Slave Out). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission.

The 1 Mbit serial nvSRAM requires a 3-byte address for any read or write operation. However, since the actual address is only 17 bits, it implies that the first seven bits which are fed in are ignored by the device. Although these seven bits are ‘don’t care’, Cypress recommends that these bits are treated as 0s to enable seamless transition to higher memory densities.

Serial Opcode

After the slave device is selected with CS byte received is treated as the opcode for the intended operation. CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard opcodes for memory accesses. In addition to the memory accesses, it provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to Tabl e 3 on page 7 for details.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin and no valid data is sent out on the SO pin. Opcode for a new instruction is recognized only after the next falling edge of CS

Status Register

CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status register. The bits in the status register are used to configure the SPI bus. These bits are described in Tab l e 5 on page 8.

). Therefore, only one opcode can be issued for each

goes LOW.

going LOW, the first

Document #: 001-50091 Rev. *A Page 5 of 22

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Figure 4. System Configuration Using SPI nvSRAM

xQ101B41YCxQ101B41YC

uController

SCK

MOSI

MISO

SI SO OSISKCSSCK

HOLD HOLDCS

CS1

CS2

HOLD1

HOLD2

LSB

MSB

765432

SCK

0 1 2 3 4 5 6 7

SCK

765432

LSB

MSB

0 12 34 56 7

SPI Modes

CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

■ SPI Mode 0 (CPOL=0, CPHA=0)

■ SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched-in on the rising edge of Serial Clock (SCK) starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge, after the clock toggles, is considered. The output data is available on the falling edge of Serial Clock (SCK).

Figure 5. SPI Mode 0

The two SPI modes are shown in Figure 5 and Figure 6. The status of clock when the bus master is in Standby mode and not transferring data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for either Mode 0 or Mode 3. The device detects the SPI mode from the status of SCK pin when the device is selected by bringing the CS pin LOW. If SCK pin is LOW when device is selected, SPI Mode 0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3.

Figure 6. SPI Mode 3

Document #: 001-50091 Rev. *A Page 6 of 22

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CY14B101Q1 CY14B101Q2 CY14B101Q3

SPI Operating Features

Power Up

Power up is defined as the condition when the power supply is turned on and V Chip Select (CS Therefore, CS up resistor. As a built-in safety feature, Chip Select (CS edge sensitive and level sensitive. After power up, the device is not selected until a falling edge is detected on Chip Select (CS). This ensures that Chip Select (CS before going Low to start the first operation.

As described earlier, nvSRAM performs a Power Up Recall operation after power up and therefore, all memory accesses are disabled for t be probed to check the ready or busy status of nvSRAM after power up.

Power On Reset

A Power On Reset (POR) circuit is included to prevent inadvertent writes. At power up, the device does not respond to any instruction until the VCC reaches the Power On Reset threshold voltage (V threshold, the device is internally reset and performs an Power Up Recall operation. The device is in the following state after POR:

■ Deselected (after Power up, a falling edge is required on Chip

Select (CS

■ Standby Power mode

■ Not in the Hold Condition

■ Status register state:

❐ Write Enable (WEN) bit is reset to 0. ❐ WPEN, BP1, BP0 unchanged from previous power down

The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous power down.

Before selecting and issuing instructions to the memory, a valid and stable V remain valid until the end of the transmission of the instruction.

Power Down

At power down (continuous decay of VCC), when VCC drops from the normal operating voltage and below the V voltage, the device stops responding to any instruction sent to it. If a write cycle is in progress during power down, it is allowed t

time to complete after Vcc transitions below V

DELAY

after which all memory accesses are inhibited and a conditional AutoStore operation is performed (AutoStore is not performed if no writes have happened since last RECALL cycle). This feature prevents inadvertent writes to nvSRAM from happening during power down.

However, to completely avoid the possibility of inadvertent writes during power down, ensure that the device is deselected and is in Standby Power Mode, and the Chip Select (CS voltage applied on V

crosses Vswitch voltage. During this time, the

) must be allowed to follow the VCC voltage.

must be connected to VCC through a suitable pull

) is both

) must have been HIGH,

duration after power up. The HSB pin can

RECALL

). After VCC transitions the POR

SWITCH

) before any instructions are started).

voltage must be applied. This voltage must

threshold

SWITCH

) follows the

Active Power and Standby Power Modes

When Chip Select (CS) is LOW, the device is selected, and is in the Active Power mode. The device consumes I specified in DC Electrical Characteristics on page 13. When Chip Select (CS

) is HIGH, the device is deselected and the device

goes into the Standby Power mode if a STORE or RECALL cycle is not in progress. If a STORE or RECALL cycle is in progress, device goes into the Standby Power Mode after the STORE or RECALL cycle is completed. In the Standby Power mode, the current drawn by the device drops to I

SPI Functional Description

The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit instruction register. Instructions and their opcodes are listed in

Ta bl e 3 . All instructions, addresses, and data are transferred with

the MSB first and start with a HIGH to LOW CS are, in all, 12 SPI instructions which provide access to most of the functions in nvSRAM. Further, the WP provide additional functionality driven through hardware.

Table 3. Instruction Set

Instruction

Cypress CY14B101Q1, CY14B101Q2, CY14B101Q3 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Logic Block Diagram

Functional Overview

Pinouts

Device Operation

SRAM Write

SRAM Read

STORE Operation

AutoStore Operation

RECALL Operation

Software Store Operation

Hardware Recall (Power Up)

Hardware STORE and HSB pin Operation

Software RECALL

Disabling and Enabling AutoStore

Serial Peripheral Interface

SPI Overview

SPI Master

SPI Slave

Serial Clock (SCK)

Data Transmission - SI and SO

Most Significant Bit (MSB)

Serial Opcode

Invalid Opcode

Status Register

SPI Modes

SPI Operating Features

Power Up

Power On Reset

Power Down

Active Power and Standby Power Modes

SPI Functional Description