Cypress CY14B101Q1, CY14B101Q2, CY14B101Q3 User Manual

PRELIMINARY

1 Mbit (128K x 8) Serial SPI nvSRAM

CY14B101Q1
CY14B101Q2
CY14B101Q3

Features

Instruction

register

Address
Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction d ecode

Write protect
Control logic

Quantum Trap

STORE

RECALL

SI

SCK

V

CC

V

CAP

SO

HSB

128K X 8

SRAM ARRAY

128K X 8

A0-A16

D0-D7

HOLD

CS

WP

Logic Block Diagram

■ 1 Mbit NonVolatile SRAM
❐ Internally organized as 128K x 8

❐ STORE to QuantumTrap

tomatically on power down (AutoStore®) or by user using
HSB pin (Hardware Store) or SPI instruction (Software Store)

❐ RECALL to SRAM initiated on power up (Power Up Recall

or by SPI Instruction (Software RECALL)

❐ Automatic STORE on power down with a small capacitor

■ High Reliability
❐ Infinite Read, Write, and RECALLl cycles

❐ 200,000 STORE cycles to QuantumTrap
❐ Data Retention: 20 Years

■ High Speed Serial Peripheral Interface (SPI)
❐ 40 MHz Clock rate
❐ Supports SPI Modes 0 (0,0) and 3 (1,1)

■ Write Protection
❐ Hardware Protection using Write Protect (WP) Pin

❐ Software Protection using Write Disable Instruction
❐ Software Block Protection for 1/4,1/2, or entire Array

®

nonvolatile elements initiated au-

■ Low Power Consumption
❐ Single 3V +20%, –10% operation
❐ Average Vcc current of 10 mA at 40 MHz operation

■ Industry Standard Configurations
❐ Commercial and industrial temperatures

®

)

❐ CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐ 8-pin DFN and 16-pin SOIC Packages
❐ RoHS compliant

Functional Overview

The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nonvolatile static RAM with a nonvolatile
element in each memory cell. The memory is organized as 128K
words of 8 bits each. The embedded nonvolatile elements incor­porate the QuantumTrap technology, creating the world’s most
reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while the QuantumTrap cell provides highly
reliable nonvolatile storage of data. Data transfers from SRAM to
the nonvolatile elements (STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
Both STORE and RECALL operations can also be triggered by
the user.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-50091 Rev. *A Revised February 2, 2009

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Pinouts

CY14B101Q2

To p Vi e w

not to scale

CS

SO

V

CAP

GND

V

CC

HOLD

SCK

SI

CY14B101Q1

To p Vi e w

not to scale

CS

SO

WP

GND

V

CC

HOLD

SCK

SI

NC

GND

WP

V

CAP

1

2

3

4

5

6

7

8

9

10

11

12

13

NC

16

15

14

V

CC

SO

SI

SCK

CS

HSB

NC

NC

NC

HOLD

NC

CY14B101Q3

To p Vi e w

not to scale

1. HSB

pin is not available in 8 DFN packages.

2. CY14B101Q1A part does not have WP

pin.

3. CY14B101Q2A part does not have V

CAP

pin and does not support AutoStore.

Figure 1. Pin Diagram - 8-Pin DFN

Figure 2. Pin Diagram - 16-Pin SOIC

[1, 2, 3]

Table 1. Pin Definitions

Pin Name I/O Type Description

CS

SCK Input Serial Clock. Runs at speeds up to max 40 MHz. All inputs are latched at the rising edge of this

SI Input Serial Input. Pin for input of all SPI instructions and data.

SO Output Serial Output. Pin for output of data through SPI.

WP

HOLD

HSB

V

CAP

Input/Output Hardware STORE Busy: A weak internal pull up keeps this pin pulled high. If not used, this pin is

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the

NC No Connect No Connect: This pin is not connected to the die.

V

CC

Document #: 001-50091 Rev. *A Page 2 of 22

GND Power Supply Ground

Power Supply Power Supply (2.7 to 3.6V)

Input Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low

power standby mode.

clock. Outputs are driven at the falling edge of the clock.

Input Write Protect. Implements hardware write protection in SPI.

Input HOLD Pin. Suspends Serial Operation.

left as No Connect.
Output: Indicates busy status of nvSRAM when LOW.
Input: Hardware STORE implemented by pulling this pin LOW externally.

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to GND.

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CY14B101Q1
CY14B101Q2
CY14B101Q3

Device Operation

CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM
memory with a nonvolatile element in each memory cell. All the
reads and writes to nvSRAM happen to the SRAM which gives
nvSRAM the unique capability to handle infinite writes to the
memory. The data in SRAM is secured by a STORE sequence
which transfers the data in parallel to the nonvolatile Quantum
Trap cells. A small capacitor (V
SRAM data in nonvolatile cells when power goes down providing
power down data security. The Quantum Trap nonvolatile
elements built in the reliable SONOS technology make nvSRAM
the ideal choice for secure data storage.

The 1 Mbit memory array is organized as 128K words x 8 bits.
The memory can be accessed through a standard SPI interface
that enables very high clock speeds upto 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 & 1, 1) and operates as SPI slave.
The device is enabled using the Chip Select pin (
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.

This device provides the feature for hardware and software write
protection through WP
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the status register. Further, the
HOLD

pin can be used to suspend any serial communication

without resetting the serial sequence.

CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).

The major benefit of nvSRAM SPI over serial EEPROMs is that
all reads and writes to nvSRAM are performed at the speed of
SPI bus with zero delay. Therefore, no wait time is required after
any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB
the RDY

The Device is available in three different pin configurations that
enable the user to choose a part which fits in best in their appli­cation

Table 2. Feature Summary

WP

V

HSB

AutoStore No Yes Yes

Power Up
RECALL

Hardware
STORE

Software
STORE

bit of the Status Register.

. The Feature summary is given in Table 2.

Feature CY14B101Q1 CY14B101Q2 CY14B101Q3

CAP

pin and WRDI instruction respectively

Yes No Ye s

No Yes Yes

No No Yes

Yes Yes Yes

No No Yes

Yes Yes Yes

) is used to AutoStore the

CAP

) pin and also reflected on

CS

) and

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables user to perform infinite write operations. A Write cycle is
performed through the SPI WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.

The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached, the address rolls over to 0x0000 and the
device continues to write.

The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.

SRAM Read

A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
performed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and 3 bytes of
address. The data is read out on the SO pin.

This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.

The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.

STORE Operation

STORE operation transfers the data from the SRAM to the
nonvolatile Quantum Trap cells. The device stores data to the
nonvolatile cells using one of three STORE operations:
AutoStore, activated on device power down; Software STORE,
activated by a STORE instruction in the SPI; Hardware STORE,
activated by the HSB
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.

The HSB signal or the RDY bit in the Status register can be
monitored by the system to detect if a STORE cycle is in
progress. The busy status of nvSRAM is indicated by HSB
pulled LOW or RDY
nonvolatile STOREs, AutoStore and Hardware STORE opera­tions are ignored unless at least one write operation has taken
place since the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of whether a
write operation has taken place.

. During the STORE cycle, an erase of the

being

bit being set to ‘1’. To avoid unnecessary

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap during
power down. This Store mechanism is implemented using a

Document #: 001-50091 Rev. *A Page 3 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

capacitor (V

0.1uF

Vcc

10kOhm

V

CAP

Vcc

CS

V

CAP

V

SS

data in the nonvolatile memory when power goes down.

During normal operation, the device draws current from V
charge the capacitor connected to the V
voltage on the V
the device inhibits all memory accesses to nvSRAM and

) and enables the device to safely STORE the

CAP

pin. When the

pin drops below V

CC

CAP

during power down,

SWITCH

CC

Figure 3. AutoStore Mode

to

automatically performs a conditional STORE operation using the
charge from the V
initiated if no write cycle has been performed since last RECALL.

capacitor. The AutoStore operation is not

CAP

During power down, the memory accesses are inhibited after the
voltage on V
writes, it must be ensured that CS

pin drops below V

CC

. To avoid inadvertent

SWITCH

is not left floating prior to this
event. Therefore, during power down the device must be
deselected and CS must be allowed to follow VCC.

Figure 3 shows the proper connection of the storage capacitor

(V

) for AutoStore operation. Refer to DC Electrical Charac-

CAP

teristics on page 13 for the size of the V

Note CY14B101Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.

CAP

.

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile
Quantum Trap elements to the SRAM. A RECALL may be

Software Store Operation

Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. This operation is initiated
irrespective of whether a write has been performed since last nv
operation.

A STORE cycle takes t
memory accesses to nvSRAM are inhibited. The RDY
Status register or the HSB
or Busy status of the nvSRAM. After the t
completed, the SRAM is activated again for read and write
operations.

to complete, during which all the

STORE

bit of the

pin may be polled to find the Ready

cycle time is

STORE

initiated in two ways: Hardware RECALL, initiated on power up;
and Software RECALL, initiated by a SPI RECALL instruction.

Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared. Next, the nonvolatile information is transferred
into the SRAM cells. All memory accesses are inhibited while a
RECALL cycle is in progress. The RECALL operation does not
alter the data in the nonvolatile elements.

Hardware Recall (Power Up)

During power up, when VCC crosses V
RECALL sequence is initiated which transfers the content of

SWITCH

nonvolatile memory on to the SRAM. The data would previously

Hardware STORE and HSB pin Operation

The HSB pin in CY14B101Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB
initiates a STORE operation after t
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for t
as HSB

The HSB

pin is LOW.

pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, when a STORE cycle
(initiated by any means) or Power up RECALL is in progress.
Upon completion of the STORE operation, the nvSRAM remains
disabled until the HSB
unconnected if not used.

Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY
of the SPI status register may be probed to determine the Ready
or Busy status of nvSRAM

pin is driven LOW, nvSRAM conditionally

duration. An actual

DELAY

duration or as long

STORE

pin returns HIGH. Leave the HSB pin

have been stored on the nonvolatile memory through a STORE
sequence.

A Power Up Recall cycle takes t
memory access is disabled during this time. HSB

time to complete and the

FA

used to detect the Ready status of the device. user

Software RECALL

Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.

A Software RECALL takes t
memory accesses to nvSRAM are inhibited. The controller must
provide sufficient delay for the RECALL operation to complete
before issuing any memory access instructions.

Disabling and Enabling AutoStore

bit

If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power down.

to complete during which all

RECALL

AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
needs this setting to survive power cycle, a STORE operation
must be performed following Autostore Disable or Enable
operation.

Document #: 001-50091 Rev. *A Page 4 of 22

, an automatic

pin can be

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from

the factory. In CY14B101Q1, V
AutoStore option is not available. The Autostore Enable and
Disable instructions to CY14B101Q1 are ignored.

Note If AutoStore is disabled and V
open. V
Recall operation cannot be disabled in any case.

pin must never be connected to GND. Power Up

CAP

pin is not present and

CAP

is not required, leave it

CAP

Serial Peripheral Interface

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO) and Serial Clock (SCK) pins.
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial
access to nvSRAM through SPI interface. The SPI bus on this
device can run at speeds up to 40 MHz

The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using a chip select
pin.

The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into nvSRAM on rising edge
of SCK starting from the first rising edge after CS

The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:

SPI Master

The SPI Master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and master
may select any of the slave devices using the Chip Select pin.
All the operations must be initiated by the master activating a
slave device by pulling the CS
also generates the Serial Clock (SCK) and all the data trans­mission on SI and SO lines are synchronized with this clock.

SPI Slave

SPI slave device is activated by the master through the Chip
Select line. A slave device gets the Serial Clock (SCK) as an
input from the SPI master and all the communication is synchro­nized with this clock. SPI slave never initiates a communication
on the SPI bus and acts on the instruction from the master.

CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI
slave and may share the SPI bus with other SPI slave devices.

Chip Select (CS

For selecting any slave device, the master needs to pull down
the corresponding CS
slave device only while the CS

is activated the first byte transferred from the bus

must go inactive after an

pin of the slave LOW. The master

)

pin. Any instruction can be issued to a

pin is LOW. When the device is

goes active.

not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.

Note A new instruction must begin with the falling edge of Chip
Select (CS
active Chip Select cycle.

Serial Clock (SCK)

Serial clock is generated by the SPI master and the communi­cation is synchronized with this clock after CS

CY14B101Q1/CY14B101Q2/CY14B101Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.

Data Transmission - SI and SO

SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as MOSI (Master Out
Slave In) and SO is referred to as MISO (Master In Slave Out).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.

The 1 Mbit serial nvSRAM requires a 3-byte address for any read
or write operation. However, since the actual address is only 17
bits, it implies that the first seven bits which are fed in are ignored
by the device. Although these seven bits are ‘don’t care’,
Cypress recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.

Serial Opcode

After the slave device is selected with CS
byte received is treated as the opcode for the intended operation.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. Refer to Tabl e 3 on page 7 for details.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin and no
valid data is sent out on the SO pin. Opcode for a new instruction
is recognized only after the next falling edge of CS

Status Register

CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status
register. The bits in the status register are used to configure the
SPI bus. These bits are described in Tab l e 5 on page 8.

). Therefore, only one opcode can be issued for each

goes LOW.

going LOW, the first

.

Document #: 001-50091 Rev. *A Page 5 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

Figure 4. System Configuration Using SPI nvSRAM

xQ101B41YCxQ101B41YC

uController

SCK

MOSI

MISO

SI SO OSISKCSSCK

CS

HOLD HOLDCS

CS1

CS2

HOLD1

HOLD2

LSB

MSB

765432

10

CS

SCK

SI

0 1 2 3 4 5 6 7

CS

SCK

SI

765432

10

LSB

MSB

0 12 34 56 7

SPI Modes

CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a
microcontroller with its SPI peripheral running in either of the
following two modes:

■ SPI Mode 0 (CPOL=0, CPHA=0)

■ SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched-in on the rising edge
of Serial Clock (SCK) starting from the first rising edge after CS
goes active. If the clock starts from a HIGH state (in mode 3), the
first rising edge, after the clock toggles, is considered. The output
data is available on the falling edge of Serial Clock (SCK).

Figure 5. SPI Mode 0

The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in Standby mode and not
transferring data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for either
Mode 0 or Mode 3. The device detects the SPI mode from the
status of SCK pin when the device is selected by bringing the CS
pin LOW. If SCK pin is LOW when device is selected, SPI Mode
0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3.

Figure 6. SPI Mode 3

Document #: 001-50091 Rev. *A Page 6 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

SPI Operating Features

Power Up

Power up is defined as the condition when the power supply is
turned on and V
Chip Select (CS
Therefore, CS
up resistor. As a built-in safety feature, Chip Select (CS
edge sensitive and level sensitive. After power up, the device is
not selected until a falling edge is detected on Chip Select (CS).
This ensures that Chip Select (CS
before going Low to start the first operation.

As described earlier, nvSRAM performs a Power Up Recall
operation after power up and therefore, all memory accesses are
disabled for t
be probed to check the ready or busy status of nvSRAM after
power up.

Power On Reset

A Power On Reset (POR) circuit is included to prevent
inadvertent writes. At power up, the device does not respond to
any instruction until the VCC reaches the Power On Reset
threshold voltage (V
threshold, the device is internally reset and performs an Power
Up Recall operation. The device is in the following state after
POR:

■ Deselected (after Power up, a falling edge is required on Chip

Select (CS

■ Standby Power mode

■ Not in the Hold Condition

■ Status register state:

❐ Write Enable (WEN) bit is reset to 0.
❐ WPEN, BP1, BP0 unchanged from previous power down

The WPEN, BP1, and BP0 bits of the Status Register are nonvol­atile bits and remain unchanged from the previous power down.

Before selecting and issuing instructions to the memory, a valid
and stable V
remain valid until the end of the transmission of the instruction.

Power Down

At power down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the V
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress during power down, it is allowed
t

time to complete after Vcc transitions below V

DELAY

after which all memory accesses are inhibited and a conditional
AutoStore operation is performed (AutoStore is not performed if
no writes have happened since last RECALL cycle). This feature
prevents inadvertent writes to nvSRAM from happening during
power down.

However, to completely avoid the possibility of inadvertent writes
during power down, ensure that the device is deselected and is
in Standby Power Mode, and the Chip Select (CS
voltage applied on V

crosses Vswitch voltage. During this time, the

CC

) must be allowed to follow the VCC voltage.

must be connected to VCC through a suitable pull

) is both

) must have been HIGH,

duration after power up. The HSB pin can

RECALL

). After VCC transitions the POR

SWITCH

) before any instructions are started).

voltage must be applied. This voltage must

CC

threshold

SWITCH

SWITCH

) follows the

.

CC

Active Power and Standby Power Modes

When Chip Select (CS) is LOW, the device is selected, and is in
the Active Power mode. The device consumes I
specified in DC Electrical Characteristics on page 13. When Chip
Select (CS

) is HIGH, the device is deselected and the device

CC

goes into the Standby Power mode if a STORE or RECALL cycle
is not in progress. If a STORE or RECALL cycle is in progress,
device goes into the Standby Power Mode after the STORE or
RECALL cycle is completed. In the Standby Power mode, the
current drawn by the device drops to I

SB

.

SPI Functional Description

The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit
instruction register. Instructions and their opcodes are listed in

Ta bl e 3 . All instructions, addresses, and data are transferred with

the MSB first and start with a HIGH to LOW CS
are, in all, 12 SPI instructions which provide access to most of
the functions in nvSRAM. Further, the WP
provide additional functionality driven through hardware.

Table 3. Instruction Set

Instruction

Category

Instruction

Name

Opcode Operation

WREN 0000 0110 Set Write Enable

Status Register
Control Instruc-

tions

WRDI 0000 0100 Reset Write

RDSR 0000 0101 Read Status

WRSR 0000 0001 Write Status

SRAM

Read/Write

Instructions

READ 0000 0011 Read Data From

WRITE 0000 0010 Write Data To

STORE 0011 1100 Software STORE

Special NV

Instructions

RECALL 0110 0000 Software

ASENB 0101 1001 AutoStore Enable

ASDISB 0001 1001 AutoStore Disable

Reserved - Reserved - 0001 1110 Reserved for

,

The SPI instructions are divided based on their functionality in
the following types:

❐ Status Register Access: WRSR and RDSR instructions
❐ Write Protection Functions: WREN and WRDI instructions

along with WP pin and WEN, BP0, and BP1 bits

❐ SRAM memory Access: READ and WRITE instructions
❐ nvSRAM special instructions: STORE, RECALL, ASENB,

and ASDISB

transition. There

and HOLD pins

Enable Latch

Register

Register

Memory Array

Memory Array

RECALL

Internal use

current, as

Latch

Document #: 001-50091 Rev. *A Page 7 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Status Register

CS

SCK

SO

01234567

SI

000001001

MSB

LSB

HI-Z

012345 67

Data

LSB

D0D1

D2

D3

D4

D5D6

MSB

D7

The status register bits are listed in Ta bl e 3 . The status register
consists of Ready bit (RDY
WEN, and WPEN. The RDY
or Busy status while a nvSRAM STORE cycle is in progress. The

) and data protection bits BP1, BP0,

bit can be polled to check the Ready

RDSR instruction. However, only WPEN, BP1, and BP0 bits of
the Status Register can be modified by using WRSR instruction.
WRSR instruction has no effect on WEN and RDY

bits. The
default value shipped from the factory for BP1, BP2 and WPEN
bits is ‘0’.

status register can be modified by WRSR instruction and read by

Table 4. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN (0) X X X BP1 (0) BP0 (0) WEN RDY

Table 5. Status Register Bit Definition

Bit Definition Description

Bit 0 (RDY

) Ready Read Only bit indicates the ready status of device to perform a memory access. This bit is

set to “1” by the device while a STORE or Software RECALL cycle is in progress.

Bit 1 (WEN) Write Enable WEN indicates if the device is write-enabled. Setting WEN = '1' enables writes and setting

WEN = '0' disables all write operations

Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details see Tab l e 6 on page 9.

Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details see Tab l e 6 on page 9.

Bit 7 (WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP

). For details see Tab l e 7 on page 10.

Read Status Register (RDSR) Instruction

The Read Status Register instruction provides access to the
status register. This instruction is used to probe the Write Enable
Status of the device or the Ready status of the device. RDY bit
is set by the device to 1 whenever a STORE cycle is in progress.
The Block Protection and WPEN bits indicate the extent of
protection employed.

This instruction is issued after the falling edge of CS

using the

opcode for RDSR.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status
register. However, this instruction cannot be used to modify bit 0
and bit 1 (WEN and RDY
to select one of four levels of block protection. Further, WPEN bit
can be set to ‘1’ to enable the use of Write Protect (WP) pin.

). The BP0 and BP1 bits can be used

Figure 7. Read Status Register (RDSR) Instruction Timing

WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by 8 bits of data to be
stored in the Status Register. Since, only bits 2, 3, and 7 can be
modified by WRSR instruction, it is recommended to leave the
other bits as ‘0’ while writing to the Status Register

Note In CY14B101Q1/CY14B101Q2/CY14B101Q3, the values
written to Status Register are saved to nonvolatile memory only
after a STORE operation. If AutoStore is disabled (or while using
CY14B101Q1), any modifications to the Status Register must be
secured by using a Software STORE operation

Note CY14B101Q2 does not have WP

pin. Any modification to
bit 7 of the Status register has no effect on the functionality of
CY14B101Q2.

Document #: 001-50091 Rev. *A Page 8 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

Figure 8. Write Status Register (WRSR) Instruction Timing

CS

SCK

SO

0123 4567

SI

0000000

1

MSB

LSB

0

0

D2

D3

0

00D7

HI-Z

012345 67

Opcode

Data in

0 0 0 0 0 1 1 0

CS

SCK

SI

SO

Hi-Z

0 1 2 3 4 5 6 7

0 00 00 1 00

CS

SCK

SI

SO

Hi-Z

0 1 2 3 4 5 6 7

Write Protection and Block Protection

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features
for both software and hardware write protection using WRDI
instruction and WP. Additionally, this device also provides block
protection mechanism through BP0 and BP1 pins of the Status
Register.

The write enable and disable status of the device is indicated by
WEN bit of the status register. The write instructions (WRSR and
WRITE) and nvSRAM special instruction (STORE, RECALL,
ASENB, and ASDISB) need the write to be enabled (WEN bit =

1) before they can be issued.

Write Enable (WREN) Instruction

On power up, the device is always in the write disable state. The
following WRITE, WRSR, or nvSRAM special instruction must
therefore be preceded by a Write Enable instruction. If the device
is not write enabled (WEN = ‘0’), it ignores the write instructions
and returns to the standby state when CS
new CS

falling edge is required to re-initiate serial communi­cation. The instruction is issued following the falling edge of CS
When this instruction is used, the WEN bit of status register is
set to ‘1’. WEN bit defaults to ‘0’ on power up.

Note After completion of a write instruction (WRSR or WRITE)
or nvSRAM special instruction (STORE, RECALL, ASENB, and
ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to
provide protection from any inadvertent writes. Therefore,
WREN instruction needs to be used before a new write
instruction is issued.

Figure 9. WREN Instruction

is brought HIGH. A

Write Disable (WRDI) Instruction

Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following falling edge of CS
opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.

Figure 10. WRDI Instruction

.

Block Protection

Block protection is provided using the BP0 and BP1 pins of the
Status register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Tab le 6 shows the function of
Block Protect bits.

Table 6. Block Write Protect Bits

Status Register

Level

000 None

1 (1/4) 0 1 0x18000-0x1FFFF

2 (1/2) 1 0 0x10000-0x1FFFF

3 (All) 1 1 0x00000-0x1FFFF

Bits

BP1 BP0

Array Addresses Protected

followed by

Document #: 001-50091 Rev. *A Page 9 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Write Protect (WP) Pin

~

CS

SCK

SO

012345 67

0

765432

1

20212223012345 67

MSB LSB

Data

SI

~

~

Op-Code

0000001

0000

0 0

1

0

A16

A3

A1A2

A0

17-bit Address

MSB LSB

D0

D1

D2

D3

D4

D5

D6

D7

The write protect pin (WP) is used to provide hardware write
protection. WP
when held HIGH. When the WP
bit is “1”, all write operations to the status register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is “0”. This enables the user to install the device in a
system with the WP
register.

WP

pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the status register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to “1”, any modifications
to status register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP
any modification of the status register bits, providing hardware
write protection.

Note WP
of the ongoing write operations to the status register.

Note CY14B101Q2 does not have WP
not provide hardware write protection.

Ta bl e 7 summarizes all the protection features of this device

Table 7. Write Protection Operation

WPEN WP WEN

X X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 LOW 1 Protected Writable Protected

1 HIGH 1 Protected Writable Writable

pin enables all normal read and write operations

pin is brought LOW and WPEN

pin tied to ground, and still write to the status

pin inhibits

going LOW when CS is still LOW has no effect on any

pin and therefore does

Protected

Blocks

Unprotected

Blocks

Status

Register

Memory Access

All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY

Read Sequence (READ)

The read operations on this device are performed by giving the
instruction on Serial Input pin (SI) and reading the output on

bit of the status register and the HSB pin.

Serial Output (SO) pin. The following sequence needs to be
followed for a read operation: After the CS
select a device, the read opcode is transmitted through the SI
line followed by three bytes of address. The Most Significant
address byte contains A16 in bit 0 and other bits as ‘don’t cares’.
Address bits A15 to A0 are sent in the following two address
bytes. After the last address bit is transmitted on the SI pin, the
data (D7-D0) at the specific address is shifted out on the SO line
on the falling edge of SCK. Any other data on SI line after the last
address bit is ignored.

CY14B101Q1/CY14B101Q2/CY14B101Q3 allows reads to be
performed in bursts through SPI which can be used to read
consecutive addresses without issuing a new READ instruction.
If only one byte is to be read, the CS
after one byte of data comes out. However, the read sequence
may be continued by holding the CS
is automatically incremented and data continues to shift out on
SO pin. When the last data memory address (0x1FFFF) is
reached, the address rolls over to 0x0000 and the device
continues to read.

line is pulled LOW to

line must be driven HIGH

line LOW and the address

Write Sequence (WRITE)

The write operations on this device are performed through the
Serial Input (SI) pin. To perform a write operation, if the device is
write disabled, then the device must first be write enabled
through the WREN instruction. When the writes are enabled
(WEN = ‘1’), WRITE instruction is issued after the falling edge of
CS

. A WRITE instruction constitutes transmitting the WRITE
opcode on SI line followed by 3 bytes address sequence and the
data (D7-D0) which is to be written. The Most Significant address
byte contains A16 in bit 0 with other bits being ‘don’t cares’.
Address bits A15 to A0 are sent in the following two address
bytes.

CY14B101Q1/CY14B101Q2/CY14B101Q3 enables writes to be
performed in bursts through SPI which can be used to write
consecutive addresses without issuing a new WRITE instruction.
If only one byte is to be written, the CS
after the D0 (LSB of data) is transmitted. However, if more bytes
are to be written, CS line must be held LOW and address is
incremented automatically. The following bytes on the SI line are
treated as data bytes and written in the successive addresses.
When the last data memory address (0x1FFFF) is reached, the
address rolls over to 0x0000 and the device continues to write.
The WEN bit is reset to “0” on completion of a WRITE sequence.

line must be driven HIGH

Figure 11. Read Instruction Timing

Document #: 001-50091 Rev. *A Page 10 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

Figure 12. Burst Mode Read Instruction Timing

CS

SCK

SO

LSB

SI

Op-Code

17-bit Address

MSB

LSB

~

~

~

01 2 3 456 7

0

765432

1

20 21 22 23

01234567 01234567

~

0

7

0000 00

11 0 0 00 00 0

A16

A3 A2 A1 A0

D0

D1

D2D3

D4

D5

D6

D7

Data Byte 1

Data Byte N

MSB

LSB

MSB

D0

D1

D2D3

D4

D5

D6

D7

D0D7

~

CS

SCK

SO

01234 5 6 7

0

765432

1

2021222301234567

MSB LSB

Data

D0D1

D2

D3

D4

D5D6D7

SI

~

~

Op-Code

00 00001

000 0

0

0

0

0

A16 A3

A1A2

A0

17-bit Address

MSB LSB

HI-Z

~

CS

SCK

SO

MSB

LSB

SI

Op-Code

17-bit Address

MSB

LSB

~~~

01 234567

0

76 5 432

1

20 21

22 23

01 234567 01 234567

~

0

7

0 00000

100000000

A16

A3 A2 A1 A0

HI-Z

Data Byte 1

Data Byte N

D0

D1

D2D3

D4

D5

D6

D7

D0

D1

D2D3

D4

D5

D6

D7

D0D7

~

~

Figure 13. Write Instruction Timing

Figure 14. Burst Mode Write Instruction Timing

~

~

nvSRAM Special Instructions

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four
special instructions which enables access to four nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.

Ta bl e 8 lists these instructions.

Software STORE

When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is issued
irrespective of whether a write has taken place since last STORE
or RECALL operation.

Document #: 001-50091 Rev. *A Page 11 of 22

~

~

~

Table 8. nvSRAM Special Instructions

Function Name Opcode Operation

STORE 0011 1100 Software STORE

RECALL 0110 0000 Software RECALL

ASENB 0101 1001 AutoStore Enable

ASDISB 0001 1001 AutoStore Disable

To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS

. The WEN

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

bit is cleared on the positive edge of CS

0 0 1 1 1 1 0 0

CS

SCK

SI

SO

Hi-Z

0 1 2 3 4 5 6 7

0 1 1 0 0 0 0 0

CS

SCK

SI

0 1 2 3 4 5 6 7

SO

Hi-Z

0 0 0 1 1 0 0 1

CS

SCK

SI

SO

Hi-Z

0 1 2 3 4 5 6 7

0 1 0 1 1 0 0 1

CS

SCK

SI

SO

Hi-Z

0 1 2 3 4 5 6 7

~

~

~

CS

SCK

HOLD

SO

instruction.

Figure 15. Software STORE Operation

following the STORE

AutoStore Enable (ASENB)

The AutoStore Enable instruction enables the AutoStore on
CY14B101Q1. This setting is not nonvolatile and needs to be
followed by a STORE sequence to survive the power cycle.

To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASENB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS
instruction.

Note If ASDISB and ASENB instructions are executed in
CY14B101Q1, the device is busy for the duration of software
sequence processing time (t
instructions have no effect on CY14B101Q1 as AutoStore is

). However, ASDISB and ASENB

SS

internally disabled.

following the ASENB

Software RECALL

When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be write enabled (WEN = ‘1’).

The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS
cleared on the positive edge of CS

following the RECALL

. The WEN bit is

instruction.

Figure 16. Software RECALL Operation

AutoStore Disable (ASDISB)

AutoStore is enabled by default in CY14B101Q2/CY14B101Q3.
The ASDISB instruction disables the AutoStore. This setting is
not nonvolatile and needs to be followed by a STORE sequence
to survive the power cycle.

To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASDISB
opcode on the SI pin following the falling edge of CS
bit is cleared on the positive edge of CS

following the ASDISB

instruction.

Figure 17. AutoStore Disable Operation

. The WEN

Figure 18. AutoStore Enable Operation

HOLD Pin Operation

The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD

pin must be brought LOW when the SCK pin is LOW. To
resume serial communication, the HOLD
HIGH when the SCK pin is LOW (SCK may toggle during HOLD
While the device serial communication is paused, inputs to the
SI pin are ignored and the SO pin is in the high impedance state.

This pin can be used by the master with the CS pin to pause the
serial communication by bringing the pin HOLD
deselecting an SPI slave to establish communication with
another slave device, without the serial communication being
reset. The communication may be resumed at a later point by
selecting the device and setting the HOLD

Figure 19. HOLD Operation

pin must be brought

LOW and

pin HIGH.

~

).

Document #: 001-50091 Rev. *A Page 12 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

Maximum Ratings

Notes

4. The HSB

pin has I

OUT

= -2 uA for VOH of 2.4V when both active high and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This

parameter is characterized but not tested.

5. V

CAP

(Storage capacitor) nominal value is 68 uF.

Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Maximum Accumulated Storage Time

At 150°C Ambient Temperature........................ 1000h

At 85°C Ambient Temperature.................. ... 20 Years

Ambient Temperature with

Power Applied ............................................ –55°C to +150°C

Supply Voltage on V

DC Voltage Applied to Outputs

in High-Z State.......................................–0.5V to V

Input Voltage..........................................–0.5V to V

Relative to GND ........–0.5V to +4.1V

CC

CC

CC

+ 0.5V

+ 0.5V

Transient Voltage (<20 ns) on

Any Pin to Ground Potential .................. –2.0V to V

+ 2.0V

CC

Package Power Dissipation
Capability (T

= 25°C) ................................................... 1.0W

A

Surface Mount Lead Soldering

Temperature (3 Seconds) .......................................... +260°C

DC Output Current (1 output at a time, 1s duration).....15 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Table 9. Operating Range

Range Ambient Temperature V

CC

Commercial 0°C to +70°C 2.7V to 3.6V

Industrial –40°C to +85°C 2.7V to 3.6V

DC Electrical Characteristics

Over the Operating Range (VCC = 2.7V to 3.6V)

Parameter Description Test Conditions Min Max Unit

I

CC1

I

CC2

I

CC4

I

SB

I

IX

I

OZ

V
V
V
V

V

[4]

IH

IL

OH

OL

CAP

Average Vcc Current At f
Average VCC Current

during STORE
Average V

during AutoStore

CAP

Current

Cycle
VCC Standby Current 5mA
Input Leakage Current

(except HSB

)

Input Leakage Current
(for HSB

)

Off State Output
Leakage Current

Input HIGH Voltage 2.0 VCC + 0.5 V
Input LOW Voltage VSS – 0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I

[5]

Storage Capacitor Between V

= 40 MHz 10 mA

SCK

All Inputs Don’t Care, VCC = Max.
Average current for duration t

All Inputs Don’t Care, V
Average current for duration t

= Max, VSS < V

V

CC

= Max, VSS < V

V

CC

VCC = Max, VSS < V

= –2 mA 2.4 V

OUT

= 4 mA 0.4 V

OUT

CAP

IN

IN

OUT

pin and VSS, 5V Rated 61 180 µF

CC

< V

< V

= Max.

CC

CC

< V

CC

STORE

STORE

–1 +1 µA

–100 +1 µA

–1 +1 µA

10 mA

5mA

Document #: 001-50091 Rev. *A Page 13 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

Data Retention and Endurance

3.0V

OUTPUT

5 pF

R1

R2

789Ω

3.0V

OUTPUT

30 pF

R1

R2

789Ω

577Ω

577Ω

Note

6. These parameters are guaranteed by design and are not tested.

Parameter Description Min Unit

DATA

NV

C

R

Data Retention 20 Years

Nonvolatile STORE Operations 200 K

Capacitance

Parameter

C

IN

C

OUT

[6]

Input Capacitance TA = 25°C, f = 1MHz,

Output Pin Capacitance 8 pF

Description Test Conditions Max Unit

6pF

V

= 3.0V

CC

Thermal Resistance

Parameter

Θ

JA

Θ

JC

[6]

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Description Test Conditions 8-SOIC 8-DFN Unit

Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.

Figure 20. AC Test Loads and Waveforms

TBD TBD °C/W

TBD TBD °C/W

AC Test Conditions

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%) ....................... <3 ns

Input and Output Timing Reference Levels.....................1.5V

Document #: 001-50091 Rev. *A Page 14 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

AC Switching Characteristics

HI-Z

VALID IN

HI-Z

CS

SCK

SI

SO

t

CL

t

CH

t

CSS

t

SD

t

HD

t

CO

t

OH

t

CS

t

CSH

t

HZCS

CS

SCK

HOLD

SO

t

SH

t

HHZ

t

HLZ

t

HH

t

SH

t

HH

~

~

~

Cypress

Parameter

f

SCK

t

CL

t

CH

t

CS

t

CSS

t

CSH

t

SD

t

HD

t

HH

t

SH

t

CO

t

HHZ

t

HLZ

t

OH

t

HZCS

f

SCK

t

WL

t

WH

t

CE

t

CES

t

CEH

t

SU

t

H

t

HD

t

CD

t

V

t

HZ

t

LZ

t

HO

t

DIS

Alt.

Parameter

Figure 21. Synchronous Data Timing (Mode 0)

Description

40MHz

Min Max

Unit

Clock Frequency, SCK 40 MHz

Clock Pulse Width Low 11 ns

Clock Pulse Width High 11 ns

CS High Time 20 ns

CS Setup Time 10 ns

CS Hold Time 10 ns

Data In Setup Time 5 ns

Data In Hold Time 5 ns

HOLD Hold Time 5 ns

HOLD Setup Time 5 ns

Output Valid 9 ns

HOLD to Output High Z 15 ns

HOLD to Output Low Z 15 ns

Output Hold Time 0 ns

Output Disable Time 25 ns

Figure 22. HOLD

Timing

~

Document #: 001-50091 Rev. *A Page 15 of 22

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CY14B101Q1
CY14B101Q2
CY14B101Q3

AutoStore or Power Up RECALL

t

STORE

t

STORE

t

HHHD

t

HHHD

t

DELAY

t

DELAY

V

VCCRISE

Note

8

Note

8

Note

11

t

LZHSB

t

LZHSB

t

FA

t

FA

V

SWITCH

V

HDIS

HSB OUT

Autostore

POWER-UP
RECALL

Read and Write
Inhibited (RWI)

POWER-UP
RECALL

POWER-UP
RECALL

Read and Write Read and Write

BROWN
OUT
AUTOSTORE

POWER
DOWN
AUTOSTORE

7. t

FA

starts from the time VCC rises above V

SWITCH.

8. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not initiated

9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t

DELAY

.

10. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V

SWITCH.

11. HS B pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Parameters Description

[7]

t

FA

t

STORE

t

DELAY

V

SWITCH

t

VCCRISE

V

HDIS

t

LZHSB

t

HHHD

[8]

[9]

[6]

Power Up RECALL Duration 20 ms

STORE Cycle Duration 8ms

Time Allowed to Complete SRAM Cycle 25 ns

Low Voltage Trigger Level 2.65 V
VCC Rise Time 150 μs
HSB Output Driver Disable Voltage 1.9 V

HSB To Output Active Time 5 μs
HSB High Active Time 500 ns

Switching Waveforms

Figure 23. AutoStore or Power Up RECALL

[10]

CY‘4B101QxA

Min Max

Unit

Document #: 001-50091 Rev. *A Page 16 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Software Controlled STORE and RECALL Cycles

0 1 1 0 0 0 0 0

CS

SCK

SI

0 1 2 3 4 5 6 7

RWI

Hi-Z

RDY

t

RECALL

12. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

13. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Parameter Description

t

RECALL

[12, 13]

t

SS

RECALL Duration 200 μs

Soft Sequence Processing Time 100 μs

Switching Waveforms

Figure 24. Software STORE Cycle

CS

SCK

SI

RWI

RDY

0 0 1 1 1 1 0 0

Figure 25. Software RECALL Cycle

0 1 2 3 4 5 6 7

Hi-Z

[12]

t

STORE

[12]

CY14B101Q1

Unit

Min Max

Document #: 001-50091 Rev. *A Page 17 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Hardware STORE Cycle

~

~

HSB (IN)

HSB (OUT)

SO

RWI

HSB (IN)

HSB (OUT)

RWI

t

HHHD

t

STORE

t

PHSB

t

DELAY

t

LZHSB

t

DELAY

t

DHSB

t

DHSB

t

PHSB

HSB pin is driven high to VCC only by Internal
100K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.

Write Latch not set

Write Latch set

~

~

~

Parameter Description

t

DHSB

t

PHSB

HSB To Output Active Time when write latch not set 25 ns

Hardware STORE Pulse Width 15 ns

Switching Waveforms

Figure 26. Hardware STORE Cycle

CY14B101Q1

Unit

Min Max

[8]

~

~

Document #: 001-50091 Rev. *A Page 18 of 22

~

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Ordering Information

Option:
T - Tape & Reel
Blank - Std.

Q - Serial SPI nvSRAM

Density:

101 - 1 Mb

Voltage:
B - 3.0V

Cypress

CY 14 B 101 Q 1-SF X C T

nvSRAM

14 - Auto Store + Software STORE + Hardware STORE

Pb-Free

Package:
SF - 16 SOIC
LH - 8 DFN

1 - 8 DFN (with WP)
2 - 8 DFN (With V

CAP

)

3 - 16 SOIC

Temperature:
C - Commercial (0 to 70

°

C)

I - Industrial (-40 to 85

°

C)

Ordering Code

CY14B101Q1-LHXIT 001-50671 8 DFN (with WP

CY14B101Q1-LHXI 001-50671 8 DFN (with WP)

CY14B101Q1-LHXCT 001-50671 8 DFN (with WP) Commercial

CY14B101Q1-LHXC 001-50671 8 DFN (with WP)

CY14B101Q2-LHXIT 001-50671 8 DFN (with V

CY14B101Q2-LHXI 001-50671 8 DFN (with V

CY14B101Q2-LHXCT 001-50671 8 DFN (with V

CY14B101Q2-LHXC 001-50671 8 DFN (with V

CY14B101Q3-SFXIT 51-85022 16 SOIC Industrial

CY14B101Q3-SFXI 51-85022 16 SOIC

CY14B101Q3-SFXCT 51-85022 16 SOIC Commercial

CY14B101Q3-SFXC 51-85022 16 SOIC

All the above parts are Pb - free. The above table contains advance information. Contact your local Cypress sales representative for availability of these parts.

Package
Diagram

Package Type

) Industrial

) Industrial

CAP

)

CAP

) Commercial

CAP

)

CAP

Operating

Range

Part Numbering Nomenclature

Document #: 001-50091 Rev. *A Page 19 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Package Diagrams

1. ALL DIMENSIONS ARE IN MILLIMETERS

3. BASED ON REF JEDEC # MO-

240 EXCEPT DIMENSIONS (L) and (b)

NOTES:

2. PACKAGE WEIGHT: TBD

001-50671 *A

Figure 27. 8-Pin (300 mil) DFN Package (001-50671)

Document #: 001-50091 Rev. *A Page 20 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Package Diagrams (continued)

51-85022 *B

Figure 28. 16-Pin (300 mil) SOIC (51-85022)

Document #: 001-50091 Rev. *A Page 21 of 22

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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Document History Page

Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3 1 MBit (128K x 8) Serial SPI nvSRAM
Document Number: 001-50091

REV. ECN NO.

Orig. of
Change

** 2607408 GSIN/

GVCH/AESA

*A 2654487 GVCH/PYRS 02/04/2009 Moved from Advance information to Preliminary

Submission

Date

12/19/08 Updated the “Feature” section

Updated nvSRAM STORE, RECALL, AutoStore Enable/Disable sections
Removed Soft Sequence
Added SPI instructions for STORE, RECALL, AutoStore Enable and Disable
Updated SPI with following changes:

-- Added more information for protocol

-- Added four new SPI instruction

-- WEN bit cleared on CS going high edge after Write instructions and four
nvSRAM special instructions
Added RDY

bit to Status Register for indicating Store/Recall in progress
Other changes as per new EROS
Removed 8 SOIC package
Added two new 8DFN packages
Changed tCO parameter to 9 ns

Changed part number from CY14B101QxA to CY14B101Qx
Updated pin description of V
Updated Device operation and SPI peripheral interface description
Added Factory setting values for BP1, BP2 and WPEN bits
Updated Real Time Clock operation description
Changed I

from 5mA to 10mA

CC2

Description of Change

pin

CAP

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.

Products

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Wireless wireless.cypress.com

Memories memory.cypress.com

Image Sensors image.cypress.com

© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

PSoC Solutions

General psoc.cypress.com/solutions

Low Power/Low Voltage psoc.cypress.com/low-power

Precision Analog psoc.cypress.com/precision-analog

LCD Drive psoc.cypress.com/lcd-drive

CAN 2.0b psoc.cypress.com/can

USB psoc.cypress.com/usb

Document #: 001-50091 Rev. *A Revised February 2, 2009 Page 22 of 22

AutoStore and QuantumTrap are trademarks of Cypress Semiconductor Corp. All products an d company names mentioned in this document are the trademarks of their respective holders.

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