Cypress CY14B101P User Manual

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PRELIMINARY

CY14B101P

1 Mbit (128K x 8) Serial SPI nvSRAM

with Real Time Clock

Features

Instruction

Address Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction decode

Write protect Control logic

Quantum Trap

STORE

RECALL

SCK

CAP

HSB

128K X 8

SRAM ARRAY

128K X 8

RTC

Xout Xin INT

MUX

A0-A16

D0-D7

HOLD

Logic Block Diagram

■

1 Mbit NonV olatile SRAM

❐

Internally organized as 128K x 8

❐

STORE to QuantumTrap® nonvolatile elements initiated automatically on power down (AutoStore®) or by user using HSB pin (Hardware Store) or SPI instruction (Software S tore)

❐

RECALL to SRAM initiated on power up (Power Up Recall®) or by SPI Instruction (Software Recall)

❐

Automatic STORE on power down with a small capacitor

■

High Reliability

❐

Infinite Read, Write, and RECALL cycles

❐

200,000 STORE cycles to QuantumTrap

❐

Data Retention: 20 Years

■

Real Time Clock

❐

Full featured Real Time Clock

❐

Watchdog timer

❐

Clock alarm with programmable interrupts

❐

Capacitor or battery backup for RTC

❐

Backup current of 300 nA

■

High Speed Serial Peripheral Interface (SPI)

❐

40 MHz Clock rate - RTC Read at 25 MHz

❐

Supports SPI Modes 0 (0,0) and 3 (1,1)

■

Write Protection

❐

Hardware Protection using Write Protect (WP) Pin

❐

Software Protection using Write Disable Instruction

❐

Software Block Protection for 1/4, 1/2, or entire Array

■

Low Power Consumption

❐

Single 3V +20%, –10% operation

❐

Average Vcc current of 10 mA at 40 MHz operation

■

Industry Standard Configurations

❐

Commercial and industrial temperatures

❐

16-pin SOIC Package

❐

RoHS compliant

Overview

The Cypress CY14B101P combines a 1 Mbit nonvolatile static RAM with full featured real time clock in a monolithic integrated circuit with serial SPI interface. The memory is organized as 128K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600 Document #: 001-44109 Rev. *B Revised February 2, 2009

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CY14B101P

Pinouts

INT

GND

CAP

SCK

HSB

HOLD

To p V ie w

not to scale

RTCbat

out

RTCcap

Figure 1. Pin Diagram - 16-Pin SOIC

Table 1. Pin Definitions

Pin Name I/O Type Description

SCK Input Serial Clock. Runs at speeds up to a maximum of 25 MHz. All inputs are latched at the rising edge

SI Input Serial Input. Pin for input of all SPI instructions and data.

SO Output Serial Output. Pin for output of data through SPI.

HOLD

HSB

CAP

RTCcap

RTCbat

Xout Output Crystal Output connection. Drives crystal on start up.

Xin Input Crystal Input connection. For 32.768 kHz crystal.

INT

NC No Connect No Connect. This pin is not connected to the die.

GND Power Supply Ground

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Input Chip Select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low

power standby mode.

of this clock. Outputs are driven at the falling edge of the clock.

Input Write Protect. Implements hardware write protection in SPI. Input HOLD Pin. Suspends Serial Operation.

Input/Output Hardware Store Busy: A weak internal pull up keeps this pin pulled HIGH. If not used, this pin is

left as No Connect. Output: Indicates busy status of nvSRAM when LOW. Input: Hardware Store implemented by pulling this pin LOW externally.

Power Supply AutoStore Capacitor . Supplies power to the nvSRAM during power loss to STORE data from the

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It

must never be connected to GND. Power Supply Capacitor Backup for RTC. Left unconnected if V Power Supply Battery Backup for RTC. Left unconnected if V

RTCcap

RTCbat

is used.

Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power

monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).

Power Supply Power Supply (2.7-3.6V)

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CY14B101P

Device Operation

CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC and SPI interface. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence that transfers the data in parallel to the nonvolatile Quantum Trap cells. A small capacitor (V is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power down data security. The Quantum Trap nonvolatile elements built in the reliable SONOS technology make nvSRAM the ideal choice for secure data storage.

In CY14B101P, the 1-Mbit memory array is organized as 128K words x 8 bits. The memory is accessed through a standard SPI interface that enables very high clock speeds upto 40 MHz with zero delay read and write cycles. CY14B101P supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 & 1, 1) and operates as SPI slave. The device is enabled using the Chip Select pin (CS

) and accessed through Serial Input (SI), Serial

Output (SO), and Serial Clock (SCK) pins. CY14B101P provides the feature for hardware and software

write protection through WP

pin and WRDI instruction. CY14B101P also provides mechanisms for block write protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the status register. Further, the HOLD

pin is used to suspend any

serial communication without resetting the serial sequence. CY14B101P uses the standard SPI opcodes for memory access.

In addition to the general SPI instructions for read and write, CY14B101P provides four special instructions that allow access to four nvSRAM specific functions: STORE, RECALL, AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).

The major benefit of nvSRAM SPI over serial EEPROMs is that all reads and writes to nvSRAM are performed at th e speed of SPI bus with zero cycle delay. Therefore, no wait time is required after any of the memory accesses. The STORE and RECALL operations need finite time to complete and all memory accesses are inhibited during this time. While a STORE or RECALL operation is in progress, the busy status of the device is indicated by the Hardware Store Busy (HSB RDY

bit of the Status Register.

) pin and also reflected on the

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not use up any endurance cycles of the nonvolatile memory. This enables user to perform infinite write operations. A write cycle is performed through the SPI WRITE instruction. The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode, 3 bytes of address and 1 byte of data. Writes to nvSRAM is done at SPI bus speed with zero cycle delay.

CY14B101P allows burst mode writes to be performed through SPI. This enables write operations on consecutive addresses without issuing a new WRITE instruction. When the last address in memory is reached in burst mode, the address rolls over to 0x0000 and the device continues to write.

The SPI write cycle sequence is defined in the Memory Access section of SPI Protocol Description.

CAP

SRAM Read

A read cycle in CY14B101P is performed at the SPI bus speed and the data is read out with zero cycle delay after the READ instruction is performed. The READ instruction is issued through the SI pin of the nvSRAM and consists of the READ opcode and 3 bytes of address. The data is read out on the SO pin.

CY14B101P allows burst mode reads to be performed through

)

SPI. This enables reads on consecutive addresses without issuing a new READ instruction. When the last address in memory is reached in burst mode read, the address rolls over to 0x0000 and the device continues to read.

The SPI read cycle sequence is defined in the Memory Access section of SPI Protocol Description

STORE Operation

STORE operation transfers the data from the SRAM to the nonvolatile Quantum Trap cells. The CY14B101P STOREs data to the nonvolatile cells using one of the three STORE operations: AutoStore, activated on device power down; Software Store, activated by a STORE instruction in the SPI; and Hardware Store, activated by the HSB

. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.

The HSB

signal or the RDY bit in the Status register can be monitored by the system to detect if a STORE cycle is in progress. The busy status of nvSRAM is indicated by HSB being pulled LOW or RDY

bit being set to ‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore and Hardware Store operations are ignored unless at least one write opera tion has taken place since the most recent STORE or RECALL cycle. However, software initiated STORE cycles are performed regardless of whether a write operation has taken place.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap during power down. This STORE mechanism is implemented using a capacitor (V data in the nonvolatile memory when power goes down.

During normal operation, the device draws current from V charge the capacitor connected to the V voltage on the V the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the V initiated if no write cycle has been performed since last RECALL.

During power down, the memory accesses are inhibited after the voltage on V writes, ensure that CS Therefore, during power down the device must be deselected and CS

must be allowed to follow VCC.

Figure 2 shows the proper connection of the storage capacitor

) for AutoStore operation. Refer to DC Electrical Charac-

CAP

teristics on page 22 for the size of the V

) and enables the device to safely STORE the

CAP

pin. When the

pin drops below V

capacitor. The AutoStore operation is not

CAP

pin drops below V

is not left floating prior to this event.

SWITCH

CAP

during power down,

SWITCH

. To avoid inadvertent

CAP

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Figure 2. AutoStore Mode

0.1uF

Vcc

10kOhm

CAP

Vcc

CAP

Software Store Operation

Software Store allows the user to trigger a STORE operation through a special SPI instruction. This operation is initiated irrespective of whether a write has been performed since last nv operation.

A STORE cycle takes t the memory accesses to nvSRAM are inhibited. The RDY the Status register or the HSB Ready/Busy status of the nvSRAM. After the t is completed, the SRAM is activated again for read an d write

time to complete, during which all

STORE

pin may be polled to find the

STORE

operations.

Hardware Store and HSB pin Operation

The HSB pin in CY14B101P is used to control and acknowledge STORE operations. If no STORE/RECALL is in progress, this pin can be used to request a Hardware Store cycle. When the HSB pin is driven LOW, the CY14B101P conditionally initiates a STORE operation after t starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for t

STORE

The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, when a STORE cycle (initiated by any means) or Power up Recall is in progress. Upon completion of the STORE operation, CY14B101P remains disabled until the HSB pin returns HIGH. HSB pin must be left unconnected if not used.

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile Quantum Trap elements to the SRAM. In CY14B101P, a RECALL may be initiated in two ways: Hardware Recall, initiated on power up; and Software Recall, initiated by a SPI RECALL instruction.

Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. All memory accesses are inhibited while a RECALL

duration. An actual STORE cycle

DELAY

duration or as long as HSB pin is LOW.

bit of

cycle time

cycle is in progress. The RECALL operation in no way alters the data in the nonvolatile elements.

Hardware Recall (Power Up)

During power up, when VCC crosses V RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM.

A Power Up Recall cycle takes t memory access is disabled during this time. HSB

time to complete and the

detect the Ready status of the device.

SWITCH

, an automatic

pin is used to

Software Recall

Software Recall allows the user to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM. In CY14B101P, this can be done by issuing a RECALL instruction in SPI.

A Software Recall takes t memory accesses to nvSRAM are inhibited. The controller must

to complete during which all

RECALL

provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions.

Disabling and Enabling AutoStore

If the application does not require the AutoStore feature, it can be disabled in CY14B101P by using the ASDISB instruction. If this is done, the nvSRAM does not perform a STORE operation at power down.

AutoStore can be re-enabled by using the ASENB instruction. However, these operations are not nonvolatile and if the user needs this setting to survive power cycle, a STORE operation must be performed following Autostore Disable or Enable operation.

Note CY14B101P comes from the factory with AutoStore Enabled.

Note If AutoStore is disabled and V recommended that the V never be connected to GND. Power Up Recall operation cannot

pin is left open. V

CAP

is not required, it is

CAP

pin must

CAP

be disabled in any case.

Serial Peripheral Interface

SPI Overview

The SPI is a four-pin interfa ce with Chip Select ( CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. CY14B101P provides serial access to nvSRAM through SPI interface. The SPI bus on CY14B101P can run at speeds up to 40 MHz for all instructions except RDRTC which runs at 25 MHz.

The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on SPI bus is activated using the Chip Select pin.

The relationship between chip select, clock, and data is dictated by the SPI mode. CY14B101P supports SPI modes 0 and 3. In both these modes, data is clocked into the nvSRAM on the rising edge of SCK starting from the first rising edge after CS active.

The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS

is activated the first byte transferred from the bus

goes

Document #: 001-44109 Rev. *B Page 4 of 32

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CY14B101P

master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued.

The commonly used terms used in SPI protocol are given below:

SPI Master

The SPI Master device controls the operations on a SPI bus. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and master may select any of the slave devices using the Chip Select pin. All the operations must be initiated by the master activating a slave device by pulling the CS also generates the Serial Clock (SCK) and all the data transmission on SI and SO lines are synchronized with this clock.

SPI Slave

SPI slave device is activated by the master through the Chip Select line. A slave device gets the Serial Clock (SCK) as an input from the SPI master and all the communication is synchronized with this clock. SPI slave never initiates a communication on the SPI bus and acts on the instruction from the master.

CY14B101P operates as a slave device and may share the SPI bus with multiple CY14B101P devices or other SPI devices.

Chip Select (CS

For selecting any slave device, the master needs to pull down the corresponding CS slave device only while the CS

The CY14B101P is selected when the CS device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high impedance state.

Note A new instruction must begin with the falling edge of Chip Select (CS active Chip Select cycle.

)

). Therefore, only one opcode can be issued for each

pin of the slave LOW. The master

pin. Any instruction can be issued to a

pin is LOW.

pin is LOW. When the

Data Transmission SI/SO

SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as MOSI (Master Out Slave In) and SO is referred to as MISO (Master In Slave O ut). The master issues instructions to the slave through the SI pin, while slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier.

CY14B101P has two separate pins for SI and SO which can be connected with the master as shown in Figure 3 on page 6.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission.

CY14B101P requires a 3-byte address for any read or write operation. However, since the actual address is only 17 bits, it implies that the first seven bits, which are fed in, are ignored by the device. Although these seven bits are ‘don’t care’, Cypress recommends that these bits are treated as 0s to enable seamless transition to higher memory densities.

Serial Opcode

After the slave device is selected with CS byte received is treated as the opcode for the intended operation.

CY14B101P uses the standard opcodes for memory accesses. In addition to the memory accesses, CY14B101P provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to

Table 2 on page 7 for details on opcodes.

Invalid Opcode

If an invalid op-code is received, the op-code is ignored and the device ignores any additional serial data on the SI pin. and no valid data is sent out on the SO pin. Opcode for a new instruction is recognized only after the next falling edge of CS

going LOW, the first

Serial Clock (SCK)

Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS

CY14B101P allows SPI modes 0 and 3 for data communication. In both these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK.

Document #: 001-44109 Rev. *B Page 5 of 32

goes LOW.

Status Register

CY14B101P has an 8-bit status register. The bits in the status register are used to configure the SPI bus. These bits are described in the Table 4 on page 8.

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CY14B101P

Figure 3. System Configuration Using SPI nvSRAM

P101B41YCP101B41YC

uController

SCK

MOSI

MISO

SI SO OSISKCSSCK

HOLD HOLDCS

CS1

CS2

HOLD1

HOLD2

LSB

MSB

765432

SCK

0 1 2 3 4 5 6 7

SCK

765432

LSB

MSB

0 12 34 56 7

SPI Modes

CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

■

SPI Mode 0 (CPOL=0, CPHA=0)

■

SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched in on the rising edge of Serial Clock (SCK) starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles are considered. The output data is available on the falling edge of Serial Clock (SCK).

Figure 4. SPI Mode 0

The two SPI modes are shown in Figure 4 and Figure 5. The status of clock when the bus master is in Standby mode and not transferring data is:

■

SCK remains at 0 for Mode 0

■

SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for the either Mode 0 or Mode 3. CY14B101P detects the SPI mode from the status of SCK pin when device is selected by bringing

pin LOW. If SCK pin is LOW when device is selected, SPI

the CS Mode 0 is assumed and if SCK pin is HIGH, CY14B101P works in SPI Mode 3.

Figure 5. SPI Mode 3

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SPI Operating Features

Power Up

Power up is defined as the condition when the power supply is turned on and V Chip Select (CS Therefore, CS up resistor. As a built in safety feature, Chip Select (CS edge sensitive and level sensitive. After power up, the device is not selected until a falling edge is detected on Chip Select (CS). This ensures that Chip Select (CS before going Low to start the first operation.

As described earlier, nvSRAM performs a Power Up Recall operation after power up and therefore, all memory accesses are disabled for t be probed to check the ready/busy status of nvSRAM after power up.

Power On Reset

A Power On Reset (POR) circuit is included to prevent inadvertent writes. At power up, the device does not respond to any instruction until the VCC reaches the Power On Reset threshold voltage (V threshold, the device is internally reset and performs a Power Up Recall operation. The device is in the following state after POR:

■

Deselected (after Power up, a falling edge is required on Chip Select (CS

■

Standby Power mode

■

Not in the Hold Condition

■

Status register state:

❐

Write Enable (WEN) bit is reset to 0.

❐

WPEN, BP1, BP0 unchanged from previous power down

The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous power down.

Before selecting and issuing instructions to the memory, a valid and stable V remain valid until the end of the transmission of the instruction.

Power Down

At power down (continuous decay of VCC), when VCC drops from the normal operating voltage and below the V voltage, the device stops responding to any instruction sent to it. If a write cycle is in progress during power down, it is allowed t

time to complete after Vcc transitions below V

DELAY

After this, all memory accesses are inhibited and a co nditional AutoStore operation is performed (AutoStore is not performed if no writes have happened since last RECALL cycle). This feature prevents inadvertent writes to nvSRAM from happening during power down.

However, to avoid the possibility of inadvertent writes during power down, ensure that the device is deselected and is in Standby Power Mode, and the Chip Select (CS voltage applied on V

crosses Vswitch voltage. During this time, the

) must be enabled to follow the VCC voltage.

must be connected to VCC through a suitable pull

) is both

) must have been HIGH,

duration after power up. The HSB pin can

RECALL

). After VCC transitions the POR

SWITCH

) before any instructions are started).

voltage must be applied. This voltage must

threshold

SWITCH

) follows the

Active Power and Standby Power Modes

When Chip Select (CS) is LOW, the device is selected, and is in the Active Power mode. The device consumes I specified in DC Electrical Characteristics on page 22. When Chip Select (CS

) is HIGH, the device is deselected and the device

goes into the Standby Power mode if a STORE or RECALL cycle is not in progress. If a STORE/RECALL cycle is in progress, the device goes into the Standby Power Mode after the STORE/RECALL cycle is completed. In the Standby Power mode the current drawn by the device drops to I

SPI Functional Description

The CY14B101P uses an 8-bit instruction register. Instructions and their operation codes are listed in Table 2. All instructions, addresses, and data are transferred with the MSB first and start with a HIGH to LOW CS instructions which provide access to most of the functions in nvSRAM. Further, the WP and HOLD pins provide additional functionality driven through hardware.

Table 2. Instruction Set

Instruction

Status Register

SCK

01234567

000001001

MSB

LSB

HI-Z

01234567

Data

LSB

D0D1

D5D6

MSB

The status register bits are listed in Table 3. The status register consists of Ready bit (RD Y WEN and WPEN. The RDY Ready/Busy status while a nvSRAM STORE cycle is in

) and data protection bits BP1, BP0,

bit can be polled to check the

tion and read by RDSR instruction. However, only WPEN, BP1 and BP0 bits of the Status Register can be modified by using WRSR instruction. WRSR instruction has no effect on WEN and

bits. The default value shipped from the factory for BP1,

RDY BP2 and WPEN bits is ‘0’.

progress. The status register can be modified by WRSR instruc-

Table 3. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN (0) X X X BP1 (0) BP0 (0) WEN RDY

Table 4. Status Register Bit Definition

Bit Definition Description

Bit 0 (RDY

) Ready Read Only bit indicates the ready status of device to perform a memory access. This

bit is set to “1” by the device while a STORE or Software Recall cycle is in progress.

Bit 1 (WEN) Write Enable WEN indicates if the device is write-enabled. Setting WEN = '1' enables writes and

setting WEN = '0' disables all write operations Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details see Table 5 on page 9. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details see Table 5 on page 9.

Bit 7(WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP

). For details see Table 6 on

page 10.

Read Status Register (RDSR) Instruction

The Read Status Register instruction provides access to the status register. This instruction is used to probe the Write Enable Status of the device or the Ready status of the device. RDY

bit is set by the device to 1 whenever a STORE cycle is in progress. The Block Protection and WPEN bits indicate the extent of protection employed.

This instruction is issued after the falling edge of CS

using the

opcode for RDSR.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status register. However, this instruction cannot be used to modify bit 0 and bit 1 (WEN and RDY). The BP0 and BP1 bits can be used

Figure 6. Read Status Register (RDSR) Instruction Timing

to select one of four levels of block protection. Further, WPEN bit must be set to ‘1’ to enable the use of Write Protect (WP

) pin.

WRSR instruction is a write instruction and needs writes to be enabled (WEN bit set to ‘1’) using the WREN instruction before it is issued. The instruction is issued after the falling edge of CS using the opcode for WRSR followed by eight bits of data to be stored in the Status Register. Since, only bits 2, 3, and 7 can be modified by WRSR instruction, it is recommended to leave the other bits as ‘0’ while writing to the Status Register.

Note In CY14B101P, the values written to Status Register are saved to nonvolatile memory only after a STORE operation. If AutoStore is disabled, any modifications to the Status Register must be secured by using a Software STORE operation

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Figure 7. Write Status Register (WRSR) Instruction Timing

SCK

01234567

0000000

MSB

LSB

00D7

HI-Z

01234567

Opcode

Data in

0 0 0 0 0 1 1 0

SCK

Hi-Z

0 1 2 3 4 5 6 7

0 00 00 1 00

SCK

Hi-Z

0 1 2 3 4 5 6 7

Write Protection and Block Protection

CY14B101P provides features for both software and hardware write protection using WRDI instruction and WP device also provides block protection mechanism through BP0 and BP1 pins of the Status Register.

The write enable and disable status of the device is indicated by WEN bit of the status register. The write instructions (WRSR, WRITE, and WRTC) and nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) need the write to be enabled (WEN bit = 1) before they can be issued.

Write Enable (WREN) Instruction

On power up, the device is always in the write disable state. The following WRITE, WRSR, WRTC, or nvSRAM special instruction must therefore be preceded by a Write Enable instruction. If the device is not write enabled (WEN = ‘0’), it ignores the write instructions and returns to the standby state when CS HIGH. A new CS communication. The instruction is issued following the falling edge of CS. When this instruction is used, the WEN bit of status register is set to ‘1’.

Note After completion of a write instruction (WRSR, WRITE, or WRTC) or nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to provide protection from any inadvertent writes. Therefore, WREN instruction needs to be used before a new write instruction can be issued.

falling edge is required to re-initiate serial

Figure 8. WREN Instruction

. Additionally, this

is brought

by opcode for WRDI instruction. The WEN bit is cleared on the rising edge of CS

following a WRDI instruction.

Figure 9. WRDI Instruction

Block Protection

Block protection is provided using the BP0 and BP1 pins of the Status register. These bits can be set using WRSR instruction and probed using the RDSR instruction. The nvSRAM is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any data within the protected segment is read only. Table 5 shows the function of Block Protect bits.

Table 5. Block Write Protect Bits

Level

1 (1/4) 0 1 0x18000-0x1FFFF 2 (1/2) 1 0 0x10000-0x1FFFF

3 (All) 1 1 0x00000-0x1FFFF

Status Register Bits

BP1 BP0

Array Addresses Protected

0 0 0 None

Hardware Write Protection (WP Pin)

The write protect pin (WP) is used to provide hardware write protection. WP when held HIGH. When the WP bit is “1”, all write operations to the status register are inhibited. The hardware write protection function is blocked when the

Write Disable (WRDI) Instruction

Write Disable instruction disables the write by clearing the WEN bit to ‘0’ in order to protect the device against inadvertent writes. This instruction is issued following the falling edge of CS

Document #: 001-44109 Rev. *B Page 9 of 32

followed

WPEN bit is “0”. This allows the user to install the CY14B101P in a system with the WP status register.

pin can be used along with WPEN and Block Protect bits

(BP1 and BP0) of the status register to inhibit writes to memory.

pin allows all normal read and write operations

pin is brought LOW and WPEN

pin tied to ground, and still write to the

[+] Feedback

PRELIMINARY

CY14B101P

When WP

SCK

01234567

765432

2021222301234567

MSB LSB

Data

Op-Code

0000001

0000

0 0

A16

A1A2

17-bit Address

MSB LSB

pin is LOW and WPEN is set to “1”, any modifications to status register are disabled. Therefore, the memory is protected by setting the BP0 and BP1 bits and the WP pin inhibits any modification of the status register bits, providing hardware write protection.

Note WP going LOW when CS is still LOW has no effect on any of the ongoing write operations to the status register.

Table 6 summarizes all the protection features provided in the

CY14B101P.

Table 6. Write Protection Operation

WPEN WP WEN

Protected

Blocks

Unprotected

Blocks

Status

X X 0 Protected Protected Protected

0 X 1 Protected Writable Writable 1 LOW 1 Protected Writable Protected 1 HIGH 1 Protected Writable Writable

Memory Access

All memory accesses are done using the READ and WRITE instructions. These instructions cannot be used while a STORE or RECALL cycle is in progress. A STORE cycle in progress is indicated by the RDY

Read Sequence (READ)

The read operations on CY14B101P are performed by giving the instruction on Serial Input pin (SI) and reading the output on Serial Output (SO) pin. The following sequence needs to be followed for a read operation: After the CS select a device, the read opcode is transmitted through the SI line followed by three bytes of address. The Most Significant address byte contains A16 in bit 0 and other bits as don’t cares. Address bits A15 to A0 are sent in the following two address bytes. After the last address bit is transmitted on the SI pin, the

bit of the status register and the HSB pin.

line is pulled LOW to

Figure 10. Read Instruction Timing

data (D7-D0) at the specific address is shifted out on the SO line on the falling edge of SCK. Any other data on SI line after the last address bit is ignored.

CY14B101P allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction. If only one byte is to be read, the CS

line must be driven HIGH after one byte of data comes out. However, the read sequence may be continued by holding the CS line LOW and the address is automatically incremented and data continues to shift out on SO pin. When the last data memory address (0x1FFFF) is reached, the address rolls over to 0x0000 and the device continues to read.

Write Sequence (WRITE)

The write operations on CY14B101P are performed through the Serial Input (SI) pin. T o perform a write operation CY14B101P, if the device is write disabled, then the device must first b e write enabled through the WREN instruction. When the writes are enabled (WEN = ‘1’), WRITE instruction is issued after the falling edge of CS WRITE opcode on SI line followed by 3-bytes address sequence and the data (D7-D0) which is to be written. The Most Significant address byte contains A16 in bit 0 with other bits being don’t cares. Address bits A15 to A0 are sent in the following two address bytes.

CY14B101P allows writes to be performed in bursts through SPI which can be used to write consecutive addresses without issuing a new WRITE instruction. If only one byte is to be written, the CS transmitted. However, if more bytes are to be written, CS must be held LOW and address incremented automatically. The following bytes on the SI line are treated as data bytes and written in the successive addresses. When the last data memory address (0x1FFFF) is reached, the address rolls over to 0x0000 and the device continues to write.

The WEN bit is reset to “0” on completion of a WRITE sequence.

. A WRITE instruction constitutes transmitting the

line must be driven HIGH after the D0 (LSB of data) is

line

Document #: 001-44109 Rev. *B Page 10 of 32

[+] Feedback

PRELIMINARY

CY14B101P

Figure 11. Burst Mode Read Instruction Timing

SCK

LSB

Op-Code

17-bit Address

MSB

LSB

01 2 3 456 7

765432

20 21 22 23

01234567 01234567

0000 00

11 0 0 00 00 0

A16

A3 A2 A1 A0

D2D3

Data Byte 1

Data Byte N

MSB

LSB

MSB

D2D3

D0D7

SCK

01234 5 6 7

765432

2021222301234567

MSB LSB

Data

D0D1

D5D6D7

Op-Code

00 00001

000 0

A16 A3

A1A2

17-bit Address

MSB LSB

HI-Z

SCK

MSB

LSB

Op-Code

17-bit Address

MSB

LSB

~~~

01 234567

76 5 432

20 21

22 23

01 234567 01234567

0 00000

100000000

A16

A3 A2 A1 A0

HI-Z

Data Byte 1

Data Byte N

D2D3

D0D7

Figure 12. Write Instruction Timing

Figure 13. Burst Mode Write Instruction Timing

READ RTC (RDRTC) Instruction

Read RTC (RDRTC) instruction allows the user to read the contents of RTC registers. Reading the RTC registers through the serial output (SO) pin requires the following sequence: After the CS is transmitted through the SI line followed by ei ght address bits for selecting the register. Any data on the SI line after the address bits is ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. RDRTC also allows burst mode read operation. When reading multiple bytes from RTC registers, the address rolls over to 0x00 after the last RTC register address (0x0F) is reached.

Document #: 001-44109 Rev. *B Page 11 of 32

line is pulled LOW to select a device, the RDRTC opcode

The R bit in RTC Flag register must be set to '1' before reading RTC time keeping registers to avoid reading transitional data. Modifying the RTC Flag registers requires a Write RTC cycle. The R bit must be cleared to '0' after completion of the read operation.

The easiest way to read RTC registers is to perform RDRTC in burst mode. The read may start from the first RTC register (0x00) and the CS registers to be transmitted through the SO pin.

Note Read RTC instruction operates at a maximum clock frequency of 25 MHz.

must be held LOW to allow the data from all 16 RTC

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PRELIMINARY

CY14B101P

Figure 14. Read RTC (RDRTC) Instruction Timing

SCK

012345 67

45 67012345 67

MSB LSB

Data

Op-Code

000 1

001

0000

A1A2

MSB

LSB

D2D3

SCK

012345 67

45 67012345 67

Op-Code

000 1

00 1

0000

A1A2

4-bit Address

MSB

LSB

MSB LSB

Data

HI-Z

0 0 1 1 1 1 0 0

SCK

Hi-Z

0 1 2 3 4 5 6 7

WRITE RTC (WRTC) Instruction

WRITE RTC (WRTC) instruction allows the user to modify the contents of RTC registers. The WRTC instruction requires the WEN bit to be set to '1' before it can be issued. If WEN bit is '0', a WREN instruction needs to be issued before using WRTC. Writing RTC registers requires the following sequence: After the CS

line is pulled LOW to select a device, WRTC opcode is trans-

mitted through the SI line followed by eight address bits identi-

of data. WRTC allows burst mode write operation. When writing more than one registers in burst mode, the address rolls over to 0x00 after the last RTC address (0x0F) is reached.

Note that writing to RTC timekeeping and control registers require the W bit to be set to '1'. The values in these RTC registers take effect only after the W bit is cleared to '0'. Write Enable bit (WEN) is automatically cleared to ‘0’ after completion of the WRTC instruction.

fying the register which is to be written to and one or more bytes

Figure 15. Write RTC (WRTC) Instruction Timing

irrespective of whether a write has taken place since last STORE

nvSRAM Special Instructions

CY14B101P provides four special instructions that allow access to the nvSRAM specific functions: STORE, RECALL, ASDISB,

or RECALL operation.

Figure 16. Software STORE Operation

and ASENB. Table 7 lists these instructions.

Table 7. nvSRAM Special Instructions

Function Name Opcode Operation

STORE 0011 1100 Software Store

RECALL 0110 0000 Software Recall

ASENB 0101 1001 AutoStore Enable

ASDISB 0001 1001 AutoStore Disable

Software Store (STORE)

When a STORE instruction is executed, CY14B101P performs a Software Store operation. The STORE operation is issued

Document #: 001-44109 Rev. *B Page 12 of 32

T o issue this instruction, the device must be write enabled (WEN bit = ‘1’).The instruction is performed by transmitting the STORE opcode on the SI pin following the falling edge of CS

. The WEN

[+] Feedback

PRELIMINARY

CY14B101P

bit is cleared on the positive edge of CS

0 1 1 0 0 0 0 0

SCK

0 1 2 3 4 5 6 7

Hi-Z

0 0 0 1 1 0 0 1

SCK

Hi-Z

0 1 2 3 4 5 6 7

0 1 0 1 1 0 0 1

SCK

Hi-Z

0 12 34 56 7

SCK

HOLD

instruction.

following the STORE

bit is cleared on the positive edge of CS instruction.

following the ASENB

Software Recall (RECALL)

When a RECALL instruction is executed, CY14B101P performs a Software Recall operation. To issue this instruction, the device must be write enabled (WEN = ‘1’).

The instruction is performed by transmitting the RECALL opcode on the SI pin following the falling edge of CS cleared on the positive edge of CS

. The WEN bit is

following the RECALL

instruction.

Figure 17. Software RECALL Operation

AutoStore Disable (ASDISB)

AutoStore is enabled by default in CY14B101P. The AutoStore Disable instruction disables the AutoStore on CY14B101P. This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive power cycle.

T o issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the ASDISB opcode on the SI pin following the falling edge of CS

bit is cleared on the positive edge of CS instruction.

following the ASDISB

Figure 18. AutoStore Disable Operation

. The WEN

Figure 19. AutoStore Enable Operation

HOLD Pin Operation

The HOLD pin is used to pause the serial communication. When the device is selected and a serial sequence is underway, HOLD is used to pause the serial communication with the master device without resetting the ongoing serial sequence. To pause, the HOLD pin must be brought LOW when the SCK pin is LOW. To resume serial communication, the HOLD HIGH when the SCK pin is LOW (SCK may toggle during HOLD While the device serial communication is paused, inputs to the SI pin are ignored and the SO pin is in the high impedance state.

This pin can be used by the master with the CS serial communication by bringing the pin HOLD deselecting an SPI slave to establish communication with another slave device, without the serial communication being reset. The communication may be resumed at a later point by selecting the device and setting the HOLD pin HIGH.

Figure 20. HOLD Operation

pin must be brought

pin to pause the

LOW and

AutoStore Enable (ASENB)

The AutoStore Enable instruction enables the AutoStore on CY14B101P. This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive power cycle.

T o issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the ASENB opcode on the SI pin following the falling edge of CS

Document #: 001-44109 Rev. *B Page 13 of 32

. The WEN

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PRELIMINARY

CY14B101P

Real Time Clock Operation

nvTIME Operation

The CY14B101P offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. The RTC registers occupy a separate address space from nvSRAM and are accessible through Read RTC (RDRTC) and Write RTC (WRTC) instructions on register addresses 0x00 to 0x0F . Internal double buffering of the clock and the timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format.

Clock Operations

The clock registers maintain time up to 9,999 years in one-second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress.

Backup Power

The RTC in the CY14B101P is intended for permanently powered operation. The V depending on whether a capacitor or battery is chosen for the application. When the primary power, V V

The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost.

During backup operation, the CY14B101P consumes a maximum of 300 nanoamps at room temperature. The user must choose capacitor or battery values according to the application.

Backup time values based on maximum current specifications are shown in the following table. Nominal backup times are approximately two times longer.

Table 8. RTC Backup Time

the device switches to the backup power supply.

SWITCH

Capacitor Value Backup Time

0.1F 72 hours

0.47F 14 days

1.0F 30 days

RTCcap

or V

pin is connected

RTCbat

, fails and drops below

Reading the Clock

The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. The user must stop internal updates to the CY14B101P time keeping registers before reading clock data, to prevent reading of data in transition. Stopping the register updates does not affect clock accuracy.

The updating process is stopped by writing a ‘1’ to the read bit ‘R’ (in the flags register at 0x00), and does not restart until a ‘0’ is written to the read bit. The RTC registers are read while the internal clock continues to run. After a ‘0’ is written to the read bit (‘R’), all RTC registers are simultaneously updated within 20 ms.

Setting the Clock

Setting the write bit ‘W’ (in the flags register at 0x00) to a ‘1’ stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time is then written into the registers and must be in 24-hour BCD format. The time written is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time. Resetting the write bit to ‘0’ transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation.

If the time written to the timekeeping registers is not in the correct BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation.

Note The values entered in the timekeeping, alarm, calibration, and interrupt registers must be saved to nonvolatile memory by a STORE operation. Therefore, while working in AutoStore disabled mode, perform a STORE operation after writing into the RTC registers for the modifications to be correctly recorded.

Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3V lithium is recommended and the CY14B101P sources current only from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B101P. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.

Stopping and Starting the Oscillator

The OSCEN bit in the calibration register at 0x08 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the “enabled” (set to 0) state. To preserve the battery life when the system is in storage, OSCEN must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start.

While system power is off, If the voltage on the backup supply (V the oscillator may fail.The CY14B101P has the ability to detect oscillator failure when system power is restored. This is recorded in the OSCF (Oscillator Failed bit) of the flags register at the address 0x00. When the device is powered on (V V OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set to “1”. The system must check for this condition and then write ‘0’ to clear the fla g. Note that in addition to setting the OSCF flag bit, the time registers are reset to the “Base Time” (see Setting the Clock on page 14), which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not a ffected by the ‘oscillator failed’ condition.

or V

RTCcap

) the OSCEN bit is checked for “enabled” status. If the

SWITCH

) falls below their respective minimum level,

RTCbat

goes above

Document #: 001-44109 Rev. *B Page 14 of 32

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PRELIMINARY

CY14B101P

The value of OSCF must be reset to ‘0’ when the time reg isters are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on.

T o reset OSCF , set the write bit “W” (in the Flags register at 0x00) to a “1” to enable writes to the Flag register. Write a “0” to the OSCF bit and then reset the write bit to “0” to disable writes.

Calibrating the Clock

The RTC is driven by a quartz controlled crystal with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystals available in market typically have an error of + CY14B101P employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds per month.

The

calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in Calibration register at 0x08. The calibration bits occupy the five lower order bits in the Calibration register. These bits are set to represent any value between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration and a ‘0’ indicates negative calibration. Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.

Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is loaded into the register, only the first two minutes of the 64-minute cycle are modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm of adjustment per calibration step in the Calibration register.

To determin e the required calibration, the CAL bit in the Flags register (0x00) must be set to ‘1’. This causes the INT pin to toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of –10 (001010b) must be loaded into the Calibration register to offset this error.

Note Setting or changing the Calibration register does not affect the test output frequency.

To set or clear CAL, set the write bit “W” (in the flags register at 0x00) to “1” to enable writes to the Flag register. Write a value to CAL, and then reset the write bit to “0” to disable writes.

20 ppm to +35 ppm. However,

Alarm

The alarm function compares user programmed values of alarm time and date (stored in the registers 0x01-5) with the corresponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on INT pin if Alarm Interrupt Enable (AIE) bit is set.

There are four alarm match fields - date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to ‘0’ indicates that the corresponding field is used in the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. Selecting all match bits (all 0s) causes an exact time an d date match.

There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at 0x00 indicates that a date or time match has occurred. The AF bit is set to “1” when a match occurs. Reading the flags register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event.

T o set, clear or enable an alarm, set the ‘W’ bit (in Flags Register

- 0x00) to ‘1’ to enable writes to Alarm Registers. After writing the alarm value, clear the ‘W’ bit back to “0” for the changes to take effect.

Note CY14B101P requires the alarm match bit for seconds (0x02 - D7) to be set to ‘0’ for proper operation of Alarm Flag and Interrupt.

Watchdog Timer

The Watchdog Timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the Watchdog Timer register.

The timer consists of a loadable register and a free running counter. On power up, the watchdog time out value in register 0x07 is loaded into the Counter Load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is compared to the terminal value of ‘0’. If the counter reaches this value, it causes an internal flag and an optional interrupt output. You can prevent the time out interrupt by setting WDS bit to ‘1’ prior to the counter reaching ‘0’. This causes the counter to reload with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and WDT flag never occur.

New time out values are written by setting the watchdog write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 21 on page 16. Note that setting the watchdog time out value to ‘0’ disables the watchdog function.

The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out. If the Watchdog Interrupt Enable (WIE) bit in the Interrupt register is set, a hardware interrupt on INT pin is also generated on watchdog timeout. The flag and the hardware interrupt are bo th cleared when user reads the Flags registers.

Document #: 001-44109 Rev. *B Page 15 of 32

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PRELIMINARY

CY14B101P

1 Hz

Oscillator

Clock

Divider

Counter

Zero

Compare

WDF

WDS

Load

WDW

Watchdog

write to

Watchdog

32 Hz

32,768 KHz

Figure 21. Watchdog Timer Block Diagram

Power Monitor

The CY14B101P provides a power management sche me with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low V

access. The power monitor is based on an internal band gap

reference circuit that compares the V threshold.

voltage to V

SWITCH

As described in the section “AutoStore Operation” on page 3, when V store operation is initiated from SRAM to the nonvolatile

is reached as VCC decays from power loss, a data

SWITCH

elements, securing the last SRAM data state. Power is also switched from V operate the RTC oscillator.

to the backup supply (battery or capacitor) to

When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not available to the user. The clock continues to operate in the background. The updated clock data is available to the user t

HRECALL

“AutoStore or Power Up RECALL” on page 26).

delay after VCC is restored to the device (see

Interrupts

The CY14B101P has a Flags register, Interrupt register, and Interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer . Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x06). In addition, each has an associated flag bit in the Flags register (0x00) that the host processor uses to determine the cause of the interrupt. The INT pin driver has two bits that specify its behavior when an interrupt occurs.

An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled (set to ‘1’). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the

Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the Flags register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section.

Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode.

Note CY14B101P generates valid interrupts only after the Powerup Recall sequence is completed. All events on INT pin must be ignored for t

duration after powerup.

Interrupt Register

Watchdog Interrupt Enable - WIE. When set to ‘1’, the

watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs. When WIE is set to ‘0’, the watchdog timer only affects the WDF flag in Flags register.

Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match drives the INT pin and an internal flag. When AIE is set to ‘0’, the alarm match only affects the AF flag in Flags register.

Power Fail Interrupt Enable - PFE. When set to ‘1’, the power fail monitor drives the pin and an internal flag. When PFE is set to ‘0’, the power fail monitor only affects the PF flag in Flags register.

High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH and the driver mode is push pull. The INT p in drives high only when V is active LOW and the drive mode is open drain. The INT pin

is greater than V

. When set to a ‘0’, the INT pin

SWITCH

must be pulled up to Vcc by a 10k resistor while using the interrupt in active LOW mode.

Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to a ‘0’, the INT pin is driven high or low (determined by H/L) until the Flags or Control register is read.

When an enabled interrupt source activates the INT pin, an external host reads the Flags registers to determine the cause. Remember that all flags are cleared when the register is read. If the INT pin is programmed for Level mo de, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for Pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete i ts specified duration if the Flags register is read. If the INT pin is used as a host reset, the Flags register is not read during a reset.

Flags Register

The Flag register has three flag bits: WDF , AF, and PF , which can be used to generate an interrupt. These flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable inter- rupts to be informed when a flag is set. These flags are automatically reset once the register is read. The flags register is automatically loaded with the value 0x00 on power up (except for the OSCF bit. See “Stopping and Starting the Oscillator” on page 14.)

Document #: 001-44109 Rev. *B Page 16 of 32

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CY14B101P

Accessing the Real Time Clock through SPI

Recommended Values

Y1 = 32.768KHz C

= 21pF

out

Note: The recommended values for C1 and C2 include

board trace capacitance.

Watchdog

Timer

Power

Monitor

Clock

Alarm

VINT

WDF

WIE

PFE

AIE

P/L

Driver

H/L

INT

WDF - Watchdog Timer Flag WIE - Watchdog Interrupt

PF - Power Fail Flag

PFE - Power Fail Enable AF - Alarm Flag

AIE - Alarm Interrupt Enable P/L - Pulse Level

H/L - High/Low

Enable

CY14B101P uses 16 registers for Real Time Clock (RTC). These registers can be read out or written to by accessing all 16 registers in burst mode or accessing each register, one at a time. The RDRTC and WRTC instructions are used to access the RTC.

All the RTC registers can be read in burst mode by issuing the RDRTC instruction and and reading all 16 bytes without bringing the CS

pin HIGH. The ‘R’ bit must be set while reading the RTC

Figure 22. RTC Recommended Component Configura ti on

timekeeping registers to ensure that transitional values of time are not read.

Writes to the RTC register are performed using the WRTC instruction. Writing RTC timekeeping registers and control registers, except for the flag register needs the ‘W’ bit of the flag register to be set to “1”. The internal counters are updated wi th the new date and time setting when the ‘W’ bi t is cleared to ‘0 ’. All the RTC registers can also be written in burst mode using the WRTC instruction.

Figure 23. Interrupt Block Diagram

Document #: 001-44109 Rev. *B Page 17 of 32

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CY14B101P

Table 9. RTC Register Map

Note

1. ( ) designates values shipped from the factory.

2. The unused bits of RTC registers are reserved for future use and should be set to ‘0’

3. This is a binary value, not a BCD value.

D7 D6 D5 D4 D3 D2 D1 D0

[1, 2]

BCD Format Data

Function/Range

0x0F 10s Years Years Years: 00–99 0x0E 0 0 0 10s

Months Months: 01–12

Months 0x0D 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0x0C 0 0 0 0 0 Day of week Day of week: 01–07 0x0B 0 0 10s Hours Hours Hours: 00–23 0x0A 0 10s Minutes Minutes Minutes: 00–59

0x09 0 10s Seconds Seconds Seconds: 00–59 0x08 OSCEN

(0) 0x07 WDS (0) WDW (0) WDT (000000) Watchdog 0x06 WIE (0) AIE (0) PFE (0) 0 H/L (1) P/L (0) 0 0 Interrupts

0Cal Sign

(0)

Calibration (00000) Calibration Values

[3]

0x05 M (1) 0 10s Alarm Date Alarm Day Alarm, Day of Month: 01–31 0x04 M (1) 0 10s Alarm Hours Alarm Hours Alarm, Hours: 00–23 0x03 M (1) 10 Al arm Minutes Alarm Minutes Alarm, Minutes: 00–59 0x02 M (1) 10 Alarm Seconds Alarm, Seconds Alarm, Seconds: 00–59 0x01 10s Cen tu r ies Centuries Centuries: 00–99 0x00 WDF AF PF OSCF 0 CAL (0) W (0) R (0) Flags

[3]

Document #: 001-44109 Rev. *B Page 18 of 32

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CY14B101P

Table 10. Register Map Detail

Time Keeping - Years

D7 D6 D5 D4 D3 D2 D1 D0

0x0F

Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.

D7 D6 D5 D4 D3 D2 D1 D0

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0X08

OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator

Calibration

Sign

Calibration These five bits control the calibration of the clock.

0 0 0 10s Month Months

Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 10s Day of Month Day of Month

Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap years are automatically adjusted for.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 Day of Week

Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 10s Hours Hours

Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.

D7 D6 D5 D4 D3 D2 D1 D0

0 10s Minutes Minutes

Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.

D7 D6 D5 D4 D3 D2 D1 D0

Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.

D7 D6 D5 D4 D3 D2 D1 D0

OSCEN 0 Calibration

saves battery or capacitor power during storage. Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.

10s Years Years

Time Keeping - Months

Time Keeping - Date

Time Keeping - Day

Time Keeping - Hours

Time Keeping - Minutes

Time Keeping - Seconds

10s Seconds Seconds

Calibration/Control

Calibration

Sign

Document #: 001-44109 Rev. *B Page 19 of 32

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CY14B101P

Table 10. Register Map Detail (continued)

WatchDog Timer

0x07

WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit

WDW Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0). This enables

WDT Watchdog timeout selection. The watchdog timer inte rval is selected by the 6-bit value in this register. It represents a

0x06

WIE Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and

AIE Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm

PFE Power Fai l Enable. When set to 1, the alarm match drives the INT pin and the PF flag. When set to 0, the power fail

0 Reserved for future use H/L HIGH/LOW. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW. P/L Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately

0x05

M Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit

0x04

M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit

0x03

M Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match

D7 D6 D5 D4 D3 D2 D1 D0

WDS WDW WDT

is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.

the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in

Watchdog Timer on page 15.

multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.

Interrupt Status/Control

D7 D6 D5 D4 D3 D2 D1 D0

WIE AIE PFE 0 H/L P/L 0 0

the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.

match only affects the AF flag.

monitor affects only the PF flag.

200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read.

Alarm - Day

D7 D6 D5 D4 D3 D2 D1 D0

M 0 10s Alarm Date Alarm Date

Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.

to ignore the date value.

Alarm - Hours

D7 D6 D5 D4 D3 D2 D1 D0

M 10s Alarm Hours Alarm Hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

to ignore the hours value.

Alarm - Minutes

D7 D6 D5 D4 D3 D2 D1 D0

M 10s Alarm Minutes Alarm Minutes

Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.

circuit to ignore the minutes value.

Document #: 001-44109 Rev. *B Page 20 of 32

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CY14B101P

Table 10. Register Map Detail (continued)

Alarm - Seconds

0x02

M Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match

0x01

0x00

WDF Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset

AF Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the

PF Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold V

OSCF Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This

CAL Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes

W Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to RTC registers,

R Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during

D7 D6 D5 D4 D3 D2 D1 D0

M 10s Alarm Seconds Alarm Seconds

Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.

circuit to ignore the seconds value.

Time Keeping - Centuries

D7 D6 D5 D4 D3 D2 D1 D0

10s Centuries Centuries

Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.

Flags

D7 D6 D5 D4 D3 D2 D1 D0

WDF AF PF OSCF 0 CAL W R

by the user. It is cleared to 0 when the Flags register is read or on power up

match bits = 0. It is cleared when the Flags register is read or on power up.

. It is cleared to

0 when the Flags register is read or on power up.

indicates that RTC backup power failed and clock value is no longer valid. This bit survives power cycle and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag.

normal operation. This bit defaults to 0 (disabled) on power up.

Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power up.

the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.

SWITCH

Document #: 001-44109 Rev. *B Page 21 of 32

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PRELIMINARY

CY14B101P

Maximum Ratings

Notes

4. The HSB

pin has I

OUT

= -2 uA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled st andard VOH and VOL are valid. This

parameter is characterized but not tested.

5. V

CAP

(Storage capacitor) nominal value is 68uF.

Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Maximum Accumulated Storage Time

At 150°C Ambient Temperature........................ 1000h

At 85°C Ambient Temperature..................... 20 Years

Ambient Temperature with

Power Applied ............................................–55°C to +150°C

Supply Voltage on V DC Voltage Applied to Outputs

in High-Z State.......................................–0.5V to V

Input Voltage..........................................–0.5V to V

Relative to GND........–0.5V to +4.1V

CC CC

+ 0.5V + 0.5V

Transient Voltage (<20 ns) on

Any Pin to Ground Potential..................–2.0V to V

+ 2.0V

Package Power Dissipation Capability (T

= 25°C) ...................................................1.0W

Surface Mount Lead Soldering

Temperature (3 Seconds).......................................... +260°C

DC Output Current (1 output at a time, 1s duration)..... 15mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Table 11. Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 2.7V to 3.6V Industrial –40°C to +85°C 2.7V to 3.6V

DC Electrical Characteristics

Over the Operating Range (VCC = 2.7V to 3.6V)

Parameter Description Test Conditions Min Max Unit

CC1

CC2

CC4

V V V V

[4]

IH IL OH OL

CAP

Average Vcc Current At f Average VCC Current

during STORE Average V

during AutoStore

CAP

Current

Cycle VCC Standby Current 5mA Input Leakage Current

(except HSB

)

Input Leakage Current (for HSB

)

Off State Output Leakage Current

Input HIGH Voltage 2.0 VCC + 0.5 V Input LOW Voltage VSS – 0.5 0.8 V Output HIGH Voltage I Output LOW Voltage I

[5]

Storage Capacitor Between V

= 40 MHz 10 mA

SCK

All Inputs Don’t Care, VCC = Max. Average current for duration t

STORE

10 mA

All Inputs Don’t Care, VCC = Max. Average current for duration t

= Max, VSS < V

VCC = Max, VSS < V

= –2 mA 2.4 V

OUT

= 4 mA 0.4 V

OUT

CAP

OUT

pin and VSS, 5V Rated 61 180 µF

< V

STORE

–1 +1 µA

–100 +1 µA

–1 +1 µA

5mA

Document #: 001-44109 Rev. *B Page 22 of 32

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CY14B101P

Data Retention and Endurance

3.0V

OUTPUT

5 pF

789Ω

3.0V

OUTPUT

30 pF

789Ω

577Ω

Note

6. These parameters are guaranteed by design and are not tested.

Parameter Description Min Unit

DATA NV

Data Retention 20 Years Nonvolatile STORE Operations 200 K

Capacitance

Parameter

OUT

[6]

Input Capacitanc e TA = 25°C, f = 1MHz, Output Pin Capacitance 8 pF

Description Test Conditions Max Unit

6pF

= 3.0V

Thermal Resistance

Parameter

[6]

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

Description Test Conditions 16-SOIC Unit

Test conditio ns follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51.

Figure 24. AC Test Loads and Waveforms

TBD °C/W

AC Test Conditions

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <

Input and Output Timing Reference Levels....................1.5V

Document #: 001-44109 Rev. *B Page 23 of 32

3 ns

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CY14B101P

Table 12. RTC Characteristics

Notes

7. Current drawn from either V

RTCcap

or V

RTCbat

when VCC < V

SWITCH.

Parameters Description Test Conditions Min Typ Max Units

BAK

RTCbat

RTCcap

OCS

[7]

RTC Backup Current Room Temperature (25oC) 300 nA

Hot Temperature (85

C) 450 nA RTC Battery Pin Voltage 1.8 3.0 3.3 V RTC Capacitor Pin Volt age 1.5 3.0 3.6 V RTC Oscillator Time to Start 1 2 sec

AC Switching Characteristics

Cypress

Parameter

SCK

CSS

CSH

HHZ

HZCS

Alt. Parameter Description

SCK

CES

CEH

DIS

Clock Frequency, SCK 40 25 MHz Clock Pulse Width LOW 11 18 ns Clock Pulse Width HIGH 11 18 ns CS HIGH Time 20 20 ns CS Setup Time 10 10 ns CS Hold Time 10 10 ns Data In Setup Time 5 5 ns Data In Hold Time 5 5 ns HOLD Hold Time 5 5 ns HOLD Setup Time 5 5 ns Output Valid 9 15 ns HOLD to Output HIGH Z 15 15 ns HOLD to Output LOW Z 15 15 ns Output Hold Time 0 0 ns Output Disable Time 25 25 ns

40 MHz

25 MHz

(RDRTC Instruction)

Min Max Min Max

Unit

Document #: 001-44109 Rev. *B Page 24 of 32

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CY14B101P

Figure 25. Synchronous Data Timing (Mode 0)

HI-Z

VALID IN

HI-Z

SCK

CSS

CSH

HZCS

SCK

HOLD

HHZ

HLZ

Figure 26. HOLD Timing

Document #: 001-44109 Rev. *B Page 25 of 32

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CY14B101P

AutoStore or Power Up RECALL

Notes

8. t

starts from the time VCC rises above V

SWITCH.

9. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.

10.On a Hardware Store, Software Store / Recall, AutoS tore Enab le / Disable and AutoS tore initiati on, SRAM operation continues to be ena bled for time t

DELAY

.Read and

Write cycles are ignored during STORE, RECALL, and while VCC is below V

SWITCH.

11. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.

STORE

HHHD

DELAY

VCCRISE

Note

LZHSB

SWITCH

HDIS

HSB OUT

Autostore

POWER-UP RECALL

Read and Write Inhibited (RWI)

POWER-UP RECALL

Read and Write Read and Write

BROWN OUT AUTOSTORE

POWER DOWN AUTOSTORE

Parameters Description

[8]

STORE

DELAY

SWITCH

VCCRISE

HDIS

LZHSB

HHHD

[9]

[10]

[6]

Power Up RECALL Duration 20 ms STORE Cycle Duration 8 ms Time Allowed to Complete SRAM Cycle 25 ns Low Voltage Trigger Level 2.65 V VCC Rise Time 150 µs

HSB Output Driver Disable Voltage 1.9 V HSB To Output Active Time 5 µs

HSB High Active Time 500 ns

Switching Waveforms

Figure 27. AutoStore or Power Up RECALL

CY14B101P

Min Max

[10]

Unit

Document #: 001-44109 Rev. *B Page 26 of 32

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CY14B101P

Software Controlled STORE/RECALL Cycles

0 1 1 0 0 0 0 0

SCK

0 1 2 3 4 5 6 7

RWI

Hi-Z

RDY

RECALL

Notes

12.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to eff ectively register command.

13.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Parameter Description

RECALL

[11, 13]

RECALL Duration 200 µs Soft Sequence Processing Time 100 µs

SCK

RWI

RDY

Figure 28. Software STORE Cycle

0 1 2 3 4 5 6 7

0 0 1 1 1 1 0 0

Hi-Z

Figure 29. Software RECALL Cycle

CY14B101P

Min Max

[13]

STORE

[13]

Unit

Document #: 001-44109 Rev. *B Page 27 of 32

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CY14B101P

Hardware STORE Cycle

HSB (IN)

HSB (OUT)

RWI

HSB (IN)

HSB (OUT)

RWI

HHHD

STORE

PHSB

DELAY

LZHSB

DELAY

DHSB

PHSB

HSB pin is driven high to VCC only by Internal 100K: resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW.

Write Latch not set

Write Latch set

Parameter Description

DHSB

PHSB

HSB To Output Active Time when write latch not set 25 ns Hardware STORE Pulse Width 15 ns

Figure 30. Hardware STORE Cycle

CY14B101P

Unit

Min Max

[9]

Document #: 001-44109 Rev. *B Page 28 of 32

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CY14B101P

Option: T - Tape & Reel Blank - Std.

P - Serial SPI nvSRAM with RTC

Density: 101 - 1 Mb

Voltage: B - 3.0V

Cypress

CY 14 B 101 P - SF X C T

nvSRAM

14 - Auto Store + Software Store + Hardware Store

Pb-Free

Package:

SF - 16 SOIC

Temperature:

C - Commercial (0 to 70

I - Industrial (-40 to 85

Ordering Information

Ordering Code Package Diagram Package Type Operating Range

CY14B101P-SFXCT 51-85022 16 SOIC CY14B101P-SFXC 51-85022 16 SOIC CY14B101P-SFXIT 51-85022 16 SOIC CY14B101P-SFXI 51-85022 16 SOIC

All the above parts are Pb - free. The above table contains advance information. Contact your local Cypress sales representative for availability of these parts.

Commercial

Industrial

Part Numbering Nomenclature

Document #: 001-44109 Rev. *B Page 29 of 32

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CY14B101P

Package Diagrams

51-85022 *B

Figure 31. 16-Pin (300 mil) SOIC Package (51-85022)

Document #: 001-44109 Rev. *B Page 30 of 32

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Document History Page

Document Title: CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Document Number: 001-44109

REV. ECN NO.

** 1939467 See ECN UNC/AESA New Data Sheet

*A 2607447 11/21/2008 GSIN/

*B 2654487 02/04/2009 GVCH/GSIN/

Submission

Date

Orig. of Change

GVCH/AESA

PYRS

Description of Change

Updated the “Feature” section, Clock rate changed from 40 MHz to 25 MHz Updated nvSRAM STORE, RECALL, AutoStore Enable/Disable sections

-- Removed Soft Sequence, added SPI instructions for STORE, RECALL, AutoStore Enable and Disable, Updated SPI with following changes:

-- Added more information for protocol

-- Added four new SPI instruction

-- WEN bit cleared on CS going HIGH edge after Write instructions and four nvSRAM special instructions

-- Added RDY Added READ RTC and WRITE RTC instructions. Changed RTC recommended configuration values. Updated tOCS values for normal and room temperature Other changes as per new EROS

-- Removed 8 SOIC package

-- Added two new 8DFN packages

-- Changed tCO parameter to 9 ns

-- Updated data sheet template

--Replaced CY14B101P with CY14B101PA. Changed title to “CY14B101PA 1Mbit (128K x 8) Serial SPI nvSRAM with Real-Time-Clock”

Moved from Advance information to Preliminary Changed part number from CY14B101PA to CY14B101P Changed X Updated pin description of V Updated Device operation and SPI peripheral interface description Added Factory setting values for BP1, BP2 and WPEN bits Updated Real Time Clock operation description Added footnote 2 Added default values to RTC Register Map” table 8 Added footnote 3 Updated flag register description in Register Map Detail” table 9 Changed C1, C2 values to 21pF, 21pF respectively Changed I Changed I Changed V

bit to Status Register for indicating Store/Recall in progress

, X2 pin names to X

from 5 mA to 10 mA

CC2

value from 350 nA to 450 nA at hot temperature

BAK

typical value from 2.4V to 3.0V

RTCcap

, Xin respectively

out

CAP

Document #: 001-44109 Rev. *B Page 31 of 32

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CY14B101P

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

Products

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© Cypress Semiconductor Corporation, 2008- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express wr i tte n ag reement with Cypress. Furthermore, Cypress does not auth or i ze i t s pr o ducts for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spe cified above is prohibited wi thout the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-44109 Rev. *B Revised February 2, 2009 Page 32 of 32

AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respectiv e holders.

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Cypress CY14B101P User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Logic Block Diagram

Overview

Pinouts

Device Operation

SRAM Write

SRAM Read

STORE Operation

AutoStore Operation

Software Store Operation

Hardware Store and HSB pin Operation

RECALL Operation

Hardware Recall (Power Up)

Software Recall

Disabling and Enabling AutoStore

Serial Peripheral Interface

SPI Overview

SPI Master

SPI Slave

Data Transmission SI/SO

Most Significant Bit (MSB)

Serial Opcode

Invalid Opcode

Serial Clock (SCK)

Status Register

SPI Modes

SPI Operating Features

Power Up

Power On Reset

Power Down

Active Power and Standby Power Modes

SPI Functional Description

Status Register

Read Status Register (RDSR) Instruction

Write Status Register (WRSR) Instruction

Write Protection and Block Protection

Write Enable (WREN) Instruction

Block Protection

Hardware Write Protection (WP Pin)

Write Disable (WRDI) Instruction

Memory Access

Read Sequence (READ)

Write Sequence (WRITE)

READ RTC (RDRTC) Instruction

WRITE RTC (WRTC) Instruction

Software Store (STORE)

Software Recall (RECALL)

AutoStore Disable (ASDISB)

HOLD Pin Operation

AutoStore Enable (ASENB)

Real Time Clock Operation

nvTIME Operation

Clock Operations

Backup Power

Reading the Clock

Setting the Clock

Stopping and Starting the Oscillator

Calibrating the Clock

Alarm

Watchdog Timer

Power Monitor

Interrupts

Flags Register

Accessing the Real Time Clock through SPI

Maximum Ratings

DC Electrical Characteristics

Data Retention and Endurance

Capacitance

Thermal Resistance

AC Test Conditions

AC Switching Characteristics

AutoStore or Power Up RECALL

Switching Waveforms

Software Controlled STORE/RECALL Cycles

Hardware STORE Cycle

Ordering Information