Cypress CY14B101P User Manual

PRELIMINARY

CY14B101P

1 Mbit (128K x 8) Serial SPI nvSRAM

with Real Time Clock

Features

Instruction

Address Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction decode

Write protect Control logic

Quantum Trap

STORE

RECALL

SCK

CAP

HSB

128K X 8

SRAM ARRAY

128K X 8

RTC

Xout Xin INT

MUX

A0-A16

D0-D7

HOLD

Logic Block Diagram

■

1 Mbit NonV olatile SRAM

❐

Internally organized as 128K x 8

❐

STORE to QuantumTrap® nonvolatile elements initiated automatically on power down (AutoStore®) or by user using HSB pin (Hardware Store) or SPI instruction (Software S tore)

❐

RECALL to SRAM initiated on power up (Power Up Recall®) or by SPI Instruction (Software Recall)

❐

Automatic STORE on power down with a small capacitor

■

High Reliability

❐

Infinite Read, Write, and RECALL cycles

❐

200,000 STORE cycles to QuantumTrap

❐

Data Retention: 20 Years

■

Real Time Clock

❐

Full featured Real Time Clock

❐

Watchdog timer

❐

Clock alarm with programmable interrupts

❐

Capacitor or battery backup for RTC

❐

Backup current of 300 nA

■

High Speed Serial Peripheral Interface (SPI)

❐

40 MHz Clock rate - RTC Read at 25 MHz

❐

Supports SPI Modes 0 (0,0) and 3 (1,1)

■

Write Protection

❐

Hardware Protection using Write Protect (WP) Pin

❐

Software Protection using Write Disable Instruction

❐

Software Block Protection for 1/4, 1/2, or entire Array

■

Low Power Consumption

❐

Single 3V +20%, –10% operation

❐

Average Vcc current of 10 mA at 40 MHz operation

■

Industry Standard Configurations

❐

Commercial and industrial temperatures

❐

16-pin SOIC Package

❐

RoHS compliant

Overview

The Cypress CY14B101P combines a 1 Mbit nonvolatile static RAM with full featured real time clock in a monolithic integrated circuit with serial SPI interface. The memory is organized as 128K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600 Document #: 001-44109 Rev. *B Revised February 2, 2009

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CY14B101P

Pinouts

INT

GND

CAP

SCK

HSB

HOLD

To p V ie w

not to scale

RTCbat

out

RTCcap

Figure 1. Pin Diagram - 16-Pin SOIC

Table 1. Pin Definitions

Pin Name I/O Type Description

SCK Input Serial Clock. Runs at speeds up to a maximum of 25 MHz. All inputs are latched at the rising edge

SI Input Serial Input. Pin for input of all SPI instructions and data.

SO Output Serial Output. Pin for output of data through SPI.

HOLD

HSB

CAP

RTCcap

RTCbat

Xout Output Crystal Output connection. Drives crystal on start up.

Xin Input Crystal Input connection. For 32.768 kHz crystal.

INT

NC No Connect No Connect. This pin is not connected to the die.

GND Power Supply Ground

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Input Chip Select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low

power standby mode.

of this clock. Outputs are driven at the falling edge of the clock.

Input Write Protect. Implements hardware write protection in SPI. Input HOLD Pin. Suspends Serial Operation.

Input/Output Hardware Store Busy: A weak internal pull up keeps this pin pulled HIGH. If not used, this pin is

left as No Connect. Output: Indicates busy status of nvSRAM when LOW. Input: Hardware Store implemented by pulling this pin LOW externally.

Power Supply AutoStore Capacitor . Supplies power to the nvSRAM during power loss to STORE data from the

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It

must never be connected to GND. Power Supply Capacitor Backup for RTC. Left unconnected if V Power Supply Battery Backup for RTC. Left unconnected if V

RTCcap

RTCbat

is used.

Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power

monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).

Power Supply Power Supply (2.7-3.6V)

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CY14B101P

Device Operation

CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC and SPI interface. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence that transfers the data in parallel to the nonvolatile Quantum Trap cells. A small capacitor (V is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power down data security. The Quantum Trap nonvolatile elements built in the reliable SONOS technology make nvSRAM the ideal choice for secure data storage.

In CY14B101P, the 1-Mbit memory array is organized as 128K words x 8 bits. The memory is accessed through a standard SPI interface that enables very high clock speeds upto 40 MHz with zero delay read and write cycles. CY14B101P supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 & 1, 1) and operates as SPI slave. The device is enabled using the Chip Select pin (CS

) and accessed through Serial Input (SI), Serial

Output (SO), and Serial Clock (SCK) pins. CY14B101P provides the feature for hardware and software

write protection through WP

pin and WRDI instruction. CY14B101P also provides mechanisms for block write protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the status register. Further, the HOLD

pin is used to suspend any

serial communication without resetting the serial sequence. CY14B101P uses the standard SPI opcodes for memory access.

In addition to the general SPI instructions for read and write, CY14B101P provides four special instructions that allow access to four nvSRAM specific functions: STORE, RECALL, AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).

The major benefit of nvSRAM SPI over serial EEPROMs is that all reads and writes to nvSRAM are performed at th e speed of SPI bus with zero cycle delay. Therefore, no wait time is required after any of the memory accesses. The STORE and RECALL operations need finite time to complete and all memory accesses are inhibited during this time. While a STORE or RECALL operation is in progress, the busy status of the device is indicated by the Hardware Store Busy (HSB RDY

bit of the Status Register.

) pin and also reflected on the

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not use up any endurance cycles of the nonvolatile memory. This enables user to perform infinite write operations. A write cycle is performed through the SPI WRITE instruction. The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode, 3 bytes of address and 1 byte of data. Writes to nvSRAM is done at SPI bus speed with zero cycle delay.

CY14B101P allows burst mode writes to be performed through SPI. This enables write operations on consecutive addresses without issuing a new WRITE instruction. When the last address in memory is reached in burst mode, the address rolls over to 0x0000 and the device continues to write.

The SPI write cycle sequence is defined in the Memory Access section of SPI Protocol Description.

CAP

SRAM Read

A read cycle in CY14B101P is performed at the SPI bus speed and the data is read out with zero cycle delay after the READ instruction is performed. The READ instruction is issued through the SI pin of the nvSRAM and consists of the READ opcode and 3 bytes of address. The data is read out on the SO pin.

CY14B101P allows burst mode reads to be performed through

)

SPI. This enables reads on consecutive addresses without issuing a new READ instruction. When the last address in memory is reached in burst mode read, the address rolls over to 0x0000 and the device continues to read.

The SPI read cycle sequence is defined in the Memory Access section of SPI Protocol Description

STORE Operation

STORE operation transfers the data from the SRAM to the nonvolatile Quantum Trap cells. The CY14B101P STOREs data to the nonvolatile cells using one of the three STORE operations: AutoStore, activated on device power down; Software Store, activated by a STORE instruction in the SPI; and Hardware Store, activated by the HSB

. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.

The HSB

signal or the RDY bit in the Status register can be monitored by the system to detect if a STORE cycle is in progress. The busy status of nvSRAM is indicated by HSB being pulled LOW or RDY

bit being set to ‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore and Hardware Store operations are ignored unless at least one write opera tion has taken place since the most recent STORE or RECALL cycle. However, software initiated STORE cycles are performed regardless of whether a write operation has taken place.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap during power down. This STORE mechanism is implemented using a capacitor (V data in the nonvolatile memory when power goes down.

During normal operation, the device draws current from V charge the capacitor connected to the V voltage on the V the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the V initiated if no write cycle has been performed since last RECALL.

During power down, the memory accesses are inhibited after the voltage on V writes, ensure that CS Therefore, during power down the device must be deselected and CS

must be allowed to follow VCC.

Figure 2 shows the proper connection of the storage capacitor

) for AutoStore operation. Refer to DC Electrical Charac-

CAP

teristics on page 22 for the size of the V

) and enables the device to safely STORE the

CAP

pin. When the

pin drops below V

capacitor. The AutoStore operation is not

CAP

pin drops below V

is not left floating prior to this event.

SWITCH

CAP

during power down,

SWITCH

. To avoid inadvertent

CAP

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CY14B101P

Figure 2. AutoStore Mode

0.1uF

Vcc

10kOhm

CAP

Vcc

CAP

Software Store Operation

Software Store allows the user to trigger a STORE operation through a special SPI instruction. This operation is initiated irrespective of whether a write has been performed since last nv operation.

A STORE cycle takes t the memory accesses to nvSRAM are inhibited. The RDY the Status register or the HSB Ready/Busy status of the nvSRAM. After the t is completed, the SRAM is activated again for read an d write

time to complete, during which all

STORE

pin may be polled to find the

STORE

operations.

Hardware Store and HSB pin Operation

The HSB pin in CY14B101P is used to control and acknowledge STORE operations. If no STORE/RECALL is in progress, this pin can be used to request a Hardware Store cycle. When the HSB pin is driven LOW, the CY14B101P conditionally initiates a STORE operation after t starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for t

STORE

The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, when a STORE cycle (initiated by any means) or Power up Recall is in progress. Upon completion of the STORE operation, CY14B101P remains disabled until the HSB pin returns HIGH. HSB pin must be left unconnected if not used.

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile Quantum Trap elements to the SRAM. In CY14B101P, a RECALL may be initiated in two ways: Hardware Recall, initiated on power up; and Software Recall, initiated by a SPI RECALL instruction.

Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. All memory accesses are inhibited while a RECALL

duration. An actual STORE cycle

DELAY

duration or as long as HSB pin is LOW.

bit of

cycle time

cycle is in progress. The RECALL operation in no way alters the data in the nonvolatile elements.

Hardware Recall (Power Up)

During power up, when VCC crosses V RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM.

A Power Up Recall cycle takes t memory access is disabled during this time. HSB

time to complete and the

detect the Ready status of the device.

SWITCH

, an automatic

pin is used to

Software Recall

Software Recall allows the user to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM. In CY14B101P, this can be done by issuing a RECALL instruction in SPI.

A Software Recall takes t memory accesses to nvSRAM are inhibited. The controller must

to complete during which all

RECALL

provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions.

Disabling and Enabling AutoStore

If the application does not require the AutoStore feature, it can be disabled in CY14B101P by using the ASDISB instruction. If this is done, the nvSRAM does not perform a STORE operation at power down.

AutoStore can be re-enabled by using the ASENB instruction. However, these operations are not nonvolatile and if the user needs this setting to survive power cycle, a STORE operation must be performed following Autostore Disable or Enable operation.

Note CY14B101P comes from the factory with AutoStore Enabled.

Note If AutoStore is disabled and V recommended that the V never be connected to GND. Power Up Recall operation cannot

pin is left open. V

CAP

is not required, it is

CAP

pin must

CAP

be disabled in any case.

Serial Peripheral Interface

SPI Overview

The SPI is a four-pin interfa ce with Chip Select ( CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. CY14B101P provides serial access to nvSRAM through SPI interface. The SPI bus on CY14B101P can run at speeds up to 40 MHz for all instructions except RDRTC which runs at 25 MHz.

The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on SPI bus is activated using the Chip Select pin.

The relationship between chip select, clock, and data is dictated by the SPI mode. CY14B101P supports SPI modes 0 and 3. In both these modes, data is clocked into the nvSRAM on the rising edge of SCK starting from the first rising edge after CS active.

The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS

is activated the first byte transferred from the bus

goes

Document #: 001-44109 Rev. *B Page 4 of 32

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PRELIMINARY

CY14B101P

master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued.

The commonly used terms used in SPI protocol are given below:

SPI Master

The SPI Master device controls the operations on a SPI bus. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and master may select any of the slave devices using the Chip Select pin. All the operations must be initiated by the master activating a slave device by pulling the CS also generates the Serial Clock (SCK) and all the data transmission on SI and SO lines are synchronized with this clock.

SPI Slave

SPI slave device is activated by the master through the Chip Select line. A slave device gets the Serial Clock (SCK) as an input from the SPI master and all the communication is synchronized with this clock. SPI slave never initiates a communication on the SPI bus and acts on the instruction from the master.

CY14B101P operates as a slave device and may share the SPI bus with multiple CY14B101P devices or other SPI devices.

Chip Select (CS

For selecting any slave device, the master needs to pull down the corresponding CS slave device only while the CS

The CY14B101P is selected when the CS device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high impedance state.

Note A new instruction must begin with the falling edge of Chip Select (CS active Chip Select cycle.

)

). Therefore, only one opcode can be issued for each

pin of the slave LOW. The master

pin. Any instruction can be issued to a

pin is LOW.

pin is LOW. When the

Data Transmission SI/SO

SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as MOSI (Master Out Slave In) and SO is referred to as MISO (Master In Slave O ut). The master issues instructions to the slave through the SI pin, while slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier.

CY14B101P has two separate pins for SI and SO which can be connected with the master as shown in Figure 3 on page 6.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission.

CY14B101P requires a 3-byte address for any read or write operation. However, since the actual address is only 17 bits, it implies that the first seven bits, which are fed in, are ignored by the device. Although these seven bits are ‘don’t care’, Cypress recommends that these bits are treated as 0s to enable seamless transition to higher memory densities.

Serial Opcode

After the slave device is selected with CS byte received is treated as the opcode for the intended operation.

CY14B101P uses the standard opcodes for memory accesses. In addition to the memory accesses, CY14B101P provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to

Table 2 on page 7 for details on opcodes.

Invalid Opcode

If an invalid op-code is received, the op-code is ignored and the device ignores any additional serial data on the SI pin. and no valid data is sent out on the SO pin. Opcode for a new instruction is recognized only after the next falling edge of CS

going LOW, the first

Serial Clock (SCK)

Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS

CY14B101P allows SPI modes 0 and 3 for data communication. In both these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK.

Document #: 001-44109 Rev. *B Page 5 of 32

goes LOW.

Status Register

CY14B101P has an 8-bit status register. The bits in the status register are used to configure the SPI bus. These bits are described in the Table 4 on page 8.

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CY14B101P

Figure 3. System Configuration Using SPI nvSRAM

P101B41YCP101B41YC

uController

SCK

MOSI

MISO

SI SO OSISKCSSCK

HOLD HOLDCS

CS1

CS2

HOLD1

HOLD2

LSB

MSB

765432

SCK

0 1 2 3 4 5 6 7

SCK

765432

LSB

MSB

0 12 34 56 7

SPI Modes

CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

■

SPI Mode 0 (CPOL=0, CPHA=0)

■

SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched in on the rising edge of Serial Clock (SCK) starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles are considered. The output data is available on the falling edge of Serial Clock (SCK).

Figure 4. SPI Mode 0

The two SPI modes are shown in Figure 4 and Figure 5. The status of clock when the bus master is in Standby mode and not transferring data is:

■

SCK remains at 0 for Mode 0

■

SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for the either Mode 0 or Mode 3. CY14B101P detects the SPI mode from the status of SCK pin when device is selected by bringing

pin LOW. If SCK pin is LOW when device is selected, SPI

the CS Mode 0 is assumed and if SCK pin is HIGH, CY14B101P works in SPI Mode 3.

Figure 5. SPI Mode 3

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CY14B101P

SPI Operating Features

Power Up

Power up is defined as the condition when the power supply is turned on and V Chip Select (CS Therefore, CS up resistor. As a built in safety feature, Chip Select (CS edge sensitive and level sensitive. After power up, the device is not selected until a falling edge is detected on Chip Select (CS). This ensures that Chip Select (CS before going Low to start the first operation.

As described earlier, nvSRAM performs a Power Up Recall operation after power up and therefore, all memory accesses are disabled for t be probed to check the ready/busy status of nvSRAM after power up.

Power On Reset

A Power On Reset (POR) circuit is included to prevent inadvertent writes. At power up, the device does not respond to any instruction until the VCC reaches the Power On Reset threshold voltage (V threshold, the device is internally reset and performs a Power Up Recall operation. The device is in the following state after POR:

■

Deselected (after Power up, a falling edge is required on Chip Select (CS

■

Standby Power mode

■

Not in the Hold Condition

■

Status register state:

❐

Write Enable (WEN) bit is reset to 0.

❐

WPEN, BP1, BP0 unchanged from previous power down

The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous power down.

Before selecting and issuing instructions to the memory, a valid and stable V remain valid until the end of the transmission of the instruction.

Power Down

At power down (continuous decay of VCC), when VCC drops from the normal operating voltage and below the V voltage, the device stops responding to any instruction sent to it. If a write cycle is in progress during power down, it is allowed t

time to complete after Vcc transitions below V

DELAY

After this, all memory accesses are inhibited and a co nditional AutoStore operation is performed (AutoStore is not performed if no writes have happened since last RECALL cycle). This feature prevents inadvertent writes to nvSRAM from happening during power down.

However, to avoid the possibility of inadvertent writes during power down, ensure that the device is deselected and is in Standby Power Mode, and the Chip Select (CS voltage applied on V

crosses Vswitch voltage. During this time, the

) must be enabled to follow the VCC voltage.

must be connected to VCC through a suitable pull

) is both

) must have been HIGH,

duration after power up. The HSB pin can

RECALL

). After VCC transitions the POR

SWITCH

) before any instructions are started).

voltage must be applied. This voltage must

threshold

SWITCH

) follows the

Active Power and Standby Power Modes

When Chip Select (CS) is LOW, the device is selected, and is in the Active Power mode. The device consumes I specified in DC Electrical Characteristics on page 22. When Chip Select (CS

) is HIGH, the device is deselected and the device

goes into the Standby Power mode if a STORE or RECALL cycle is not in progress. If a STORE/RECALL cycle is in progress, the device goes into the Standby Power Mode after the STORE/RECALL cycle is completed. In the Standby Power mode the current drawn by the device drops to I

SPI Functional Description

The CY14B101P uses an 8-bit instruction register. Instructions and their operation codes are listed in Table 2. All instructions, addresses, and data are transferred with the MSB first and start with a HIGH to LOW CS instructions which provide access to most of the functions in nvSRAM. Further, the WP and HOLD pins provide additional functionality driven through hardware.

Table 2. Instruction Set

Instruction

Status Register

SCK

01234567

000001001

MSB

LSB

HI-Z

01234567

Data

LSB

D0D1

D5D6

MSB

The status register bits are listed in Table 3. The status register consists of Ready bit (RD Y WEN and WPEN. The RDY Ready/Busy status while a nvSRAM STORE cycle is in

) and data protection bits BP1, BP0,

bit can be polled to check the

tion and read by RDSR instruction. However, only WPEN, BP1 and BP0 bits of the Status Register can be modified by using WRSR instruction. WRSR instruction has no effect on WEN and

bits. The default value shipped from the factory for BP1,

RDY BP2 and WPEN bits is ‘0’.

progress. The status register can be modified by WRSR instruc-

Table 3. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN (0) X X X BP1 (0) BP0 (0) WEN RDY

Table 4. Status Register Bit Definition

Bit Definition Description

Bit 0 (RDY

) Ready Read Only bit indicates the ready status of device to perform a memory access. This

bit is set to “1” by the device while a STORE or Software Recall cycle is in progress.

Bit 1 (WEN) Write Enable WEN indicates if the device is write-enabled. Setting WEN = '1' enables writes and

setting WEN = '0' disables all write operations Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details see Table 5 on page 9. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details see Table 5 on page 9.

Bit 7(WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP

). For details see Table 6 on

page 10.

Read Status Register (RDSR) Instruction

The Read Status Register instruction provides access to the status register. This instruction is used to probe the Write Enable Status of the device or the Ready status of the device. RDY

bit is set by the device to 1 whenever a STORE cycle is in progress. The Block Protection and WPEN bits indicate the extent of protection employed.

This instruction is issued after the falling edge of CS

using the

opcode for RDSR.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status register. However, this instruction cannot be used to modify bit 0 and bit 1 (WEN and RDY). The BP0 and BP1 bits can be used

Figure 6. Read Status Register (RDSR) Instruction Timing

to select one of four levels of block protection. Further, WPEN bit must be set to ‘1’ to enable the use of Write Protect (WP

) pin.

WRSR instruction is a write instruction and needs writes to be enabled (WEN bit set to ‘1’) using the WREN instruction before it is issued. The instruction is issued after the falling edge of CS using the opcode for WRSR followed by eight bits of data to be stored in the Status Register. Since, only bits 2, 3, and 7 can be modified by WRSR instruction, it is recommended to leave the other bits as ‘0’ while writing to the Status Register.

Note In CY14B101P, the values written to Status Register are saved to nonvolatile memory only after a STORE operation. If AutoStore is disabled, any modifications to the Status Register must be secured by using a Software STORE operation

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Figure 7. Write Status Register (WRSR) Instruction Timing

SCK

01234567

0000000

MSB

LSB

00D7

HI-Z

01234567

Opcode

Data in

0 0 0 0 0 1 1 0

SCK

Hi-Z

0 1 2 3 4 5 6 7

0 00 00 1 00

SCK

Hi-Z

0 1 2 3 4 5 6 7

Write Protection and Block Protection

CY14B101P provides features for both software and hardware write protection using WRDI instruction and WP device also provides block protection mechanism through BP0 and BP1 pins of the Status Register.

The write enable and disable status of the device is indicated by WEN bit of the status register. The write instructions (WRSR, WRITE, and WRTC) and nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) need the write to be enabled (WEN bit = 1) before they can be issued.

Write Enable (WREN) Instruction

On power up, the device is always in the write disable state. The following WRITE, WRSR, WRTC, or nvSRAM special instruction must therefore be preceded by a Write Enable instruction. If the device is not write enabled (WEN = ‘0’), it ignores the write instructions and returns to the standby state when CS HIGH. A new CS communication. The instruction is issued following the falling edge of CS. When this instruction is used, the WEN bit of status register is set to ‘1’.

Note After completion of a write instruction (WRSR, WRITE, or WRTC) or nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to provide protection from any inadvertent writes. Therefore, WREN instruction needs to be used before a new write instruction can be issued.

falling edge is required to re-initiate serial

Figure 8. WREN Instruction

. Additionally, this

is brought

by opcode for WRDI instruction. The WEN bit is cleared on the rising edge of CS

following a WRDI instruction.

Figure 9. WRDI Instruction

Block Protection

Block protection is provided using the BP0 and BP1 pins of the Status register. These bits can be set using WRSR instruction and probed using the RDSR instruction. The nvSRAM is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any data within the protected segment is read only. Table 5 shows the function of Block Protect bits.

Table 5. Block Write Protect Bits

Level

1 (1/4) 0 1 0x18000-0x1FFFF 2 (1/2) 1 0 0x10000-0x1FFFF

3 (All) 1 1 0x00000-0x1FFFF

Status Register Bits

BP1 BP0

Array Addresses Protected

0 0 0 None

Hardware Write Protection (WP Pin)

The write protect pin (WP) is used to provide hardware write protection. WP when held HIGH. When the WP bit is “1”, all write operations to the status register are inhibited. The hardware write protection function is blocked when the

Write Disable (WRDI) Instruction

Write Disable instruction disables the write by clearing the WEN bit to ‘0’ in order to protect the device against inadvertent writes. This instruction is issued following the falling edge of CS

Document #: 001-44109 Rev. *B Page 9 of 32

followed

WPEN bit is “0”. This allows the user to install the CY14B101P in a system with the WP status register.

pin can be used along with WPEN and Block Protect bits

(BP1 and BP0) of the status register to inhibit writes to memory.

pin allows all normal read and write operations

pin is brought LOW and WPEN

pin tied to ground, and still write to the

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PRELIMINARY

CY14B101P

When WP

SCK

01234567

765432

2021222301234567

MSB LSB

Data

Op-Code

0000001

0000

0 0

A16

A1A2

17-bit Address

MSB LSB

pin is LOW and WPEN is set to “1”, any modifications to status register are disabled. Therefore, the memory is protected by setting the BP0 and BP1 bits and the WP pin inhibits any modification of the status register bits, providing hardware write protection.

Note WP going LOW when CS is still LOW has no effect on any of the ongoing write operations to the status register.

Table 6 summarizes all the protection features provided in the

CY14B101P.

Table 6. Write Protection Operation

WPEN WP WEN

Protected

Blocks

Unprotected

Blocks

Status

X X 0 Protected Protected Protected

0 X 1 Protected Writable Writable 1 LOW 1 Protected Writable Protected 1 HIGH 1 Protected Writable Writable

Memory Access

All memory accesses are done using the READ and WRITE instructions. These instructions cannot be used while a STORE or RECALL cycle is in progress. A STORE cycle in progress is indicated by the RDY

Read Sequence (READ)

The read operations on CY14B101P are performed by giving the instruction on Serial Input pin (SI) and reading the output on Serial Output (SO) pin. The following sequence needs to be followed for a read operation: After the CS select a device, the read opcode is transmitted through the SI line followed by three bytes of address. The Most Significant address byte contains A16 in bit 0 and other bits as don’t cares. Address bits A15 to A0 are sent in the following two address bytes. After the last address bit is transmitted on the SI pin, the

bit of the status register and the HSB pin.

line is pulled LOW to

Figure 10. Read Instruction Timing

data (D7-D0) at the specific address is shifted out on the SO line on the falling edge of SCK. Any other data on SI line after the last address bit is ignored.

CY14B101P allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction. If only one byte is to be read, the CS

line must be driven HIGH after one byte of data comes out. However, the read sequence may be continued by holding the CS line LOW and the address is automatically incremented and data continues to shift out on SO pin. When the last data memory address (0x1FFFF) is reached, the address rolls over to 0x0000 and the device continues to read.

Write Sequence (WRITE)

The write operations on CY14B101P are performed through the Serial Input (SI) pin. T o perform a write operation CY14B101P, if the device is write disabled, then the device must first b e write enabled through the WREN instruction. When the writes are enabled (WEN = ‘1’), WRITE instruction is issued after the falling edge of CS WRITE opcode on SI line followed by 3-bytes address sequence and the data (D7-D0) which is to be written. The Most Significant address byte contains A16 in bit 0 with other bits being don’t cares. Address bits A15 to A0 are sent in the following two address bytes.

CY14B101P allows writes to be performed in bursts through SPI which can be used to write consecutive addresses without issuing a new WRITE instruction. If only one byte is to be written, the CS transmitted. However, if more bytes are to be written, CS must be held LOW and address incremented automatically. The following bytes on the SI line are treated as data bytes and written in the successive addresses. When the last data memory address (0x1FFFF) is reached, the address rolls over to 0x0000 and the device continues to write.

The WEN bit is reset to “0” on completion of a WRITE sequence.

. A WRITE instruction constitutes transmitting the

line must be driven HIGH after the D0 (LSB of data) is

line

Document #: 001-44109 Rev. *B Page 10 of 32

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Cypress CY14B101P User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Logic Block Diagram

Overview

Pinouts

Device Operation

SRAM Write

SRAM Read

STORE Operation

AutoStore Operation

Software Store Operation

Hardware Store and HSB pin Operation

RECALL Operation

Hardware Recall (Power Up)

Software Recall

Disabling and Enabling AutoStore

Serial Peripheral Interface

SPI Overview

SPI Master

SPI Slave

Data Transmission SI/SO

Most Significant Bit (MSB)

Serial Opcode

Invalid Opcode

Serial Clock (SCK)

Status Register

SPI Modes

SPI Operating Features

Power Up

Power On Reset

Power Down

Active Power and Standby Power Modes

SPI Functional Description

Status Register

Read Status Register (RDSR) Instruction

Write Status Register (WRSR) Instruction

Write Protection and Block Protection

Write Enable (WREN) Instruction

Block Protection

Hardware Write Protection (WP Pin)

Write Disable (WRDI) Instruction

Memory Access

Read Sequence (READ)

Write Sequence (WRITE)