How it Works
Cypress
Loading...
CY14B101NA
User Manual
25 pgs914.46 Kb0
Table of contents
Loading...

Cypress CY14B101NA, CY14B101LA User Manual

Download
PRELIMINARY
CY14B101LA, CY14B101NA
1 Mbit (128K x 8/64K x 16) nvSRAM

Features

67$7,&5$0
$55$<
;
5 2 :
' ( & 2 ' ( 5
&2/801,2
&2/801'(&
, 1 3 8 7 % 8 ) ) ( 5 6
32:(5
&21752/
6725(5(&$//
&21752/
4XDWUXP7UDS
;
6725(
5(&$//
9
&&
9
&$3
+6%
$$
$
$$$$

62)7:$5( '(7(&7
$$
2(
&(
:(
%+(
%/(
$
$
$
$
$
$

$

$

$

$

'4
'4
'4
'4
'4
'4
'4
'4
'4
'4
'4

'4

'4

'4

'4

'4


Logic Block Diagram
[1, 2, 3]

Note
1. Address A
0
- A16 for x8 configuration and Address A0 - A15 for x16 configuration.
2. Data DQ
0
- DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE
and BLE are applicable for x16 configuration only.

Functional Description

■ 20 ns, 25 ns, and 45 ns Access Times
(CY14B101NA)
■ Hands off Automatic STORE on power down with only a small
Capacitor
■ STORE to QuantumTrap
Software, device pin, or AutoStore
■ RECALL to SRAM initiated by software or power up
■ Infinite Read, Write, and Recall Cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20% to -10% operation
■ Commercial and Industrial Temperatures
■ 48-ball FBGA, 44-pin TSOP - II, 48-pin SSOP, and 32-pin SOIC
®
nonvolatile elements initiated by
®
on power down
packages
■ Pb-free and RoHS compliance
The Cypress CY14B101LA/CY14B101NA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 128K bytes of 8 bits each or 64K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 001-42879 Rev. *B Revised January 29, 2009
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Pinouts

WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
NC
A
2
A
1
NC
V
CC
DQ
4
NC
DQ
5
DQ
6
NC
DQ
7
NC
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC NC
DQ
1
48-FBGA
(not to scale)
Top View
(x8)
[6]
[7]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
BHE
NC
NC
A
2
A
1
BLE
V
CC
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
NC
NC
NC
DQ
11
48-FBGA
(not to scale)
Top View
(x16)
[6]
[7]
[4]
[5]
[4]
[5]
NC
A
8
NC NC
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
NC
NC
NC
1 2
3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18
19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A
10
NC
WE
DQ
7
HSB
NC
V
SS
V
CC
V
CAP
NC
(x8)
[6]
[7]
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
NC
NC
1 2
3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18
19 20
21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
WE
DQ
7
A
0
V
SS
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
(x16)
44-TSOP II
(x8)
44-TSOP II
(x16)
[8]
[4]
[5]
[4]
[5]
Notes
4. Address expansion for 2 Mbit. NC pin not connected to die.
5. Address expansion for 4 Mbit. NC pin not connected to die.
6. Address expansion for 8 Mbit. NC pin not connected to die.
7. Address expansion for 16 Mbit. NC pin not connected to die.
8. HSB
pin is not available in 44-TSOP II (x16) package.
Figure 1. Pin Diagram - 48 FBGA
Figure 2. Pin Diagram - 44 Pin TSOP II
Document #: 001-42879 Rev. *B Page 2 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Pinouts (continued)
NC
A
8
NC NC
V
SS
DQ6
DQ5 DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
NC
NC
NC
1
2 3 4
5
6 7 8 9
10 11 12 13 14 15 16 17 18
19
20 21 22
23 24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Top View
(not to scale)
A
10
NC
WE
DQ7
HSB
INT
V
SS
V
CC
V
CAP
NC
45
46
47
48
NC
NC
NC
NC
48-SSOP
Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC
Table 1. Pin Definitions
Pin Name I/O Type Description
– A
A
0
– A
A
0
– DQ
DQ
0
DQ0 – DQ
WE
16
15
7
Input/Output
15
Input
Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
Address Inputs Used to Select one of the 131,072 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
to the specific address location.
CE
OE
BHE
BLE
V
SS
V
CC
[8]
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Document #: 001-42879 Rev. *B Page 3 of 25
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
HIGH.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground Ground for the Device. Must be connected to the ground of the system.
Power
Power Supply Inputs to the Device. 3.0V +20%, –10%
Supply
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
Power
Supply
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is driven HIGH for short time with standard output high current.
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Device Operation

0.1uF
Vcc
10kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
The CY14B101LA/CY14B101NA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B101LA/CY14B101NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. Refer to the Truth Table For SRAM Operations on page 15 for a complete description of read and write modes.

SRAM Read

The CY14B101LA/CY14B101NA performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address specified on pins A data bytes or 65,536 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of t (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at t data output repeatedly responds to address changes within the
ACE
tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0-16
or at t
or A
DOE
determines which of the 131,072
0-15
, whichever is later (read cycle 2). The
AA
Figure 4 shows the proper connection of the storage capacitor
(V
) for automatic STORE operation. Refer to DC Electrical
CAP
Characteristics on page 7 for the size of V
the V pull up on WE only effective if the WE
pin is driven to V
CAP
to hold it inactive during power up. This pull up is
by a regulator on the chip. Place a
CC
signal is tri-state during power up. Many
. The voltage on
CAP
MPUs tri-state their controls on power up. This must be verified when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE
held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB
signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE
or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ are written into the memory if the data is valid tSD before the end of a WE write. The Byte Enable inputs (BHE are written, in the case of 16-bit words. Keep OE
-controlled write or before the end of a CE-controlled , BLE) determine which bytes
HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE buffers t
is left LOW, internal circuitry turns off the output
after WE goes LOW.
HZWE

AutoStore Operation

The CY14B101LA/CY14B101NA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by HSB; address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from V charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below V automatically disconnects the V operation is initiated with power provided by the V
Software STORE activated by an
pin. This stored
CAP
, the part
pin from VCC. A STORE
CAP
SWITCH
CAP
capacitor.
0–15
CC

Hardware STORE Operation

The CY14B101LA/CY14B101NA provides the HSB control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101LA/CY14B101NA conditionally initiates a STORE operation after t only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated. After HSB CY14B101LA/CY14B101NA continues SRAM operations for
. However, any SRAM write cycles requested after HSB
t
DELAY
goes LOW are inhibited until HSB returns HIGH. If the write latch is not set, HSB
to
CY14B101LA/CY14B101NA, but any SRAM read/write cycles are inhibited until HSB
is not driven low by the
is returned HIGH by MPU or another
external source.
. An actual STORE cycle
DELAY
goes LOW, the
[8]
pin to
Document #: 001-42879 Rev. *B Page 4 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
During any STORE operation, regardless of how it is initiated,
Notes
9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A
14
- A2) are used to control software modes.
Rest of the address lines are don’t care.
10. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
the CY14B101LA/CY14B101NA continues to drive the HSB
pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B101LA/CY14B101NA remains disabled until the HSB returns HIGH. Leave the HSB
unconnected if it is not used.
pin

Hardware RECALL (Power Up)

During power up or after any low power condition (V
CC<VSWITCH
V
again exceeds the sense voltage of V
CC
cycle is automatically initiated and takes t During this time, HSB
), an internal RECALL request is latched. When
, a RECALL
SWITCH
is driven low by the HSB driver.
HRECALL
to complete.

Software STORE

Data is transferred from SRAM to the nonvolatile memory by a software address sequence. The CY14B101LA/CY14B101NA Software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 2. Mode Selection
The software sequence may be clocked with CE
controlled reads. After the sixth address in the sequence
or OE
controlled reads
is entered, the STORE cycle commences and the chip is disabled. HSB
is driven low. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the t fulfilled, the SRAM is activated again for the read and write
STORE
cycle time is
operation.

Software RECALL

Data is transferred from nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the t ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
controlled read operations must be
cycle time, the SRAM is again
RECALL
CE WE OE, BHE, BLE
[3]
A15 - A
[9]
0
Mode I/O Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F 0x8B45
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
AutoStore
Disable
Document #: 001-42879 Rev. *B Page 5 of 25
Output Data Output Data Output Data Output Data Output Data Output Data
Active
[10]
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Table 2. Mode Selection (continued)
CE WE OE, BHE, BLE
[3]
L H L 0x4E38
L H L 0x4E38
L H L 0x4E38

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
0xB1C7
0x83E0
0x7C1F
0x703F 0x4B46
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
[9]
0
Mode I/O Power
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
AutoStore Enable
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
Nonvolatile
Output Data Output Data Output Data Output Data Output Data Output Data
Output Data Output Data Output Data Output Data Output Data
Output High Z
Active I
A15 - A
STORE
Output Data Output Data Output Data Output Data Output Data
Output High Z
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM
Nonvolatile
Recall

Data Protection

The CY14B101LA/CY14B101NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when V CY14B101LA/CY14B101NA is in a write mode (both CE
is less than V
CC
SWITCH
are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after t active). This protects against inadvertent writes during power up
LZHSB
or brown out conditions.

Noise Considerations

Refer to CY application note AN1064.
[10]
Active
[10]
CC2
[10]
Active
. If the
and WE
(HSB to output
Document #: 001-42879 Rev. *B Page 6 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Maximum Ratings

Notes
11. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V
CC
= 3V. Not 100% tested.
12. The HSB
pin has I
OUT
= -2 uA for VOH of 2.4V when both active high and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
13. V
CAP
(Storage capacitor) nominal value is 68 uF.
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Maximum Accumulated Storage Time:
At 150°C Ambient Temperature ........................1000h
At 85°C Ambient Temperature..................... 20 Years
Ambient Temperature with Power Applied.. –55°C to +150°C
Supply Voltage on V
Voltage Applied to Outputs in High-Z State–0.5V to V
Input Voltage.............................................–0.5V to Vcc+0.5V
Relative to GND ..........–0.5V to 4.1V
CC
CC
+ 0.5V
Package Power Dissipation Capability (T
= 25°C) ...................................................1.0W
A
Surface Mount Pb Soldering
Temperature (3 Seconds).......................................... +260°C
DC Output Current (1 output at a time, 1s duration)......15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA

Operating Range

Range Ambient Temperature V
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial –40°C to +85°C 2.7V to 3.6V
CC
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to V
+ 2.0V
CC

DC Electrical Characteristics

Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter Description Test Conditions Min Max Unit
I
CC1
I
CC2
I
CC3
I
CC4
I
SB
[11]
Average VCC Current tRC = 20 ns
t
RC
t
RC
Values obtained without output loads (I
Average VCC Current during STORE
Average VCC Current at t
= 200 ns, 3V, 25°C
RC
typical
Average V during AutoStore Cycle
CAP
Current
All Inputs Don’t Care, VCC = Max Average current for duration t
All I/P cycling at CMOS levels. Values obtained without output loads (I
All Inputs Don’t Care, VCC = Max Average current for duration t
VCC Standby Current CE > (VCC – 0.2V). All others V
current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz
I
I
V
V
V
V
V
IX
OZ
IH
IL
OH
OL
CAP
[12]
Input Leakage Current (except HSB
)
Input Leakage Current (for HSB
)
Off-State Output Leakage Current
Input HIGH Voltage 2.0 VCC+0.5 V
Input LOW Voltage Vss–0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I
[13]
Storage Capacitor Between V
V
CC
V
CC
VCC = Max, VSS < V
or WE < V
OUT
OUT
Commercial 65 = 25 ns = 45 ns
OUT
= 0 mA)
Industrial 70
65 50
70 52
10 mA
STORE
35 mA
= 0 mA)
OUT
5mA
STORE
= Max, VSS < V
= Max, VSS < V
IL
< 0.2V or > (VCC – 0.2V). Standby
IN
< V
IN
CC
< V
IN
CC
< VCC, CE or OE > V
OUT
or BHE/BLE > V
IH
–1 +1 µA
–100 +1 µA
–1 +1 µA
IH
5mA
= –2 mA 2.4 V
= 4 mA 0.4 V
pin and VSS, 5V Rated 61 180 µF
CAP
mA mA mA
mA mA mA
Document #: 001-42879 Rev. *B Page 7 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Data Retention and Endurance

3.0V
OUTPUT
5 pF
R1
R2
789Ω
3.0V
OUTPUT
30 pF
R1
R2
789Ω
for tri-state specs
577Ω
577Ω
Note
14. These parameters are guaranteed by design and are not tested.
Parameter Description Min Unit
DATA
NV
C
R
Data Retention 20 Years
Nonvolatile STORE Operations 200 K

Capacitance

Parameter
C
IN
C
OUT
[14]
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF
Description Test Conditions Max Unit
= 0 to 3.0V
V
CC
7pF

Thermal Resistance

Parameter
Θ
JA
Θ
JC
[14]
Description Test Conditions 48-FBGA 48-SSOP 44-TSOP II 32-SOIC Unit
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.
Figure 5. AC Test Loads
28.82 TBD 31.11 TBD °C/W
7.84 TBD 5.56 TBD °C/W

AC Test Conditions

Input Pulse Levels.................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <
Input and Output Timing Reference Levels.................... 1.5V
Document #: 001-42879 Rev. *B Page 8 of 25
3 ns
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

AC Switching Characteristics

Address
Data Output
Address Valid
Previous Data Valid
Output Data Valid
t
RC
t
AA
t
OHA
Notes
15. WE
must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE
, OE and BHE / BLE LOW.
17. Measured ±200 mV from steady state output voltage.
18. If WE
is low when CE goes low, the outputs remain in the high impedance state.
19. HSB
must remain HIGH during READ and WRITE cycles.
Parameters
Cypress
Parameters
Alt
Parameters
SRAM Read Cycle
t
ACE
t
RC
t
AA
t
DOE
t
OHA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
PU
t
PD
t
DBE[
t
LZBE
t
HZBE
[15]
[16]
[16]
[14]
[14]
[14]
[14, 17]
[14, 17]
[14, 17]
[14, 17]
[14]
[14]
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
- Byte Enable to Data Valid 10 12 20 ns
- Byte Enable to Output Active 0 0 0 ns
- Byte Disable to Output Inactive 8 10 15 ns
Chip Enable Access Time 20 25 45 ns Read Cycle Time 20 25 45 ns
Address Access Time 20 25 45 ns
Output Enable to Data Valid 10 12 20 ns
Output Hold After Address Change 3 3 3 ns
Chip Enable to Output Active 3 3 3 ns
Chip Disable to Output Inactive 8 10 15 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 8 10 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 20 25 45 ns
SRAM Write Cycle
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
t
HZWE
t
LZWE
t
BW
[14, 17,18]
[14, 17]
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
- Byte Enable to End of Write 15 20 30 ns
Write Cycle Time 20 25 45 ns Write Pulse Width 15 20 30 ns Chip Enable To End of Write 15 20 30 ns Data Setup to End of Write 8 10 15 ns Data Hold After End of Write 0 0 0 ns Address Setup to End of Write 15 20 30 ns Address Setup to Start of Write 0 0 0 ns Address Hold After End of Write 0 0 0 ns Write Enable to Output Disable 8 10 15 ns
Output Active after End of Write 3 3 3 ns
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled
Description
20 ns 25 ns 45 ns
Min Max Min Max Min Max
[15, 16, 19]
Unit
Document #: 001-42879 Rev. *B Page 9 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Note
21. CE
or WE must be > VIH during address transitions.
CE
Data Output
Data Input
Input Data Valid
High Impedance
Address ValidAddress
Previous Data
t
WC
t
SCE
t
HA
t
BW
t
AW
t
PWE
t
SA
t
SD
t
HD
t
HZWE
t
LZWE
WE
BHE, BLE
CE
OE
BHE, BLE
Data Output
I
CC
Figure 7. SRAM Read Cycle #2: CE and OE Controlled
Address ValidAddress
t
RC
t
ACE
t
AA
t
LZCE
t
DOE
t
LZOE
t
DBE
t
LZBE
High Impedance
t
PU
Standby
Active
[3, 15, 19]
t
HZCE
t
HZOE
t
HZBE
Output Data Valid
t
PD
Figure 8. SRAM Write Cycle #1: WE Controlled
[3, 18, 19, 21]
Document #: 001-42879 Rev. *B Page 10 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Figure 9. SRAM Write Cycle #2: CE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input
Input Data Valid
High Impedance
Address ValidAddress
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
Controlled
[3, 18, 19, 21]
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled
Document #: 001-42879 Rev. *B Page 11 of 25
[3, 18, 19, 21]
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

AutoStore/Power Up RECALL

V
SWITCH
V
HDIS
V
VCCR ISE
t
STORE
t
STORE
t
HHHD
t
HHHD
t
DELAY
t
DELAY
t
LZHSB
t
LZHSB
t
HRECALL
t
HRECALL
HSB OUT
Autostore
POWER-
UP
RECALL
Read & Write
Inhibited
(
RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
Autostore
POWER-UP
RECALL
Read & Write
POWER
DOWN
Autostore
Note
23
Note
23
Note
26
Notes
22. t
HRECALL
starts from the time VCC rises above V
SWITCH.
23. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
24. On a Hardware STORE, Software STORE / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
26. HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Parameters Description
[27]
t
HRECALL
t
STORE
t
DELAY
V
SWITCH
t
VCCRISE
V
HDIS
t
LZHSB
t
HHHD
Power Up RECALL Duration 20 20 20 ms
[23]
STORE Cycle Duration 8 8 8 ms
[24]
Time Allowed to Complete SRAM Cycle 20 25 25 ns
Low Voltage Trigger Level 2.65 2.65 2.65 V
VCC Rise Time 150 150 150 µs
[14]
HSB Output Driver Disable Voltage 1.9 1.9 1.9 V
HSB To Output Active Time 5 5 5 µs HSB High Active Time 500 500 500 ns
Switching Waveforms
20 ns 25 ns 45 ns
Min Max Min Max Min Max
Figure 11. AutoStore or Power Up RECALL
Unit
[27]
Document #: 001-42879 Rev. *B Page 12 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Software Controlled STORE/RECALL Cycle

t
RC
t
RC
t
SA
t
CW
t
CW
t
SA
t
HA
t
LZCE
t
HZCE
t
HA
t
HA
t
HA
t
DELAY
t
STORE/tRECALL
t
HHHD
t
LZHSB
High Impedance
Address #1 Address #6Address
CE
OE
HSB(STOREonly)
DQ (DATA)
RWI
Notes
27. The software sequence is clocked with CE
controlled or OE controlled reads.
28. The six consecutive addresses must be read in the order listed in Table 2 on page 5. WE
must be HIGH during all six consecutive cycles.
Parameters
t
RC
t
SA
t
CW
t
HA
t
RECALL
[27, 28]
Description
STORE/RECALL Initiation Cycle Time 20 25 45 ns
Address Setup Time 0 0 0 ns
Clock Pulse Width 15 20 30 ns
Address Hold Time 0 0 0 ns
RECALL Duration 200 200 200 µs
Switching Waveforms
20 ns 25 ns 45 ns
Min Max Min Max Min Max
Unit
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
Figure 13. Autostore Enable / Disable Cycle
t
RC
Address #1 Address #6Address
t
SA
t
CW
t
RC
t
CW
[28]
CE
OE
DQ (DATA)
t
SA
t
LZCE
t
t
t
HZCE
HA
HA
Document #: 001-42879 Rev. *B Page 13 of 25
t
HA
t
DELAY
t
HA
t
SS
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Hardware STORE Cycle

t
PHSB
t
PHSB
t
DELAY
t
DHSB
t
DELAY
t
STORE
t
HHHD
t
LZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to V
CC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low.
HSB driver is disabled
t
DHSB
100kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
t
SS
t
SS
CE
Address
V
CC
t
SA
t
CW
Soft Sequence
Command
t
CW
Parameters Description
t
DHSB
t
PHSB
t
SS
[29, 30]
HSB To Output Active Time when write latch not set 20 25 25 ns
Hardware STORE Pulse Width 15 15 15 ns
Soft Sequence Processing Time 100 100 100 μs
20ns 25ns 45ns
Min Max Min Max Min Max
Unit
Switching Waveforms
Figure 14. Hardware STORE Cycle
[23]
Notes
29. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
30. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-42879 Rev. *B Page 14 of 25
Figure 15. Soft Sequence Processing
[29, 30]
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Truth Table For SRAM Operations

HSB must remain HIGH for SRAM operations.
Table 3. Truth Table for x8 Configuration
CE WE OE Inputs/Outputs
H X X High Z Deselect/Power down Standby
L H L Data Out (DQ
–DQ7); Read Active
0
L H H High Z Output Disabled Active
L L X Data in (DQ
–DQ7); Write Active
0
Table 4. Truth Table for x16 Configuration
CE WE OE BHE BLE Inputs/Outputs
H X X X X High-Z Deselect/Power down Standby
L X X H H High-Z Output Disabled Active
L H L L L Data Out (DQ
L H L H L Data Out (DQ
L H L L H Data Out (DQ
L H H L L High-Z Output Disabled Active
L H H H L High-Z Output Disabled Active
L H H L H High-Z Output Disabled Active
L L X L L Data In (DQ
L L X H L Data In (DQ
L L X L H Data In (DQ
[2]
DQ
–DQ
8
–DQ7 in High-Z
DQ
0
DQ
–DQ
8
DQ
–DQ7 in High-Z
0
Mode Power
[2]
–DQ15) Read Active
0
–DQ7);
0
in High-Z
15
–DQ15);
8
–DQ15) Write Active
0
–DQ7);
0
in High-Z
15
–DQ15);
8
Read Active
Read Active
Write Active
Write Active
Mode Power
Document #: 001-42879 Rev. *B Page 15 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Ordering Information

Speed
(ns)
20 CY14B101LA-ZS20XCT 51-85087 44-pin TSOP II Commercial
CY14B101LA-ZS20XC 51-85087 44-pin TSOP II
CY14B101LA-BA20XCT 51-85128 48-ball FBGA
CY14B101LA-BA20XC 51-85128 48-ball FBGA
CY14B101LA-SP20XCT 51-85061 48-pin SSOP
CY14B101LA-SP20XC 51-85061 48-pin SSOP
CY14B101LA-SZ20XCT 51-85127 32-pin SOIC
CY14B101LA-SZ20XC 51-85127 32-pin SOIC
CY14B101NA-ZS20XCT 51-85087 44-pin TSOP II
CY14B101NA-ZS20XC 51-85087 44-pin TSOP II
CY14B101NA-BA20XCT 51-85128 48-ball FBGA
CY14B101NA-BA20XC 51-85128 48-ball FBGA
CY14B101LA-ZS20XIT 51-85087 44-pin TSOP II Industrial
CY14B101LA-ZS20XI 51-85087 44-pin TSOP II
CY14B101LA-BA20XIT 51-85128 48-ball FBGA
CY14B101LA-BA20XI 51-85128 48-ball FBGA
CY14B101LA-SP20XIT 51-85061 48-pin SSOP
CY14B101LA-SP20XI 51-85061 48-pin SSOP
CY14B101LA-SZ20XIT 51-85127 32-pin SOIC
CY14B101LA-SZ20XI 51-85127 32-pin SOIC
CY14B101NA-ZS20XIT 51-85087 44-pin TSOP II
CY14B101NA-ZS20XI 51-85087 44-pin TSOP II
CY14B101NA-BA20XIT 51-85128 48-ball FBGA
CY14B101NA-BA20XI 51-85128 48-ball FBGA
Ordering Code
Package Diagram
Package Type
Operating
Range
Document #: 001-42879 Rev. *B Page 16 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Ordering Information (continued)
Speed
(ns)
25 CY14B101LA-ZS25XCT 51-85087 44-pin TSOP II Commercial
CY14B101LA-ZS25XC 51-85087 44-pin TSOP II
CY14B101LA-BA25XCT 51-85128 48-ball FBGA
CY14B101LA-BA25XC 51-85128 48-ball FBGA
CY14B101LA-SP25XCT 51-85061 48-pin SSOP
CY14B101LA-SP25XC 51-85061 48-pin SSOP
CY14B101LA-SZ25XCT 51-85127 32-pin SOIC
CY14B101LA-SZ25XC 51-85127 32-pin SOIC
CY14B101NA-ZS25XCT 51-85087 44-pin TSOP II
CY14B101NA-ZS25XC 51-85087 44-pin TSOP II
CY14B101NA-BA25XCT 51-85128 48-ball FBGA
CY14B101NA-BA25XC 51-85128 48-ball FBGA
CY14B101LA-ZS25XIT 51-85087 44-pin TSOP II Industrial
CY14B101LA-ZS25XI 51-85087 44-pin TSOP II
CY14B101LA-BA25XIT 51-85128 48-ball FBGA
CY14B101LA-BA25XI 51-85128 48-ball FBGA
CY14B101LA-SP25XIT 51-85061 48-pin SSOP
CY14B101LA-SP25XI 51-85061 48-pin SSOP
CY14B101LA-SZ25XIT 51-85127 32-pin SOIC
CY14B101LA-SZ25XI 51-85127 32-pin SOIC
CY14B101NA-ZS25XIT 51-85087 44-pin TSOP II
CY14B101NA-ZS25XI 51-85087 44-pin TSOP II
CY14B101NA-BA25XIT 51-85128 48-ball FBGA
CY14B101NA-BA25XI 51-85128 48-ball FBGA
Ordering Code
Package Diagram
Package Type
Operating
Range
Document #: 001-42879 Rev. *B Page 17 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Ordering Information (continued)
Speed
(ns)
45 CY14B101LA-ZS45XCT 51-85087 44-pin TSOP II Commercial
CY14B101LA-ZS45XC 51-85087 44-pin TSOP II
CY14B101LA-BA45XCT 51-85128 48-ball FBGA
CY14B101LA-BA45XC 51-85128 48-ball FBGA
CY14B101LA-SP45XCT 51-85061 48-pin SSOP
CY14B101LA-SP45XC 51-85061 48-pin SSOP
CY14B101LA-SZ45XCT 51-85127 32-pin SOIC
CY14B101LA-SZ45XC 51-85127 32-pin SOIC
CY14B101NA-ZS45XCT 51-85087 44-pin TSOP II
CY14B101NA-ZS45XC 51-85087 44-pin TSOP II
CY14B101NA-BA45XCT 51-85128 48-ball FBGA
CY14B101NA-BA45XC 51-85128 48-ball FBGA
CY14B101LA-ZS45XIT 51-85087 44-pin TSOP II Industrial
CY14B101LA-ZS45XI 51-85087 44-pin TSOP II
CY14B101LA-BA45XIT 51-85128 48-ball FBGA
CY14B101LA-BA45XI 51-85128 48-ball FBGA
CY14B101LA-SP45XIT 51-85061 48-pin SSOP
CY14B101LA-SP45XI 51-85061 48-pin SSOP
CY14B101LA-SZ45XIT 51-85127 32-pin SOIC
CY14B101LA-SZ45XI 51-85127 32-pin SOIC
CY14B101NA-ZS45XIT 51-85087 44-pin TSOP II
CY14B101NA-ZS45XI 51-85087 44-pin TSOP II
CY14B101NA-BA45XIT 51-85128 48-ball FBGA
CY14B101NA-BA45XI 51-85128 48-ball FBGA
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Ordering Code
Package Diagram
Package Type
Operating
Range
Document #: 001-42879 Rev. *B Page 18 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Part Numbering Nomenclature

Option: T - Tape & Reel Blank - Std.
Speed:
20 - 20 ns
25 - 25 ns
Data Bus: L - x8
N - x16
Density: 101 - 1 Mb
Voltage: B - 3.0V
Cypress
CY 14 B 101L A-ZS 20 X C T
NVSRAM
14 - AutoStore + Software STORE + Hardware STORE
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Package:
BA - 48 FBGA
ZS - TSOP II
45 - 45 ns
SP - 48 SSOP SZ - 32 SOIC
Die revision: Blank: No Rev
A - 1
st
Rev
Document #: 001-42879 Rev. *B Page 19 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Package Diagrams

MAX MIN.
DIMENSION IN MM (INCH)
11.938 (0.470)
PLANE
SEATING
PIN 1 I.D.
44
1
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
EJECTOR PIN
R
G
OKE
A
X
S
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
BASE PLANE
0.10 (.004)
22
23
TOP VIEW BOTTOM VIEW
51-85087-*A
Figure 16. 44-Pin TSOP II (51-85087)
Document #: 001-42879 Rev. *B Page 20 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Package Diagrams (continued)
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
10.00±0.10
A
10.00±0.10
6.00±0.10
B
1.875
2.625
0.36
51-85128-*D
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
Document #: 001-42879 Rev. *B Page 21 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Package Diagrams (continued)
51-85061 *C
Figure 18. 48-Pin SSOP (51-85061)
Document #: 001-42879 Rev. *B Page 22 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA
Package Diagrams (continued)
Figure 19. 32-Pin SOIC (51-85127)
Document #: 001-42879 Rev. *B Page 23 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Document History Page

Document Title: CY14B101LA/CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Document Number: 001-42879
Rev. ECN No.
Submission
Date
** 2050747 See ECN UNC/PYRS New Data Sheet
*A 2607447 11/14/2008 GVCH/AESA Removed 15 ns access speed
*B 2654484 02/05/09 GVCH/PYRS Changed the data sheet from Advance information to Preliminary
Orig. of Change
Description of Change
Updated “Features” Updated Logic block diagram Added footnote 1 2, 3 and 7 Pin definition: Updated WE
, HSB and NC pin description Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description Updated Figure 4 Page 4: Updated Hardware store operation and Hardware RECALL (Power up)description Page 4: Updated Software store and software recall description Footnote 1 and 11 referenced for Mode selection Table Added footnote 11 Updated footnote 9 and 10 Page 6: updated Data protection description Maximum Ratings:Added Max. Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed I Changed I Changed I Changed I Added I Updated I Changed V Added V Updated footnote 12 and 13
from 6mA to 10mA
CC2
from 15mA to 35mA
CC3
from 6mA to 5mA
CC4
from 3mA to 5mA
SB
for HSB
IX
CC1, ICC3, ISB
voltage min value from 68uF to 61uF
CAP
voltage max value to 180uF
CAP
and I
Test conditions
OZ
Added footnote 14 Added Data retention and Endurance Table Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages Updated Input Rise and Fall time in AC test Conditions Referenced footnote 17 to t Updated All switching waveforms
parameter
OHA
Updated footnote 17 Added footnote 20 Added Figure 10 (SRAM WRITE CYCLE:BHE Changed t Updated t Added V Updated footnote 24
HDIS
max value from 12.5ms to 8ms
STORE
value
DELAY
, t
HHHD
and t
LZHSB
parameters
and BLE controlled)
Added footnote 26 and 27 Software controlled STORE/RECALL Table: Changed t Changed t Changed t Added Figure 13 Added t Changed t
DHSB
Updated tSS from 70us to 100us
to t
GHAX HA
HA
value from 1ns to 0 ns
parameter
to t
HLHX
PHSB
AS
to t
Added truth table for SRAM operations Updated ordering information and part numbering nomenclature
, t
Referenced Note 15 to parameters t Updated Figure 12
LZCE
, t
HZCE
LZOE, tHZOE, tLZWE
SA
and t
HZWE
Document #: 001-42879 Rev. *B Page 24 of 25
[+] Feedback
PRELIMINARY
CY14B101LA, CY14B101NA

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-42879 Rev. *B Revised January 29, 2009 Page 25 of 25
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use