CY14B101L
1 Mbit (128K x 8) nvSRAM
Features
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
1024 X 1024
QuantumTrap
1024 x 1024
STORE
RECALL
COLUMN IO
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
15
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with STK14CA8
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited READ, WRITE, and RECALL cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention at 55°C
■
Single 3V +20%, –10% operation
■
Commercial and industrial temperature
■
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
■
RoHS compliance
Functional Description
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06400 Rev. *I Revised January 30, 2009
[+] Feedback
CY14B101L
Pinouts
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
V
CC
A
15
HSB
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
7
DQ
6
DQ
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
V
SS
DQ
2
DQ
3
DQ
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
NC
DQ7
DQ6
DQ5
NC
DQ4
V
CC
DQ3
DQ2
DQ1
DQ0
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
NC
HSB
WE
NC
NC
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Top View
(not to scale)
OE
CE
V
CC
V
SS
V
CAP
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Pin Definitions
Pin Name Alt IO Type Description
A
0–A16
DQ
-DQ
0
7
WE
CE
OE
V
V
SS
CC
W
E
G
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Document Number: 001-06400 Rev. *I Page 2 of 18
Input Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
Input or Output Bidirectional Dat a IO Lines. Used as input or output lines depending on operation.
Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Input Chip Enable Input, Active LOW . When LOW , selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE
HIGH causes the IO pins to tri-state.
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
[+] Feedback
CY14B101L
Device Operation
The CY14B101L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
When the READ is initiated by an address transition, the outputs
are valid after a delay of t
initiated by CE
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the t
the need for transitions on any control input pins, and remains
valid until another address change or until CE or OE is brought
HIGH, or WE
determines the 131,072 data bytes accessed.
0–16
(READ cycle 1). If the READ is
or OE, the outputs are valid at t
AA
or at t
ACE
access time without
AA
or HSB is brought LOW.
DOE
Figure 2 shows the proper connection of the storage capacitor
(V
) for automatic store operation. Refer to the D C Electrical
CAP
Characteristics on page 7 for the size of V
the V
A pull up is placed on WE
pin is driven to 5V by a charge pump internal to the chip.
CAP
to hold it inactive during power up.
. The voltage on
CAP
Figure 2. AutoStore Mode
V
CAP
CAP
V
V
WE
CC
10k Ohm
,
V
CC
U
0.1 F
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
is HIGH. The address inputs must be stable prior to entering
HSB
the WRITE cycle and must remain stable until either CE
or WE
goes HIGH at the end of the cycle.
The data on the common IO pins DQ
memory if it has valid t
WRITE or before the end of an CE
, before the end of a WE controlled
SD
controlled WRITE. Keep OE
are written into the
0–7
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE
the output buffers t
is left LOW , internal circuitry turns of f
after WE goes LOW.
HZWE
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
pin drops below V
CC
pin from VCC. A STORE
CAP
pin. This stored
CAP
SWITCH
capacitor.
CAP
to
CC
, the part
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB
signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
LOW, the CY14B101L conditionally initiates a STORE operation
after t
the SRAM takes place since the last STORE or RECALL cycle.
. An actual STORE cycle only begins if a WRITE to
DELAY
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB
is driven LOW by any means, are given time to comple te
before the STORE operation is initiated. After HSB
the CY14B101L continues SRAM operations for t
, multiple SRAM READ operations take place. If a WRITE
t
DELAY
is in progress when HSB
is pulled LOW, it allows a time, t
to complete. However, any SRAM WRITE cycles requested after
goes LOW are inhibited until HSB returns HIGH.
HSB
If HSB
is not used, it is left unconnected.
pin is used to
pin is driven
goes LOW,
. During
DELAY
DELAY
.
Document Number: 001-06400 Rev. *I Page 3 of 18
[+] Feedback
CY14B101L
Hardware RECALL (Power Up)
Data Protection
During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When V
SWITCH
SWITCH
HRECALL
, a RECALL
to complete.
CC
Software ST ORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x8FC0, Initiate STORE cycle
The software sequence is clocked with CE
OE
controlled READs. When the sixth address in the sequence
controlled READs or
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE
a valid sequence. After the t
SRAM is again activated for READ and WRITE operation.
cycle time is fulfilled, the
STORE
is LOW for
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x4C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
controlled READ operations is
cycle time, the SRAM is once
RECALL
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
If the CY14B101L is in a WRITE mode (both CE
is less than V
CC
SWITCH
.
and WE are low)
at power up after a RECALL or after a STORE, the WRITE is
inhibited until a negative transition on CE
or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The CY14B101L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
CC
and V
using leads and traces that are as short
SS,
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the CY14B101L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B101L depends on the
following items:
■
The duty cycle of chip enable
■
The overall cycle rate for accesses
■
The ratio of READs to WRITEs
■
CMOS versus TTL input levels
■
The operating temperature
■
The VCC level
■
IO loading
Figure 3. Current Versus Cycle Time
Document Number: 001-06400 Rev. *I Page 4 of 18
[+] Feedback
CY14B101L
Preventing Store
Best Practices
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE
controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of
controlled READ operations:
CE
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on must always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■
If autostore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.
■
The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum V
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger V
to make sure there is extra store charge should discuss their
V
CAP
the Vcap voltage level at the end of a t
value specified in this data sheet includes a minimum
CAP
value because
CAP
value
CAP
size selection with Cypress to understand any impact on
period.
RECALL
Document Number: 001-06400 Rev. *I Page 5 of 18
[+] Feedback
CY14B101L
.
Notes
1. The six consecutive address locations are in the order listed. WE
is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
3. IO state depends on the state of OE
. The IO table shown is based on OE Low.
Table 1. Hardware Mode Selection
CE WE OE
A15 – A
0
Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
LHL0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
LHL0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
LHL0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
LHL0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
Active
Active
Active
[1, 2, 3]
[1, 2, 3]
CC2
[1, 2, 3]
[3]
[1, 2, 3]
Document Number: 001-06400 Rev. *I Page 6 of 18
[+] Feedback
CY14B101L
Maximum Ratings
Notes
4. The HSB
pin has I
OUT
= –10 μA for VOH of 2.4 V. This parameter is characterized but not tested.
5. V
IH
changes by 100 mV when VCC > 3.5V.
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage on V
Voltage Applied to Outputs
in High Z State.......................................–0.5V to V
Input Voltage..................... ......................–0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential..................–2.0V to V
Relative to GND..........–0.5V to 4.1V
CC
CC
CC
+ 0.5V
+ 2.0V
Package Power Dissipation
Capability (T
= 25°C) ...................................................1.0W
A
Surface Mount Lead Soldering
Temperature (3 Seconds)..........................................+260°C
DC output Current (1 output at a time, 1s duration) ....15 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial -40°C to +85°C 2.7V to 3.6V
CC
DC Electrical Characteristics
Over the operating range (VCC = 2.7V to 3.6V)
[4, 5]
Parameter Description Test Conditions Min Max Unit
I
CC1
I
CC2
I
CC3
I
CC4
I
SB
Average VCC Current tRC = 25 ns
t
= 35 ns
RC
= 45 ns
t
RC
Dependent on output loading and cycle rate.
V alues obtained without output loads.
I
= 0 mA.
OUT
Average VCC Current
during STORE
Average VCC Current at
t
= 200 ns, 5V, 25°C
RC
Typical
Average V
during AutoStore Cycle
CAP
Current
All Inputs Do Not Care, VCC = Max
Average current for duration t
> (VCC – 0.2V). All other inputs cycling.
WE
STORE
Dependent on output loading and cycle rate. Values obtained
without output loads.
All Inputs Do Not Care, VCC = Max
Average current for duration t
STORE
VCC Standby Current CE > (VCC – 0.2V). All others V
Standby current level after nonvolatile cycle is complete.
Commercial 65
Industrial 70
< 0.2V or > (VCC – 0.2V).
IN
55
50
60
55
6mA
10 mA
3mA
3mA
Inputs are static. f = 0 MHz.
I
I
V
V
V
V
V
IX
OZ
IH
IL
OH
OL
CAP
Input Leakage Current VCC = Max, VSS < V
Off State Output
VCC = Max, VSS < V
Leakage Current
< V
IN
CC
< VCC, CE or OE > V
IN
or WE < V
IH
-1 +1 μA
IL
-1 +1 μA
Input HIGH Voltage 2.0 VCC +
0.5
Input LOW Voltage VSS – 0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I
Storage Capacitor Between V
= –2 mA 2.4 V
OUT
= 4 mA 0.4 V
OUT
pin and Vss, 6V rated. 17 120 uF
CAP
mA
mA
mA
mA
mA
V
Document Number: 001-06400 Rev. *I Page 7 of 18
[+] Feedback
CY14B101L
Data Retention and Endurance
3.0V
Output
30 pF
R1 577Ω
R2
789Ω
3.0V
Output
5 pF
R1 577
Ω
R2
789
Ω
For Tri-state Specs
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% to 90%)...................... <
5 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
6. These parameters are guaranteed by design and are not tested.
Parameter Description Min Unit
DATA
NV
C
R
Data Retention at 55°C20Years
Nonvolatile STORE Operations 200 K
Capacitance
In the following table, the capacitance parameters are listed.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 0 to 3.0V
Output Capacitance 7 pF
CC
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter Description Test Conditions 32-SOIC 48-SSOP Unit
Θ
Θ
JA
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
Figure 4. AC Test Loads
[6]
7pF
[6]
33.64 32.9 °C/W
13.6 16.35 °C/W
AC Test Conditions
Document Number: 001-06400 Rev. *I Page 8 of 18
[+] Feedback
CY14B101L
AC Switching Characteristics
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Notes
7. WE
and HSB must be HIGH during SRAM READ cycles.
8. Device is continuously selected with CE
and OE both Low.
9. Measured ±200 mV from steady state output voltage.
10.HSB
must remain high during READ and WRITE cycles.
SRAM Read Cycle
Parameter
Cypress
Parameter
t
ACE
[7]
t
RC
[8]
t
AA
t
DOE
[8]
t
OHA
[9]
t
LZCE
[9]
t
HZCE
[9]
t
LZOE
[9]
t
HZOE
[6]
t
PU
[6]
t
PD
Alt
t
ELQV
t
AVAV, tELEH
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
t
ELICCH
t
EHICCL
Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 12 15 20 ns
Output Hold After Address Change 3 3 3 ns
Chip Enable to Output Active 3 3 3 ns
Chip Disable to Output Inactive 10 13 15 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
Description
25 ns 35 ns 45 ns
Min Max Min Max Min Max
[7, 8, 10]
Unit
Document Number: 001-06400 Rev. *I Page 9 of 18
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
[7, 10]
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CY14B101L
SRAM Write Cycle
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
11. If WE
is Low when CE goes Low, the outputs remain in the high impedance state.
12.
CE
or WE must be greater than VIH during address transitions.
Parameter
Cypress
Parameter
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
[9,11]
t
HZWE
[9]
t
LZWE
t
t
t
t
t
t
t
t
t
t
Alt
AVAV
WLWH, tWLEH
ELWH, tELEH
DVWH, tDVEH
WHDX, tEHDX
AVWH, tAVEH
AVWL, tAVEL
WHAX, tEHAX
WLQZ
WHQX
Switching Waveforms
25 ns 35 ns 45 ns
Description
Min Max Min Max Min Max
Unit
Write Cycle Time 25 35 45 ns
Write Pulse Width 20 25 30 ns
Chip Enable To End of Write 20 25 30 ns
Data Setup to End of Write 10 12 15 ns
Data Hold After End of Write 0 0 0 ns
Address Setup to End of Write 20 25 30 ns
Address Setup to Start of Write 0 0 0 ns
Address Hold After End of Write 0 0 0 ns
Write Enable to Output Disable 10 13 15 ns
Output Active After End of Write 3 3 3 ns
Figure 7. SRAM Write Cycle 1: WE Controlled
[11, 12]
Document Number: 001-06400 Rev. *I Page 10 of 18
Figure 8. SRAM Write Cycle 2: CE and OE Controlled
[11, 12]
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CY14B101L
AutoStore or Power Up RECALL
V
CC
V
SWITCH
t
STORE
t
STORE
t
HRECALL
t
HRECALL
AutoStore
POWER-UP RECALL
Read & Write Inhibited
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
t
VCCRISE
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below V
SWITCH
Notes
13.t
HRECALL
starts from the time VCC rises above V
SWITCH
.
14.If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
15.Industrial Grade devices requires 15 ms max.
Parameter Alt Description
t
HRECALL
t
STORE
V
SWITCH
t
VCCRISE
[13]
[14, 15]
t
RESTORE
t
HLHZ
Power up RECALL Duration 20 ms
STORE Cycle Duration 12.5 ms
Low Voltage Trigger Level 2.65 V
VCC Rise Time 150
Switching Waveforms
Figure 9. AutoStore/Power Up RECALL
CY14B101L
Min Max
Unit
μ
s
Document Number: 001-06400 Rev. *I Page 11 of 18
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CY14B101L
Software Controlled STORE/RECALL Cycle
t
RC
t
RC
t
SA
t
SCE
t
HA
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
t
RC
t
RC
6#SSERDDA1#SSERDDA
ADDRESS
t
SA
t
SCE
t
HA
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
HIGH IMPEDANCE
CE
OE
DQ (DATA)
Notes
16.The software sequence is clocked on the falling edge of CE
controlled READs or OE controlled READs.
17.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE
must be HIGH during all six consecutive cycles.
The software controlled STORE/RECALL cycle follows.
Parameter Alt Description
[17]
t
RC
t
SA
t
CW
t
HA
t
RECALL
t
AVAV
t
AVEL
t
ELEH
t
GHAX, tELAX
STORE/RECALL Initiation Cycle Time 25 35 45 ns
Address Setup Time 0 0 0 ns
Clock Pulse Width 20 25 30 ns
Address Hold Time 1 1 1 ns
RECALL Duration 120 120 120
[16, 17]
25 ns 35 ns 45 ns
Min Max Min Max Min Max
Unit
μ
s
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle
Figure 11. OE Controlled Software STORE/RECALL Cycle
[17]
[17]
Document Number: 001-06400 Rev. *I Page 12 of 18
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CY14B101L
Hardware STORE Cycle
3+6%
$GGUHVV $GGUHVV $GGUHVV $GGUHVV
6RIW6HTXHQFH
&RPPDQG
W
66
W
66
&(
$GGUHVV
9
&&
W
6$
W
&:
6RIW6HTXHQFH
&RPPDQG
W
&:
Notes
18.On a hardware STORE initiation, SRAM operation continues to be enabled for time t
DELAY
to allow read and write cycles to complete.
19.This is the amount of time to take action on a soft sequence command. Vcc power must remain high to effectively register command.
20.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Parameter Alt Description
t
PHSB
t
DELAY
[19, 20]
t
ss
[18]
t
HLHX
t
HLQZ , tBLQZ
Hardware STORE Pulse Width 15 ns
Time Allowed to Complete SRAM Cycle 1 70
Soft Sequence Processing Time 70 us
Switching Waveforms
Figure 12. Hardware STORE Cycle
CY14B101L
Min Max
Unit
μ
s
[19, 20]
Figure 13. Soft Sequence Processing
Document Number: 001-06400 Rev. *I Page 13 of 18
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CY14B101L
Ordering Information
Option
T - Tape and Reel
Blank - Std.
Speed
25 - 25 ns
35 - 35 ns
45 - 45 ns
Package
SZ - 32 SOIC
SP - 48 SSOP
Data Bus
L - x8
Density
101 - 1 Mb
Voltage
B - 3.0V
Cypress
Part Numbering Nomenclature
CY 14 B 101 L - SZ 25 X C T
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Temperature
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Speed
(ns)
25 CY14B101L-SZ25XCT 51-85127 32-pin SOIC Commercial
35 CY14B101L-SZ35XCT 51-85127 32-pin SOIC Commercial
Document Number: 001-06400 Rev. *I Page 14 of 18
Ordering Code Package Diagram Package Type
CY14B101L-SZ25XC 51-85127 32-pin SOIC
CY14B101L-SP25XCT 51-85061 48-pin SSOP
CY14B101L-SP25XC 51-85061 48-pin SSOP
CY14B101L-SZ25XIT 51-85127 32-pin SOIC Industrial
CY14B101L-SZ25XI 51-85127 32-pin SOIC
CY14B101L-SP25XIT 51-85061 48-pin SSOP
CY14B101L-SP25XI 51-85061 48-pin SSOP
CY14B101L-SZ35XC 51-85127 32-pin SOIC
CY14B101L-SP35XCT 51-85061 48-pin SSOP
CY14B101L-SP35XC 51-85061 48-pin SSOP
CY14B101L-SZ35XIT 51-85127 32-pin SOIC Industrial
CY14B101L-SZ35XI 51-85127 32-pin SOIC
CY14B101L-SP35XIT 51-85061 48-pin SSOP
CY14B101L-SP35XI 51-85061 48-pin SSOP
Operating
Range
[+] Feedback
CY14B101L
Ordering Information
51-85058 *A
PIN 1 ID
SEATING PLANE
116
17 32
DIMENSIONS IN INCHES[MM]
MIN.
MAX.
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
0.050[1.270]
TYP.
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.0100[0.254]
0.006[0.152]
0.012[0.304]
0.021[0.533]
0.041[1.041]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
0.014[0.355]
0.020[0.508]
0.810[20.574]
0.822[20.878]
51-85127-*A
Speed
(ns)
Ordering Code Package Diagram Package Type
45 CY14B101L-SZ45XCT 51-85127 32-pin SOIC Commercial
CY14B101L-SZ45XC 51-85127 32-pin SOIC
CY14B101L-SP45XCT 51-85061 48-pin SSOP
CY14B101L-SP45XC 51-85061 48-pin SSOP
CY14B101L-SZ45XIT 51-85127 32-pin SOIC Industrial
CY14B101L-SZ45XI 51-85127 32-pin SOIC
CY14B101L-SP45XIT 51-85061 48-pin SSOP
CY14B101L-SP45XI 51-85061 48-pin SSOP
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
Operating
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
Range
Document Number: 001-06400 Rev. *I Page 15 of 18
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CY14B101L
Package Diagrams
51-85061-*C
(continued)
Figure 15. 48-Pin Shrunk Small Outline Package (51-85061)
Document Number: 001-06400 Rev. *I Page 16 of 18
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CY14B101L
Document History Page
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 001-06400
Rev. ECN No.
Submission
Date
** 425138 TUP New data sheet
*A 437321 TUP Show data sheet on External Web
*B 471966 TUP Changed I
*C 503272 PCI Changed from Advance to Preliminary
*D 597002 TUP Removed V
*E 688776 VKN Added footnote related to HSB
*F 1349963 UHA/SFV Changed from Preliminary to Final
*G 242798 6 GVCH Move to external web
*H 2546756 GVCH/AESA 08/01/2008 Aligned part number nomenclature
*I 2625139 GVCH/PYRS 01/30/09 Updated “features”
Orig. of
Change
Description of Change
from 5 mA to 10 mA
Changed ISB from 2 mA to 3 mA
Changed V
Changed t
Changed Endurance from 1 million Cycles to 500K Cycles
CC3
from 2.2V to 2.0V
IH(min)
from 40 μs to 50 μs
RECALL
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
Changed the term “Unlimited” to “Infinite”
Changed Endurance from 500K Cycles to 200K Cycles
Added temperature specification to Data Retention - 20 years at 55
Removed Icc
Changed Icc
Added a footnote on V
Changed V
Added footnote 17 related to using the software command
values from the DC table for 25 ns and 35 ns industrial grade
1
value from 3 mA to 6 mA in the DC table
2
SWITCH(min)
IH
from 2.55V to 2.45V
Updated Part Nomenclature Table and Ordering Information Table
specification from the AutoStore/Power Up RECALL
specification of 70 μs in the hardware STORE cycle table
from 57 μF to 120 μF
to t
GHAX
table
Changed t
Added t
DELAY(max)
Removed t
Changed t
Changed V
Changed t
SWITCH(min)
specification from 20 ns to 1 ns
GLAX
specification
HLBL
specification from 70 μs (min) to 70 μs (max)
SS
CAP(max)
GLAX
Updated Ordering Information table
Corrected typo in ordering information
Changed pin definition of NC pin
Updated data sheet template
Added data retention at 55
Updated WE
pin description
Added best practices
Added I
Updated V
Removed footnote 4 and 5
spec for 25ns and 35ns access speed for industrial temperate
CC1
from Vcc+0.3 to Vcc+0.5
IH
Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter t
Changed t
Renamed t
Updated figure 11 and 12
Renamed t
Updated Figure 13
RECALL
GLAX
HLHX
to t
to t
to t
AS
from 50us to 120us (Including tss of 70us)
HA
PHSB
°
C
o
C
SA
Document Number: 001-06400 Rev. *I Page 17 of 18
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CY14B101L
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales
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© Cypress Semiconductor Corporation, 2006- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used fo r
medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express written agreemen t wi t h Cy press. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify , crea te deri vative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress
integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06400 Rev. *I Revised January 30, 2009 Page 18 of 18
AutoStore and Quant umTrap ar e registered tradem arks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be the trademarks of their respective
holders.
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