Cypress CY14B101L User Manual

CY14B101L

1 Mbit (128K x 8) nvSRAM

Features

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

1024 X 1024

QuantumTrap

1024 x 1024

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

OE

CE

WE

HSB

V

CC

V

CAP

A

15

-

A

0

A

0

A

1

A

2

A

3

A

4

A

10

A

11

A

5

A

6

A

7

A

8

A

9

A

12

A

13

A

14

A

15

A

16

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

■

25 ns, 35 ns, and 45 ns access times

■

Pin compatible with STK14CA8

■

Hands off automatic STORE on power down with only a small
capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited READ, WRITE, and RECALL cycles

■

200,000 STORE cycles to QuantumTrap

■

20 year data retention at 55°C

■

Single 3V +20%, –10% operation

■

Commercial and industrial temperature

■

32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages

■

RoHS compliance

Functional Description

The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06400 Rev. *I Revised January 30, 2009

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CY14B101L

Pinouts

V

CAP

A

16

A

14

A

12

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

DQ

0

DQ

1

V

CC

A

15

HSB
WE
A

13

A

8

A

9

A

11

OE
A

10

CE
DQ

7

DQ

6

DQ

5

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

V

SS

DQ

2

DQ

3

DQ

4

32
31
30
29
28
27
26
25
24
23
22
21
20
19

18
17

A

16

NC

DQ7

DQ6

DQ5

NC

DQ4

V

CC

DQ3

DQ2

DQ1

DQ0

V

SS

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

NC

HSB
WE

NC

NC

A

8

A

9

A

10

A

11

A

12

A

13

A

14

A

15

1
2
3
4
5
6
7
8
9
10
11

12
13
14

15
16
17
18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

Top View

(not to scale)

OE

CE

V

CC

V

SS

V

CAP

NC

NC

NC
NC

NC

NC
NC

NC
NC

Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP

Pin Definitions

Pin Name Alt IO Type Description

A

0–A16

DQ

-DQ

0

7

WE

CE
OE

V

V

SS

CC

W

E
G

HSB

V

CAP

NC No Connect No Connect. This pin is not connected to the die.

Document Number: 001-06400 Rev. *I Page 2 of 18

Input Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.

Input or Output Bidirectional Dat a IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.
Input Chip Enable Input, Active LOW . When LOW , selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

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CY14B101L

Device Operation

The CY14B101L nvSRAM is made up of two functional compo­nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera­tions from the nonvolatile cells and up to one million STORE
operations.

SRAM Read

The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
When the READ is initiated by an address transition, the outputs
are valid after a delay of t
initiated by CE
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the t
the need for transitions on any control input pins, and remains
valid until another address change or until CE or OE is brought
HIGH, or WE

determines the 131,072 data bytes accessed.

0–16

(READ cycle 1). If the READ is

or OE, the outputs are valid at t

AA

or at t

ACE

access time without

AA

or HSB is brought LOW.

DOE

Figure 2 shows the proper connection of the storage capacitor

(V

) for automatic store operation. Refer to the D C Electrical

CAP

Characteristics on page 7 for the size of V

the V
A pull up is placed on WE

pin is driven to 5V by a charge pump internal to the chip.

CAP

to hold it inactive during power up.

. The voltage on

CAP

Figure 2. AutoStore Mode

V

CAP

CAP

V

V

WE

CC

10k Ohm

,

V

CC

U

0.1 F

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB
the WRITE cycle and must remain stable until either CE

or WE

goes HIGH at the end of the cycle.
The data on the common IO pins DQ

memory if it has valid t
WRITE or before the end of an CE

, before the end of a WE controlled

SD

controlled WRITE. Keep OE

are written into the

0–7

HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE
the output buffers t

is left LOW , internal circuitry turns of f

after WE goes LOW.

HZWE

AutoStore Operation

The CY14B101L stores data to nvSRAM using one of three
storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.

During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V

pin drops below V

CC

pin from VCC. A STORE

CAP

pin. This stored

CAP

SWITCH

capacitor.

CAP

to

CC

, the part

To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB

signal is monitored by the system to detect if an

AutoStore cycle is in progress.

Hardware STORE (HSB) Operation

The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
LOW, the CY14B101L conditionally initiates a STORE operation
after t
the SRAM takes place since the last STORE or RECALL cycle.

. An actual STORE cycle only begins if a WRITE to

DELAY

The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be exter­nally pulled up if it is used to drive other inputs.

SRAM READ and WRITE operations, that are in progress when
HSB

is driven LOW by any means, are given time to comple te
before the STORE operation is initiated. After HSB
the CY14B101L continues SRAM operations for t

, multiple SRAM READ operations take place. If a WRITE

t

DELAY

is in progress when HSB

is pulled LOW, it allows a time, t

to complete. However, any SRAM WRITE cycles requested after

goes LOW are inhibited until HSB returns HIGH.

HSB
If HSB

is not used, it is left unconnected.

pin is used to

pin is driven

goes LOW,

. During

DELAY

DELAY

.

Document Number: 001-06400 Rev. *I Page 3 of 18

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CY14B101L

Hardware RECALL (Power Up)

Data Protection

During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

), an internal RECALL request is latched. When V

SWITCH

SWITCH

HRECALL

, a RECALL

to complete.

CC

Software ST ORE

Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ
sequence is performed:

1. Read address 0x4E38, Valid READ

2. Read address 0xB1C7, Valid READ

3. Read address 0x83E0, Valid READ

4. Read address 0x7C1F, Valid READ

5. Read address 0x703F, Valid READ

6. Read address 0x8FC0, Initiate STORE cycle

The software sequence is clocked with CE
OE

controlled READs. When the sixth address in the sequence

controlled READs or

is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE
a valid sequence. After the t
SRAM is again activated for READ and WRITE operation.

cycle time is fulfilled, the

STORE

is LOW for

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:

1. Read address 0x4E38, Valid READ

2. Read address 0xB1C7, Valid READ

3. Read address 0x83E0, Valid READ

4. Read address 0x7C1F, Valid READ

5. Read address 0x703F, Valid READ

6. Read address 0x4C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.

controlled READ operations is

cycle time, the SRAM is once

RECALL

The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V

If the CY14B101L is in a WRITE mode (both CE

is less than V

CC

SWITCH

.

and WE are low)
at power up after a RECALL or after a STORE, the WRITE is
inhibited until a negative transition on CE

or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.

Noise Considerations

The CY14B101L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of

CC

and V

using leads and traces that are as short

SS,

power, ground, and signals reduce circuit noise.

Low Average Active Power

CMOS technology provides the CY14B101L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper­ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B101L depends on the
following items:

■

The duty cycle of chip enable

■

The overall cycle rate for accesses

■

The ratio of READs to WRITEs

■

CMOS versus TTL input levels

■

The operating temperature

■

The VCC level

■

IO loading

Figure 3. Current Versus Cycle Time

Document Number: 001-06400 Rev. *I Page 4 of 18

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CY14B101L

Preventing Store

Best Practices

Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE

controlled READ operations:

1. Read Address 0x4E38 Valid READ

2. Read Address 0xB1C7 Valid READ

3. Read Address 0x83E0 Valid READ

4. Read Address 0x7C1F Valid READ

5. Read Address 0x703F Valid READ

6. Read Address 0x8B45 AutoStore Disable

Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of

controlled READ operations:

CE

1. Read Address 0x4E38 Valid READ

2. Read Address 0xB1C7 Valid READ

3. Read Address 0x83E0 Valid READ

4. Read Address 0x7C1F Valid READ

5. Read Address 0x703F Valid READ

6. Read Address 0x4B46 AutoStore Enable

If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.

nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:

■

The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on must always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.

■

Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).

■

If autostore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.

■

The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum V
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger V
to make sure there is extra store charge should discuss their
V

CAP

the Vcap voltage level at the end of a t

value specified in this data sheet includes a minimum

CAP

value because

CAP

value

CAP

size selection with Cypress to understand any impact on

period.

RECALL

Document Number: 001-06400 Rev. *I Page 5 of 18

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CY14B101L

.

Notes

1. The six consecutive address locations are in the order listed. WE

is HIGH during all six cycles to enable a nonvolatile cycle.

2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.

3. IO state depends on the state of OE

. The IO table shown is based on OE Low.

Table 1. Hardware Mode Selection

CE WE OE

A15 – A

0

Mode IO Power

H X X X Not Selected Output High Z Standby

L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
LHL0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F
0x8B45

LHL0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F
0x4B46

LHL0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8FC0

LHL0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4C63

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

AutoStore Disable

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

AutoStore Enable

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile Store

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile Recall

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Active I

Active

Active

Active

[1, 2, 3]

[1, 2, 3]

CC2

[1, 2, 3]

[3]

[1, 2, 3]

Document Number: 001-06400 Rev. *I Page 6 of 18

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