Cypress CapSense CY8CMBR2044 Design Manual

CapSense® Design Guide

AN66308 - CY8CMBR2044

Doc. No. 001-66308 Rev. *F

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

Phone (USA): 800.858.1810

Phone (Intnl): 408.943.2600

http://www.cypress.com

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AN66308 - CY8CMBR2044 CapSense® Design GuideDoc. No. 001-66308 Rev. *F 2

Contents

1. Introduction .................................................................................................................................................................... 5

1.1 Abstract ................................................................................................................................................................. 5

1.2 Cypress’s CapSense Documentation Ecosystem .................................................................................................. 5

1.3 CY8CMBR2044 CapSense Express™ Device Features ....................................................................................... 7

1.4 Document Conventions ......................................................................................................................................... 9

2. CapSense Technology ................................................................................................................................................ 10

2.1 CapSense Fundamentals .................................................................................................................................... 10

2.2 Capacitive Sensing Method ................................................................................................................................. 11

2.2.1 CapSense Sigma-Delta (CSD) ............................................................................................................... 11

2.3 SmartSense Auto-Tuning .................................................................................................................................... 13

2.3.1 Process Variation.................................................................................................................................... 13

2.3.2 Reduced Design Cycle Time .................................................................................................................. 13

3. CapSense Schematic Design ..................................................................................................................................... 15

3.1 CY8CMBR2044 Configuration Options ............................................................................................................... 15

3.1.1 CapSense Buttons (CSx) ........................................................................................................................ 15

3.1.2 General-Purpose Outputs (GPOx) .......................................................................................................... 15

3.1.3 Modulation Capacitor (C

3.1.4 Button Auto Reset (ARST) ...................................................................................................................... 16

3.1.5 Toggle ON/OFF ...................................................................................................................................... 16

3.1.6 Flanking Sensor Suppression (FSS) ....................................................................................................... 17

3.1.7 LED ON Time ......................................................................................................................................... 18

3.1.8 System Diagnostics ................................................................................................................................ 19

3.1.9 Scan Rate/Sleep ..................................................................................................................................... 21

3.1.10 Serial Debug Data Out ............................................................................................................................ 22

3.2 Design Toolbox .................................................................................................................................................... 25

3.2.1 General Layout Guidelines ................................ ..................................................................................... 25

3.2.2 Layout Estimator ..................................................................................................................................... 26

3.2.3 CP, Power Consumption and Response Time Calculator ....................................................................... 27

3.2.4 Design Validation .................................................................................................................................... 28

) .................................................................................................................. 15

MOD

4. Electrical and Mechanical Design Considerations ................................................................................................... 30

4.1 Overlay Selection ................................................................................................................................................ 30

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 3

4.1.1 Bonding Overlay to PCB ......................................................................................................................... 31

Contents

4.2 ESD Protection .................................................................................................................................................... 31

4.2.1 Prevent ................................................................................................................................................... 31

4.2.2 Redirect .................................................................................................................................................. 31

4.2.3 Clamp ..................................................................................................................................................... 31

4.3 Electromagnetic Compatibility (EMC) Considerations ......................................................................................... 32

4.3.1 Radiated Interference ............................................................................................................................. 32

4.3.2 Conducted Immunity and Emissions ....................................................................................................... 32

4.4 PCB Layout Guidelines ....................................................................................................................................... 32

5. Low-Power Design Considerations ........................................................................................................................... 33

5.1 System Design Recommendations ...................................................................................................................... 33

5.2 Calculating Average Power ................................................................................................................................. 33

5.2.1 Button Scan Rate (TR) ............................................................................................................................ 33

5.2.2 Scan Time (TS) ....................................................................................................................................... 34

5.2.3 Average Current in NO TOUCH State (I

5.2.4 Average Current in TOUCH State (I

5.2.5 Average Standalone Current (I

5.2.6 Average Current (I

5.2.7 Average Power (P

) ............................................................................................................................ 35

AVE

) ............................................................................................................................. 36

AVE

AVE_T

) ..................................................................................................... 35

AVE_SA

5.2.8 Example Calculation ............................................................................................................................... 36

5.3 Sleep Modes........................................................................................................................................................ 37

5.3.1 Low-Power Sleep Mode .......................................................................................................................... 37

5.3.2 Deep Sleep Mode ................................................................................................................................ ... 37

) ....................................................................................... 35

AVE_NT

) ............................................................................................... 35

6. Resources .................................................................................................................................................................... 38

6.1 Website ............................................................................................................................................................... 38

6.2 Datasheet ............................................................................................................................................................ 38

6.3 Design Toolbox .................................................................................................................................................... 38

6.4 Multi-Chart ........................................................................................................................................................... 38

6.5 Design Support .................................................................................................................................................... 39

7. Appendix ...................................................................................................................................................................... 40

7.1 Schematic Example ............................................................................................................................................. 40

7.1.1 Schematic 1: Four Buttons with Four GPOs ........................................................................................... 40

7.1.2 Schematic 2: Three Buttons with Advanced Features enabled .............................................................. 42

Acronyms ...................................................................................................................................................................... 43

Glossary ................................................................................................................................................................................ 44

Revision History ................................................................................................................................................................... 50

Document Revision History ........................................................................................................................................... 50

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 4

1. Introduction

Abstract

This document describes how to implement capacitive sensing functionality using Cypress’s CapSense

CY8CMBR2044 device. The following topics are covered in this guide:

 Features of the CY8CMBR2044
 CapSense principles of operation
 Configuration options of the CY8CMBR2044 device
 Using the Design Toolbox with the CY8CMBR2044
 System electrical and mechanical design considerations for the CY8CMBR2044
 Low-power design considerations for the CY8CMBR2044
 Additional resources and support for designing CapSense into your system

®

Express

Cypress’s CapSense Documentation Ecosystem

Figure 1-1 and Table 1-1 summarize the CapSense documentation ecosystem. These resources allow the

implementers to quickly access the information they need to complete a CapSense product design. Figure 1-1 shows
a typical product design cycle with capacitive sensing; this document covers the topics highlighted in green. Table 1-1
offers links to supporting documents for each of the numbered tasks in Figure 1-1.

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 5

Introduction

3. Select CapSense device based on
required functionality

2. Specify system requirements and
characteristics

11. Preproduction build (prototype)

12. Test and evaluate system functionality and
CapSense performance

Meets

specifications?

13. Production

Yes

No

= Topics covered in this document

1. Understand CapSense technology

4. Mechanical
Design

5. Schematic
capture and

PCB layout

Design for CapSense

9. Programming PSoC

†

10. CapSense
Configuration*

6. PSoC Designer project

creation†

7. Firmware

development†

8. CapSense tuning†

*

†

= Applicable to MBR family of devices only
= Applicable to programmable devices only

Figure 1-1. Typical CapSense Product Design Flow

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 6

Introduction

Numbered Design Task of
Figure 1-1

Supporting Cypress CapSense® Documentation

1

Getting Started with CapSense

2

CY8CMBR2044 Device Datasheet

3

Getting Started with CapSense

4

This document

5

This document

6

Not applicable for CY8CMBR2044

7

Not applicable for CY8CMBR2044

8

Not applicable for CY8CMBR2044

9

Not applicable for CY8CMBR2044

10

This document

11

This document

Table 1-1. Cypress Documents That Support Numbered Design Tasks of Figure 1-1

CY8CMBR2044 CapSense Express™ Device Features

Cypress’s CY8CMBR2044 is an ultra-low power device that can quickly and easily add CapSense capacitive touch
sensing to your user interface. This device uses hardware to perform system configuration, eliminating the need for
software tools, firmware development and device programming. The features of the device are listed as follows. For
more details, see CY8CMBR2044 Configuration Options.

 Easy-to-use capacitive button controller

 Four-button solution configurable through Hardware straps
 No software tools or programming required
 Four general-purpose outputs (GPOs)
 GPOs are linked to CapSense buttons
 GPOs support direct LED drive

 Robust noise performance

 Specifically designed for superior noise immunity to external radiated and conducted noise
 Low radiated noise emission

 SmartSense™ Auto-Tuning

 Saves time and effort in device tuning
 CapSense parameters dynamically set in runtime
 Maintains optimal button performance even in noisy environment

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 7

Introduction

 Wide parasitic capacitance CP range ( 5 pF – 40 pF)

 System Diagnostics of CapSense buttons – reports any faults at device power-up

 Button shorted to Ground
 Button shorted to VDD
 Button to button short
 Improper value of modulator capacitor (C
 Parasitic capacitance (CP) out of range

 Advanced features

 Toggle ON/OFF feature on GPOs
 Flanking Sensor Suppression (FSS) provides robust sensing even with closely spaced buttons
 Configurable LED ON Time after button release
 Button output reset if touched for excessive time
 User-controlled Button Scan Rate
 Serial Debug Data output

o Simplifies production line testing and system debug

 Wider operating voltage range

 1.71 V to 5.5 V – ideal for both regulated and unregulated battery applications

 Low power consumption

 Supply current in run mode as low as 15 µAa per button
 Deep Sleep current: 100 nA

 Industrial temperature range: –40 ºC to + 85 ºC

 16-pad Quad Flat No leads (QFN) package (3 mm x 3 mm x 0.6 mm)

a

Power consumption calculated with 1.7% touch time, 500 ms Button Scan Rate, Cp of each button < 19 pF

MOD

)

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 8

Introduction

Convention

Usage

Courier New

Displays file locations, user entered text, and source code:

C:\ ...cd\icc\

Italics

Displays file names and reference documentation:

Read about the sourcefile.hex file in the PSoC Designer User Guide.

[Bracketed, Bold]

Displays keyboard commands in procedures:

[Enter] or [Ctrl] [C]

File > Open

Represents menu paths:

File > Open > New Project

Bold

Displays commands, menu paths, and icon names in procedures:

Click the File icon and then click Open.

Times New Roman

Displays an equation:

2 + 2 = 4

Text in gray boxes

Describes Cautions or unique functionality of the product.

Document Conventions

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 9

2. CapSense Technology

CY8CMBR2044

C

MOD

Sensor

Capacitors

CapSense Fundamentals

CapSense is a touch sensing technology that works by measuring the capacitance of each input pin on the
CapSense controller that has been designated as a sensor. As shown in Figure 2-1, the total capacitance on each of
the sensor pins can be modeled as equivalent lumped capacitors with values of C
sensors. Circuitry internal to the CY8CMBR2044 device converts the magnitude of each CX into a digital code that is
stored for post-processing. A modulating capacitor, C
C

will be discussed in more detail in Capacitive Sensing Method.

MOD

, is used by the CapSense controller’s internal circuitry.

MOD

Figure 2-1. CapSense Implementation in a CY8CMBR2044 Device

through C

X,1

for a design with n

X,n

Each sensor input pin is connected to a sensor pad by traces, vias, or both, as necessary. A nonconductive overlay is
required to cover the sensor pad and constitutes the product’s touch interface. When a finger comes into contact with
the overlay, the conductivity and mass of the body effectively introduces a grounded conductive plane parallel to the
sensor pad. This action is represented in Figure 2-2. This arrangement constitutes a parallel plate capacitor, whose
capacitance is given by the following equation:





 Equation 1



Where:
CF = The capacitance affected by a finger in contact with the overlay over a sensor

ε

= Free space permittivity

0

ε

= Dielectric constant (relative permittivity) of overlay

r

A = Area of finger and sensor pad overlap
D = Overlay thickness

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 10

CapSense Technology

Figure 2-2. Section of typical CapSense PCB with the Sensor being activated by a Finger

In addition to the parallel plate capacitance, a finger in contact with the overlay causes electric field fringing between
itself and other conductors in the immediate vicinity. Typically, the effect of these fringing fields is minor, and it can
usually be ignored.

Even without a finger touching the overlay, the sensor input pin has some parasitic capacitance (CP). CP results from
the combination of the CapSense controller internal parasitic and electric field coupling among the sensor pad,

traces, and vias, and other conductors in the system, such as ground plane, other traces, any metal in the product’s

chassis or enclosure, and so on. The CapSense controller measures the total capacitance (CX) connected to a
sensor pin.

When a finger is not touching a sensor, use this equation:

  Equation 2

With a finger on the sensor, CX equals the sum of CP and CF:

   Equation 3

In general, CP is an order of magnitude greater than CF. CP usually ranges from 10 pF to 20 pF, but in extreme cases
it can be as high as 40 pF. CF usually ranges from 0.1 pF to 0.4 pF.

Capacitive Sensing Method

CY8CMBR2044 device supports the CapSense Sigma Delta (CSD) with SmartSense™ Auto-Tuning for converting
sensor capacitance (CX) into digital counts. The CSD method is described in the following sections.

CapSense Sigma-Delta (CSD)

The CSD method in the CY8CMBR2044 device incorporates CX into a switched capacitor circuit, as shown in

Figure 2-3. The sensor (CX) is alternatively connected to GND and the Analog MUX (AMUX) bus by the non-

overlapping switches Sw1 and Sw2, respectively. Sw1 and Sw2 are driven by a precharge clock to bleed a current
(ISENSOR) from the AMUX bus. The magnitude of ISENSOR is directly proportional to the magnitude of CX. The sigma-
delta converter samples AMUX bus voltage and generates a modulating bit stream that controls the constant current
source (IDAC), which charges AMUX such that the average AMUX bus voltage is maintained at VREF. The sensor
bleeds off the charge ISENSOR from the modulating capacitor (CMOD). CMOD, in combination with Rbus, forms a low-pass
filter that attenuates precharge switching transients at the sigma-delta converter input.

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 11

CapSense Technology

Cx

isensor

Sigma-Delta

Converter

Precharge

Clock

Cmod

High-Z

input

Sw1

Sw2

CY8CMBR2044

Gnd

= External Connection

AMUX

Bus

Vref

Rbus

Gnd

IDAC

Figure 2-3. CSD Block Diagram

In maintaining the average AMUX voltage at a steady state value (VREF), the sigma-delta converter matches the
average charge current (IDAC) to ISENSOR by controlling the bit stream duty cycle. The sigma-delta converter stores the
bit stream over the duration of a sensor scan, and the accumulated result is a digital output value, known as raw
count, which is directly proportional to CX. This raw count is interpreted by high-level algorithms to resolve the sensor
state. Figure 2-4 plots the CSD raw counts from a number of consecutive scans during which the sensor is touched
and then released by a finger. As explained in CapSense Fundamentals, the finger touch causes CX to increase by
CF, which in turn causes raw counts to increase proportionally. By comparing the shift in steady state raw count level
to a predetermined threshold, the high-level algorithms can determine whether the sensor is in an ON (Touch) or OFF
(No Touch) state.

Figure 2-4. CSD Raw Counts During a Finger Touch

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 12

CapSense Technology

SmartSense Auto-Tuning

Tuning the touch-sensing user interface is a critical step in ensuring proper system operation and a pleasant user
experience. In the typical design flow, the button interface is tuned in the initial design phase, during system
integration, and before the production ramp. Because it’s an iterative process, tuning can be time-consuming.
SmartSense Auto-Tuning was developed to simplify the user interface development cycle. It is easy to use and
reduces the design cycle time by eliminating the hassles of further manual tuning in prototype and manufacturing
stages. SmartSense Auto-Tuning tunes each CapSense button automatically at power up and then monitors and
maintains optimum button performance during runtime. This technology adapts for manufacturing variation in PCBs
and overlays and automatically tunes out noise from sources such as LCD inverters, AC lines, and switch-mode
power supplies.

Process Variation

SmartSense Auto-Tuning for the CY8CMBR2044 is designed to work with button parasitic capacitance in the range of
5 pF to 40 pF, (typical button CP values range from 10 pF to 20 pF). The sensitivity parameter for each button is set
automatically, based on the characteristics of that particular button. The parameter improves the yield in mass
production because every button maintains a consistent response regardless of the CP variation (from 5 pF to 40 pF)
between the buttons. Parasitic capacitance of the individual buttons can vary due to PCB layout and trace length,
PCB manufacturing process variation, or vendor-to-vendor PCB variation within a multi-sourced supply chain. The
sensitivity of a button depends on its parasitic capacitance; higher CP values decrease sensitivity, resulting in
decreased finger touch signal amplitude. In some cases, a change in CP detunes the system, resulting in unfavorable
button performance (either too sensitive or insensitive) or even a nonoperational button. In either situation, you must
retune the system and, in some cases, you need to requalify the user interface subsystem. SmartSense Auto-Tuning
resolves these issues.

SmartSense Auto-Tuning makes platform designs possible. For example, consider the capacitive touch sensing
multimedia keys on a laptop computer; the spacing between the buttons depends on the size of the laptop and the
keyboard layout. In this example, the wide-screen machine has larger spaces between the buttons than a standard­screen model would. The additional space means increased trace length between the button and the CapSense
controller. The bigger trace length, in turn, leads to a higher parasitic capacitance of the button. As a result, the
parasitic capacitance of the CapSense buttons can vary in different models of the same platform design. Though the
buttons’ functionality is identical for all of the laptop models, the buttons must be tuned for each model. SmartSense
Auto-Tuning lets you do platform designs using the recommended practices shown in the PCB Layout in Getting

Started with CapSense.

Figure 2-5. Design of Laptop Multi-Media Keys for 21-inch Model

Figure 2-6. Design of Laptop Multi-Media Keys for 15-inch Model with Same Functionality and Button Size

Reduced Design Cycle Time

When you design a capacitive button interface, the most time-consuming tasks are firmware development, layout,
and button tuning. With a typical touch-sensing controller, the button must be retuned when the same design is
ported to different models or when the mechanical dimensions change in the PCB or the button PCB layout. A design
with SmartSense™ Auto-Tuning meets these challenges because it needs no firmware development, no manual
tuning, and no retuning. In addition, SmartSense™ Auto-Tuning speeds up a typical design cycle. Figure 2-7
compares the design cycles of a typical touch-sensing controller and a SmartSense™ Auto-Tuning-based design.

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 13

CapSense Technology

Feasibility

Study

Schematics

Design

PCB Layout

Design

Mechanical Design

Review

System

Integration

Retuning for any

changes

Tuning process

Production Fine

Tuning

Design

Validation

Production

Typical capacitive user interface Design Cycle

Firmware

Development

Feasibility

Study

Schematics

Design

PCB Layout

Design

Mechanical Design

Review

System

Integration

Design

Validation

Production

CapSense® Express with SmartSense™ Auto-Tuning based

capacitive user interface Design Cycle

Device

Configuration

Figure 2-7. Typical Capacitive Interface Design Cycle Comparison

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 14

3. CapSense Schematic Design

CY8CMBR2044 Configuration Options

Cypress’s CY8CMBR2044 enables you to implement capacitive touch sensing using only hardware. This section
provides an overview of the CapSense controller pins and how to configure them.

Figure 3-1. CY8CMBR2044 Pin Diagram

CapSense Buttons (CSx)

The CY8CMBR2044 controller has four capacitive sense inputs, CS0–CS3. Each capacitive button requires a
connection to one of the capacitive sense inputs. You must ground all unused CapSense (CSx) inputs pins.

General-Purpose Outputs (GPOx)

There are four active LOW outputs on the CY8CMBR2044 controller, GPO0–GPO3. Each output, GPOx, is driven by
its corresponding capacitive sensing input, CSx. You can use GPOs to directly drive LEDs or to replace mechanical
switches. GPOs are in strong drivea mode. You must leave all unused GPOs floating.

Modulation Capacitor (C

Connect a 2.2-nF (±10%) capacitor to the C

a

When a pin is in strong drive mode, it is pulled up to VDD when the output is HIGH and pulled down to Ground when the output is

LOW. The output cannot be floating.

AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 15

MOD

)

pin.

MOD