Cypress CapSense CY8C20396, CapSense CY8C20x36, CapSense CY8C20x46, CapSense CY8C20x66 Specification Sheet

Download

CapSense™ Applications

CY8C20x36/46/66, CY8C20396

Features

■ 1.71V to 5.5V Operating Range

■ Low Power CapSense™ Block

❐ Configurable Capacitive Sensing Elements ❐ Supports Combination of CapSense Buttons, Sliders,

Touchpads, Touch Screens, and Proximity Sensor

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds Running to 24 MHz ❐ Low Power at High Speed ❐ Interrupt Controller ❐ Temperature Range: -40°C to +85°C

■ Flexible On-Chip Memory

❐ Three Program/Data Storage Size Options:

• CY8C20x36: 8K Flash / 1K SRAM

• CY8C20x46: 16K Flash / 2K SRAM

• CY8C20x66: 32K Flash / 2K SRAM

❐ 50,000 Flash Erase/Write Cycles ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ In-System Serial Programming (ISSP)

■ Full-Speed USB

❐ Available on CY8C20396 and CY8C20666 Only ❐ 12 Mbps USB 2.0 Compliant ❐ Eight Unidirectional Endpoints ❐ One Bidirectional Control Endpoint ❐ Dedicated 512 Byte Buffer ❐ Internally Regulated at 3.3V

■ Precision, Programmable Clocking

❐ Internal Main Oscillator: 6/12/24 MHz ± 5% ❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and

Sleep Timers

❐ Precision 32 kHz Oscillator for Optional External Crystal

(CY8C20x46/66 only)

❐ 0.25% Accuracy for USB with No External Components

(CY8C20396 and CY8C20666 only)

■ Programmable Pin Configurations

❐ Up to 36 GPIO (Depending on Package) ❐ Dual Mode GPIO: All GPIO Support Digital IO and Analog

Input

❐ 25 mA Sink Current on All GPIO ❐ Pull up, High Z, Open Drain Modes on All GPIO ❐ CMOS Drive Mode(5 mA Source Current) on Ports 0 and 1:

• 20 mA (at 3.0V) Total Source Current on Port 0

• 20 mA (at 3.0V) Total Source Current on Port 1

❐ Selectable, Regulated Digital IO on Port 1 ❐ Configurable Input Threshold on Port 1 ❐ Hot Swap Capability on all Port 1 GPIO

■ Versatile Analog Mux

❐ Common Internal Analog Bus ❐ Simultaneous Connection of IO ❐ High PSRR Comparator ❐ Low Dropout Voltage Regulator for All Analog Resources

■ Additional System Resources

❐ I

C™ Slave:

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• No Clock Stretching Required (under most conditions)

• Implementation During Sleep Modes with Less Than 100 µA

• Hardware Address Validation

❐ SPI™ Master and Slave: Configurable 46.9 kHz - 12 MHz ❐ Three 16-Bit Timers ❐ Watchdog and Sleep Timers ❐ Internal Voltage Reference ❐ Integrated Supervisory Circuit

■ Complete Development Tools

❐ Free Development Tool (PSoC Designer™) ❐ Full Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Trace Memory

■ Package Options

❐ CY8C20x36:

• 16-Pin 3 x 3 x 0.6 mm QFN

• 24-Pin 4 x 4 x 0.6 mm QFN

• 32-Pin 5 x 5 x 0.6 mm QFN

❐ CY8C20x46:

• 16-Pin 3 x 3 x 0.6 mm QFN

• 24-Pin 4 x 4 x 0.6 mm QFN

• 32-Pin 5 x 5 x 0.6 mm QFN

❐ CY8C20396: 24-Pin 4 x 4 x 0.6 mm QFN ❐ CY8C20x66:

• 32-Pin 5 x 5 x 0.6 mm QFN

• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)

• 48-Pin SSOP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-12696 Rev. *D Revised March 17, 2009

[+] Feedback

CY8C20x36/46/66, CY8C20396

Block Diagram

CAPSENSE

SYSTEM

1K/2K SRAM

Interrupt

Controller

Sleep and

Watchdog

Multiple Clock Sources

Internal Low Speed Oscillator (ILO)

6/12/24 MHz Internal Main Oscillator

(IMO)

PSoC CORE

CPU Core (M8C)

Supervisory ROM (SROM)

8K/16K/32K Flash

Nonvolatile Memory

SYSTEM RESOURCES

SYSTEM BUS

Analog

Reference

SYSTEM BUS

Port 3 Port 2 Port 1 Port 0

CapSense

Module

Global Analog Interconnect

1.8/2.5/3V LDO

Analog

Mux

Two

Comparators

I2C

Slave

SPI

Master/

Slave

POR

and

LVD

USB

System

Resets

Internal Voltage

References

Three 16-Bit

Programmable

Timers

PWRSYS

(Regulator)

Port 4

Digital

Clocks

Document Number: 001-12696 Rev. *D Page 2 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

IDAC

Reference

Buffer

Cinternal

Analog Global Bus

Cap Sense Counters

Comparator

Mux

Refs

CapSense

Clock Select

Oscillator

CSCLK

IMO

PSoC® Functional Overview

The PSoC family consists of on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized periphe ral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts.

The architecture for this device family, as shown in the Block

Diagram on page 2, is comprised of three main areas: the Core,

the CapSense Analog System, and the System Resources (including a full speed USB port). A common, versatile bus allows connection between IO and the analog system. Each CY8C20x36/46/66, CY8C20396 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 36 general purpose IO (GPIO) are also included. The GPIO provides access to the MCU and analog mux.

PSoC Core

The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard architecture microprocessor.

System Resources provide additional capability, such as configurable USB and I2C slave/SPI master-slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C.

The Analog System is composed of the CapSense PSoC block and an internal 1.2V analog reference, which together support capacitive sensing of up to 36 inputs.

CapSense Analog System

The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports.

Figure 1. Analog System Block Diagram

Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin . Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator.

Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Complex capacitive sensing interfaces, such as sliders and

touchpads.

■ Chip-wide mux that allows analog input from any IO pin.

■ Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, which can be found under http://www.cypress.com >> Documentation >> Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1.

Document Number: 001-12696 Rev. *D Page 3 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Additional System Resources

System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here:

■ The I2C slave/SPI master-slave module provides 50/100/400

kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock).

■ The I2C hardware address recognition feature reduces the

already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received.

■ Low Voltage Detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR (Power-On-Reset) circuit eliminates the need for a system supervisor.

■ An internal reference provides an absolute reference for capac-

itive sensing.

■ The 5.5V maximum input, 1.8/2.5/3V-selectable output, low-

dropout regulator (LDO) provides regulation for IOs. A registercontrolled bypass mode allows the user to disable the LDO.

■ Standard Cypress PSoC IDE tools are available for debugging

the CY8C20x36/46/66, CY8C20396 family of parts. However, the additional trace length and a minimal ground plane in the Flex-Pod can create noise problems that make it difficult to debug a Power PSoC design. A custom bonded On-Chip Debug (OCD) device is available in an 48-pin QFN package. The OCD device is recommended for debugging designs that have high current and/or high analog accuracy requirements. The QFN package is compact and is connected to the ICE through a high density connector.

Getting Started

The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications.

For in depth information, along with detailed programming details, see the PSoC Technical Reference Manual for CY8C28xxx PSoC devices.

For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.

Application Notes

Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark.

Training

Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.

CYPros Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.

Programmable System-on-Chip™

Document Number: 001-12696 Rev. *D Page 4 of 34

Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various

application designs that include firmware and hardware design files that enable you to complete your designs quickly.

Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800541-4736.

[+] Feedback

CY8C20x36/46/66, CY8C20396

Development Tools

PSoC Designer™ is a Microsoft® Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows XP and Windows Vista.

This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers.

PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.

PSoC Designer Software Subsystems

System-Level View

The system-level view is a drag-and-drop visual embedded system design environment based on PSoC Express. In this view you solve design problems the same way you might think about the system. Select input and output devices based upon system requirements. Add a communication interface and define the interface to the system (registers). Define when and how an output device changes state based upon any/all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC devices that match your system requirements.

PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device.

Chip-Level View

The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.x. You choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. You configure the user modules for your chosen application and connect them to each other and to the proper pins. Then you generate your project. This prepopulates your project with APIs and libraries that you can use to program your application.

The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time.

Hybrid Designs

You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over onchip resources. All views of the project share common code editor, builder , and common debug, emulation, and programming tools.

Code Generation Tools

PSoC Designer supports multiple third-party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to be merged seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices.

The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Debugger

PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

Document Number: 001-12696 Rev. *D Page 5 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Designing with PSoC Designer

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.

The PSoC development process can be summarized in the following four steps:

1. Select Components

2. Configure Components

3. Organize and Connect

4. Generate, Verify, and Debug

Select Components

Both the system-level and chip-level views provide a library of pre-built, pre-tested hardware peripheral components. In the system-level view these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2Cbus, for example), and the logic to control how they interact with one another (called valuators).

In the chip-level view the components are called “user modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and progra mma ble system-on-chip varieties.

Configure Components

Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or b y selecting values from drop-down menus.

Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.

Organize and Connect

You build signal chains at the chip level by interconnecting user modules to each other and the IO pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions.

In the system-level view selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog-todigital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan.

In the chip-level view, you perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system.

Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code.

A complete code development environment allows you to develop and customize your applications in C, assembly language, or both.

The last step in the development process takes place inside PSoC Designer’s Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

Document Number: 001-12696 Rev. *D Page 6 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Table 1. Acronyms

Acronym Description

AC alternating current API application programming interface CPU central processing unit DC direct current FSR full scale range GPIO general purpose IO GUI graphical user interface ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output LSb least-significant bit LVD low voltage detect MSb most-significant bit POR pow er on r eset PPOR precision power on reset PSoC® Programmable System-on-Chip™ SLIMO slow IMO SRAM static random access memory

Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 9 on page 15 lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

Document Number: 001-12696 Rev. *D Page 7 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Pinouts

QFN

(Top View)

AI, XOut, P2[5]

AI, I2C SCL, SPI SS, P1[7]

AI, I2C SDA, SPI MISO, P1[5]

AI, SPI CLK, P1[ 3 ]

1 2

3 4

11 10

161514

P0[3], AI

P0[7], AI

Vdd

P0[4], AI

AI, CLK

, SPI MOSI, P1[1]

AI, DATA

, I2C SDA, SPI CLK, P1[0]

P1[2], AI

AI, XIn, P2[3]

P1[4], EXTCLK, AI

XRES

P0[1], AI

Vss

567

Notes

1. These are the ISSP pins, which are not High Z at POR (Power On Reset).

2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.

The CY8C20x36/46/66, CY8C20396 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO.

16-Pin QFN

Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device

Pin No.

Type

Digital Analog

Name Description

[2]

1 IO I P2[5] Crystal output (XOut) 2 IO I P2[3] Crystal input (XIn) 3 IOHR I P1[7] I 2C SCL, SPI SS 4 IOHR I P1[5] I2C SDA, SPI MISO 5 IOHR I P1[3] SPI CLK 6 IOHR I P1[1] ISSP CLK

[1]

, I2C SCL, SPI

MOSI 7 Power Vss Ground connection 8 IOHR I P1[0] ISSP DATA

[1]

, I2C SDA, SPI

CLK 9 IOHR I P1[2]

10 IOHR I P1[4] Optional external clock

(EXTCLK)

11 Input XRES Active high external reset with

internal pull down

12 IOH I P0[4] 13 Power Vdd Supply voltage 14 IOH I P0[7] 15 IOH I P0[3] Integrating input 16 IOH I P0[1] Integrating input

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Figure 2. CY8C20236, CY8C20246 PSoC Device

Document Number: 001-12696 Rev. *D Page 8 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

24-Pin QFN

Note

3. The center pad (CP) on the QFN package must be connected t o gr ound (Vss) for be st mechanical, thermal, an d electrical perf ormance . If not connected t o ground , it must be electrically floated and not connected to any other signal.

AI, DATA

, I2C SDA, SPI CLK, P1[0]

QFN

(Top View)

AI, I2C SCL, SPI SS, P1[7]

AI, I2C SDA, SPI MISO, P1[5]

AI, SPI CLK, P1[3]

1 2 3 4 5

18 17 16 15 14 13

P0[2], AI P0[0], AI

2423222120

P0[3], AI

P0[5], AI

P0[7], AI

Vdd

P0[4], AI

SPI MOSI, P1[1]

AI, P1[2]

AI, P2[1]

P1[6], AI

AI, EXTCLK, P1[4]

XRES

P2[0], AI

P0[6], AI

AI, CLK

, I2C SCL

P0[1], AI

Vss

AI, XOut, P2[5]

AI, XIn, P2[3]

Table 3. Pin Definitions - CY8C20336, CY8C20346

Pin No.

Type

Digital Analog

Name Description

[2, 3]

Figure 3. CY8C20336, CY8C20346 PSoC Device

1 IO I P2[5] Crystal output (XOut) 2 IO I P2[3] Crystal input (XIn) 3 IO I P2[1] 4 IOHR I P1[7] I2C SCL, SPI SS 5 IOHR I P1[5] I2C SDA, SPI MISO 6 IOHR I P1[3] SPI CLK 7 IOHR I P1[1] ISSP CLK

MOSI

[1]

, I2C SCL, SPI

8 NC No connection 9 Power Vss Ground connection 10 IOHR I P1[0] ISSP DATA

[1]

, I2C SDA, SPI

CLK 11 IOHR I P1[2] 12 IOHR I P1[4] Optional external clock input

(EXTCLK) 13 IOHR I P1[6] 14 Input XRES Active high external reset with

internal pull down 15 IO I P2[0] 16 IOH I P0[0] 17 IOH I P0[2] 18 IOH I P0[4] 19 IOH I P0[6] 20 Power Vdd Supply voltage 21 IOH I P0[7] 22 IOH I P0[5] 23 IOH I P0[3] Integrating input 24 IOH I P0[1] Integrating input CP Power Vss Center pad must be connected

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

to ground

Document Number: 001-12696 Rev. *D Page 9 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

24-Pin QFN with USB Pinout

P0[7]

I2C SDA, SPI MISO, P1[5]

USB D-

QFN

(Top View)

I2C SCL, SPI SS, P1[7]

SPI CLK, P1[3]

1 2 3 4 5

18 17 16 15 14 13

P0[0] XRES

2423222120

P0[3]

P0[5]

P0[6]

P0[2]

ISSP CLK, I2C SCL, SPI MOSI, P1[1]

VDD

P2[1]

Vss

P1[2]

ISSP DATA, I2C SDA, P1[0]

P1[4], EXTCLK

P1[6]

P0[4]

P0[1], AI

USB D+

P2[5]

P2[3]

Figure 4. CY8C20396 PSoC Device

Table 4. Pin Definitions - CY8C20396 PSoC Device

Pin No.

1 IO I P2[5] 2 IO I P2[3] 3 IO I P2[1] 4 IOHR I P1[7] I2C SCL, SPI SS 5 IOHR I P1[5] I2C SDA, SPI MISO 6 IOHR I P1[3] SPI CLK 7 IOHR I P1[1] ISSP CLK, I2C SCL, SPI MOSI 8 Power VSS Ground

9 IO I D+ USB D+ 10 IO I D- USB D11 Power VDD Supply 12 IOHR I P1[0] ISSP DATA, I2C SDA 13 IOHR I P1[2] 14 IOHR I P1[4] Optional external clock input

15 IOHR I P1[6] 16 RESET INPUT XRES Active high external reset with

17 IOH I P0[0] 18 IOH I P0[2] 19 IOH I P0[4] 20 IOH I P0[6] 21 IOH I P0[7] 22 IOH I P0[5] 23 IOH I P0[3] Integrating input 24 IOH I P0[1] Integrating input

CP Power VSS Thermal pad must be

LEGEND I = Input, O = Output, OH = 5 mA High O utput Drive, R = Regulated Output

Type

Digital Analog

Name Description

(EXTCLK)

internal pull down

connected to Ground

[2, 3]

Document Number: 001-12696 Rev. *D Page 10 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

32-Pin QFN

AI, P0[1] AI, P2[7]

AI, XOut, P2[5]

AI, XIn, P2[3]

AI, P2[1] AI, P3[3]

QFN

(Top View)

10111213141516

1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

32313029282726

Vss

P0[3], AI

P0[7], AI

Vdd

P0[6], AI

P0[4], AI

P0[2], AI

AI, P3[1]

AI, I2C SCL, SPI SS, P1[7]

P0[0], AI P2[6], AI

P3[0], AI XRES

AI, I2C SDA, SPI MISO, P1[5]

AI, SPICLK, P1[3]

Vss

AI, P1[2]

AI, EXTCLK, P1[4]

AI, P1[6]

P2[4], AI P2[2], AI P2[0], AI P3[2], AI

P0[5], AI

AI, CLK

, I2C SCL, SPI MOSI, P1[1]

AI, DATA

, I2C SDA, SPI CLK, P1[0]

Table 5. Pin Definitions - CY8C20436/46/66 PSoC Device

Pin No.

1 IOH I P0[1] Integrating input 2 IO I P2[7] 3 IO I P2[5] Crystal output (XOut) 4 IO I P2[3] Crystal input (XIn) 5 IO I P2[1] 6 IO I P3[3] 7 IO I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO 10 IOHR I P1[3] SPI CLK. 11 IOHR I P1[1] ISSP CLK 12 Power Vss Ground connection. 13 IOHR I P1[0] ISSP DATA 14 IOHR I P1[2] 15 IOHR I P1[4] Optional external clock input

16 IOHR I P1[6] 17 Input XRES Active high external reset with

18 IO I P3[0]

Type

Digital Analog

Name Description

[1]

, I2C SCL, SPI MOSI.

[1]

, I2C SDA., SPI CLK

(EXTCLK)

internal pull down

[2, 3]

Figure 5. CY8C20436/46/66 PSoC Device

19 IO I P3[2] 20 IO I P2[0] 21 IO I P2[2] 22 IO I P2[4] 23 IO I P2[6] 24 IOH I P0[0] 25 IOH I P0[2] 26 IOH I P0[4] 27 IOH I P0[6] 28 Power Vdd Supply voltage 29 IOH I P0[7] 30 IOH I P0[5] 31 IOH I P0[3] Integrating input 32 Power Vss Ground connection CP Power Vss Center pad must be connected to

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

ground

Document Number: 001-12696 Rev. *D Page 11 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

48-Pin QFN

QFN

(Top View)

Vss

P0[3], AI

P0[5], AI

P0[7], AI

Vdd

P0[6], AI

P0[2], AI

P0[0], AI

10 11

AI, P2[7]

AI, XOut, P2[5]

AI, XIn, P2[3]

AI, P2[1] AI, P4[3] AI, P4[1] AI, P3[7]

AI, P3[5] AI, P3[3] AI, P3[1]

AI, I2C SCL, SPI SS, P1[7]

35 34 33 32 31 30 29

28 27 26

4847464544

43424140393837

P2[4], AI P2[2], AI

P2[0], AI P4[2], AI P4[0], AI P3[6], AI

P3[4], AI P3[2], AI P3[0

], AI

XRES

P1[6], AI

P2[6], AI

1 2 3 4 5 6 7 8 9

131415161718192021

I2C SDA, SPI MISO, A I, P1[5]

SPI CLK, AI, P1[3]

AI, CLK

, I2C SCL, SPI MOSI, P1[1]

Vss

D+

D-

Vdd

AI, DATA

, I2C SDA, SPI CLK, P1[0]

AI, P1[2]

AI, EXTCLK, P1[4]

P0[4], AI

P0[1], AI

Table 6. Pin Definitions - CY8C20666 PSoC Device

Pin No.

1 NC No connection 2 IO I P2[7] 3 IO I P2[5] Crystal output (XOut) 4 IO I P2[3] Crystal input (XIn) 5 IO I P2[1] 6 IO I P4[3] 7 IO IP4[1] 8 IO I P3[7] 9 IO I P3[5] 10 IO I P3[3] 11 IO I P3[1] 12 IOHR I P1[7] I2C SCL, SPI SS 13 IOHR I P1[5] I2C SDA, SPI MISO 14 NC No connection 15 NC No connection 16 IOHR I P1[3] SPI CLK 17 IOHR I P1[1] ISSP CLK 18 Power Vss Ground connection 19 IO D+ 20 IO D21 Power Vdd Supply voltage 22 IOHR I P1[0] ISSP DATA 23 IOHR I P1[2] 24 IOHR I P1[4] Optional external clock input

25 IOHR I P1[6] 26 Input XRES Active high external reset with

27 IO I P3[0] 28 IO IP3[2] 29 IO IP3[4]

30 IO IP3[6] 40 IOH I P0[6] 31 IO I P4[0] 41 Power Vdd Supply voltage 32 IO I P4[2] 42 NC No connection 33 IO I P2[0] 43 NC No connection 34 IO I P2[2] 44 IOH I P0[7] 35 IO I P2[4] 45 IOH I P0[5] 36 IO I P2[6] 46 IOH I P0[3] Integrating input 37 IOH I P0[0] 47 Power Vss Ground connection 38 IOH I P0[2] 48 IOH I P0[1] 39 IOH I P0[4] CP Power Vss Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Name Description

Digital

Analog

[1]

(EXTCLK)

internal pull down

, I2C SCL, SPI MOSI

, I2C SDA, SPI CLK

[2, 3]

Pin No.

Figure 6. CY8C20666 PSoC Device

Name Description

Digital

Analog

Document Number: 001-12696 Rev. *D Page 12 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

48-Pin SSOP

SSOP

P0[7]

VDD

P0[5]

P0[6]

P0[3]

P0[4] P0[1] P0[2] P2[7]

P0[0] P2[5]

P2[6] P2[3]

P2[4] P2[1]

P2[2]

P2[0]

P3[6] P4[3]

P3[4] P4[1]

P3[2]

P3[0] P3[7]

XRES P3[5]

NC P3[3]

NC P3[1] NC

NC P1[7]

NC P1[5]

P1[6] P1[3]

P1[4] P1[1] P1[2]

VSS P1[0]

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

47 46 45

38 37

32 31

30 29 28

Table 7. Pin Definitions - CY8C20566 PSoC Device

Name Description

Digital

Analog

pull down

[1]

, I2C SCL, SPI MOSI

[1]

, I2C SDA, SPI CLK

Pin No.

1 IOH IO P0[7] 2 IOH IO P0[5] 3 IOH IO P0[3] 4 IOH IO P0[1] 5 IO IO P2[7] 6 IO IO P2[5] XTAL Out 7 IO IO P2[3] XTAL In 8 IO IO P2[1] 9 NC No connection 10 NC No connection 11 IO IO P4[3] 12 IO IO P4[1] 13 NC No connection 14 IO IO P3[7] 15 IO IO P3[5] 16 IO IO P3[3] 17 IO IO P3[1] 18 NC No connection 19 NC No connection 20 IOHR IO P1[7] I2C SCL, SPI SS 21 IOHR IO P1[5] I2C SDA, SPI MISO 22 IOHR IO P1[3] SPI CLK 23 IOHR IO P1[1] TC CLK 24 VSS Ground Pin 25 IOHR IO P1[0] TC DATA 26 IOHR IO P1[2] 27 IOHR IO P1[4] EXT CLK 28 IOHR IO P1[6] 29 NC No connection 30 NC No connection 31 NC No connection 32 NC No connection

33 NC No connection 41 IO IO P2[2] 34 NC No connection 42 IO IO P2[4] 35 XRES Active high external reset with internal

36 IO IO P3[0] 44 IOH IO P0[0] 37 IO IO P3[2] 45 IOH IO P0[2] 38 IO IO P3[4] 46 IOH IO P0[4] 39 IO IO P3[6] 47 IOH IO P0[6] 40 IO IO P2[0] 48 Power Vdd Power Pin

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

Document Number: 001-12696 Rev. *D Page 13 of 34

[2]

Pin No.

43 IO IO P2[6]

Figure 7. CY8C20566 PSoC Device

Name Description

Digital

Analog

[+] Feedback

CY8C20x36/46/66, CY8C20396

48-Pin QFN OCD

QFN

(Top View)

Vss

P0[3], AI

P0[5], AI

P0[7], AI

Vdd

P0[6], AI

P0[2], AI

P0[0], AI

10 11

, P2[7]

AI, XOut, P2[5]

AI, XIn, P2[3]

AI, P2[1] AI, P4[3] AI, P4[1]

AI, P3[7] AI, P3[5] AI, P3[3] AI, P3[1]

AI, I2C SCL, SPI SS, P1[7]

35 34 33 32 31 30 29

28 27 26

4847464544

43424140393837

P2[4], AI P2[2], AI

P2[0], AI P4[2], AI P4[0], AI P3[6], AI

P3[4 ], AI P3[2], AI P3[0 ], AI

XRES

P1[6], AI

P2[6], AI

1 2 3 4 5 6 7 8 9

131415161718192021

I2C SDA, SPI MISO, AI, P1[5]

SPI CLK, AI, P1[3]

AI, CLK

, I2C SCL, SPI MOSI, P1[1]

Vss

D+

D-

Vdd

AI, DATA

, I2C SDA, SPI CLK, P1[0]

AI, P1[2]

AI, EXTCLK, P1[4]

P0[4], AI

P0[1], AI

OCDO

CCLK

HCLK

OCDE

OCDO

Note

4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.

The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit debugging.

[4]

Table 8. Pin Definitions - CY8C20066 PSoC Device

No.

1 OCDOE OCD mode direction pin 2 IO I P2[7] 3 IO I P2[5] Crystal output (XOut) 4 IO I P2[3] Crystal input (XIn) 5 IO I P2[1] 6 IO I P4[3] 7 IO IP4[1] 8 IO I P3[7] 9 IO I P3[5] 10 IO I P3[3] 11 IO I P3[1] 12 IOHR I P1[7] I2C SCL, SPI SS 13 IOHR I P1[5] I2C SDA, SPI MISO 14 CCLK OCD CPU clock output 15 HCLK OCD high speed clock output 16 IOHR I P1[3] SPI CLK. 17 IOHR I P1[1] ISSP CLK 18 Power Vss Ground connection 19 IO D+ 20 IO D21 Power Vdd Supply voltage 22 IOHR I P1[0] ISSP DAT A 23 IOHR I P1[2]

24 IOHR I P1[4] Optional external clock input

25 IOHR I P1[6] 38 IOH I P0[2] 26 Input XRES Active high external reset with

27 IO I P3[0] 40 IOH I P0[6] 28 IO IP3[2] 41 Power Vdd Supply voltage 29 IO IP3[4] 42 OCDO OCD even data IO 30 IO IP3[6] 43 OCDE OCD odd data output 31 IO I P4[0] 44 IOH I P0[7] 32 IO I P4[2] 45 IOH I P0[5] 33 IO I P2[0] 46 IOH I P0[3] Integrating input 34 IO I P2[2] 47 Power Vss Ground connection 35 IO I P2[4] 48 IOH I P0[1] 36 IO I P2[6] CP Power Vss Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Name Description

Digital

Analog

(EXTCLK)

internal pull down

[1]

, I2C SCL, SPI MOSI

(1)

, I2C SDA, SPI CLK

[2, 3]

Figure 8. CY8C20066 PSoC Device

Pin No.

37 IOH I P0[0]

39 IOH I P0[4]

Digital

Name Description

Analog

Document Number: 001-12696 Rev. *D Page 14 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Electrical Specifications

5.5V

750 kH z

24 MHz

CPU Frequency

Vdd Voltage

5.5V

750 kH z 6 MHz 24 MH z

IMO Frequency

Vdd Voltage

3 MHz

1.71V1.71V

3 MHz

SLIMO

Mode

= 01

12 MHz

SLIMO

Mode

= 00

SLIMO

Mode

= 10

This section presents the DC and AC electrical specifications of the CY8C20x36/46/66, CY8C20396 PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/p soc.

Figure 9 . Voltage versus CPU Frequency Figure 10 . IMO Frequency Tri m Options

The following table lists the units of measure that are used in this section.

Table 9. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

°C degree Celsius mA milli-ampere dB decibels ms milli-second fF femto farad mV milli-volts Hz hertz nA nanoampere KB 1024 bytes ns nanosecond Kbit 1024 bits nV nanovolts kHz kilohertz Ω ohm ksps kilo samples per second pA picoampere kΩ kilohm pF picofarad MHz megahertz pp peak-to-peak MΩ megaohm ppm parts per million

μA microampere ps picosecond μF microfarad sps samples per second μH microhenry s sigma: one standard deviation μs microsecond V volts μW microwatts

Document Number: 001-12696 Rev. *D Page 15 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Comparator User Module Electrical Specifications

Note

5. Monotonicity is not guaranteed.

The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V.

Table 10. Comparator User Module Electrical Specifications

Symbol Description Min Typ Max Units Conditions

COMP

Comparator Response Time 70 100 ns 50 mV overdrive Offset 2.5 30 mV Current 20 80 µA Average DC current, 50 mV

overdrive PSRR Input

Supply voltage >2V 80 dB Power Supply Rejection Ratio Supply voltage <2V 40 dB Power Supply Rejection Ratio

0 1.5 V

Range

ADC Electrical Specifications

Table 11. ADC User Module Electrical Specifications

Symbol Description Min Typ Max Units Conditions

Input

RES Resolution 8 10 Bits Settings 8, 9, or 10

S10 10-Bit Sample Rate 5.859 ksps Data Clock set to 6 MHz.

DC Accuracy

DNL

INL I ntegral Nonlinearity -2 +2 LSB For any configuration

Eoffset Offset Error 0 15 90 mV

ADC

PSRR Power Supply Rejection Ration

Egain Gain Error 1 5 %FSR For any resolution

Input Voltage Range Vss 1.3 V This gives 72% of maximum

Input Capacitance 5 pF

code

S8 8-Bit Sample Rate 23.4375 ksps Data Clock set to 6 MHz.

Sample Rate = 0.001/

(2^Resolution/Data clock)

Sample Rate = 0.001/

(2^Resolution/Data clock)

[5]

Differential Nonlinearity -1 +2 LSB For any configuration

Operating Current 275 350 μA Data Clock 2.25 12 MHz Source is chip’s internal main

CLK

oscillator. See device data

sheet for accuracy.

PSRR (Vdd>3.0V) 24 dB PSRR (2.2 < Vdd < 3.0) 30 dB PSRR (2.0 < Vdd < 2.2) 12 dB PSRR (Vdd < 2.0) 0 dB

Input Resistance 1/(500fF*

Data-Clock)

1/(400fF*

Data-Clock)

1/(300fF*

Data-Clock)

Ω Equivalent switched cap input

resistance for 8-, 9-, or 10-bit

resolution.

Document Number: 001-12696 Rev. *D Page 16 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 12. Absolute Maximum Ratings

Symbol Description Conditions Min Typ Max Units

STG

Storage Temperature Hig her storage temperatures reduces data

retention time. Recommended Storage Temperature is +25°C ± 25°C. Extended duration storage temperatures above 85

–55 +25 +125 °C

degrades reliability. Vdd Supply Voltage Relative to Vss –0.5 – +6.0 V V V I

MIO

IO IOZ

DC Input Voltage Vss – 0.5 – Vdd + 0.5 V DC Voltage Applied to Tri-state Vss –0.5 – Vdd + 0.5 V

Maximum Current into any Port Pin –25 – +50 mA ESD Electro Static Discharge Voltage Human Body Model ESD 2000 – – V LU Latch up Current In accordance with JESD78 standard – – 200 mA

Operating Temperature

Table 13. Operating Temperature

Symbol Description Conditions Min Typ Max Units

Ambient Temperature –40 – +85 °C

Operational Die Temperature The temperature rise from ambient to junction

is package specific. Refer the table Thermal

Impedances per Package on page 28. The

–40 – +100 °C user must limit the power consumption to comply with this requirement.

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 14. DC Chip-Level Specifications

Symbol Description Conditions Min Typ Max Units

Vdd Supply Voltage Refer the table DC POR and LVD

Specifications on page 21

DD24

Supply Current, IMO = 24 MHz Conditions are Vdd = 3.0V, TA = 25°C,

CPU = 24 MHz. CapSense running at 12 MHz, no IO sourcing current

DD12

Supply Current, IMO = 12 MHz Conditions are Vdd = 3.0V, TA = 25°C,

CPU = 12 MHz. CapSense running at 12 MHz, no IO sourcing current

DD6

Supply Current, IMO = 6 MHz Conditions are Vdd = 3.0V, TA = 25°C,

CPU = 6 MHz. CapSense running at 6 MHz, no IO sourcing current

SB0

SB1

Deep Sleep Current Vdd = 3.0V, TA = 25°C, IO regulator turned off – 0.1 – μA Standby Current with POR, L VD and

Vdd = 3.0V , TA = 25°C, IO regulator turned off – 1.07 1.5 μA

Sleep Timer

1.71 – 5.5 V

– 2.88 4.0 mA

– 1.71 2.6 mA

– 1.16 1.8 mA

Document Number: 001-12696 Rev. *D Page 17 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

DC General Purpose IO Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and –40°C ≤ T apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 15. 3.0V to 5.5V DC GPIO Specifications

Symbol Description Conditions Min Typ Max Units

OH1

OH2

OH3

OH4

OH5

OH6

OH7

OH8

OH9

OH10

≤ 85°C, 2.4V to 3.0V and –40°C ≤ TA ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Pull up Resistor 4 5.6 8 kΩ High Output Voltage

Port 2 or 3 Pins High Output Voltage

Port 0 or 1 Pins with LDO Regulator

IOH < 10 μA, maximum of 10 mA source current in all IOs

IOH = 1 mA, maximum of 20 mA source current in all IOs

IOH < 10 μA, maximum of 10 mA source current in all IOs

Vdd - 0.2 – – V

Vdd - 0.9 – – V

Vdd - 0.2 – – V

Disabled for Port 1 High Output Voltage

Port 0 or 1 Pins with LDO Regulator

IOH = 5 mA, maximum of 20 mA source current in all IOs

Vdd - 0.9 – – V

Disabled for Port 1 High Output Voltage

Port 1 Pins with LDO Regulator

IOH < 10 μA, Vdd > 3.1V , maximum of 4 IOs all sourcing 5 mA

2.85 3.00 3.3 V

Enabled for 3V Out High Output Voltage

Port 1 Pins with LDO Regulator

IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs

2.20 – – V

Enabled for 3V Out High Output Voltage

Port 1 Pins with LDO Enabled for 2.5V

IOH < 10 μA, Vdd > 2.7V , maximum of 20 mA source current in all IOs

2.35 2.50 2.75 V

Out High Output Voltage

Port 1 Pins with LDO Enabled for 2.5V

IOH = 2 mA, Vdd > 2.7V, maximum of 20 mA source current in all IOs

1.90 – – V

Out High Output Voltage

Port 1 Pins with LDO Enabled for 1.8V

IOH < 10 μA, Vdd > 2.7V , maximum of 20 mA source current in all IOs

1.60 1.80 2.1 V

Out High Output Voltage

Port 1 Pins with LDO Enabled for 1.8V

IOH = 1 mA, Vdd > 2.7V, maximum of 20 mA source current in all IOs

1.20 – – V

Out Low Output Voltage IOL = 25 mA, Vdd > 3.3V, maximum of

––0.75V 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5])

Input Low Voltage – – 0.80 V Input High Voltage 2.00 – V Input Hysteresis Voltage – 80 – mV Input Leakage (Absolute Value) – 0.001 1 μA Pin Capacitance Package and pin depend ent

0.5 1.7 5 pF

Temp = 25°C

Document Number: 001-12696 Rev. *D Page 18 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Table 16. 2.4V to 3.0V DC GPIO Specifications

Symbol Description Conditions Min Typ Max Units

R V

PU OH1

OH2

OH3

Pull up Resistor 4 5.6 8 kΩ High Output Voltage

Port 2 or 3 Pins High Output Voltage

Port 0 or 1 Pins with LDO Regulator

IOH < 10 μA, maximum of 10 mA source current in all IOs

IOH = 0.2 mA, maximum of 10 mA source current in all IOs

IOH < 10 μA, maximum of 10 mA source current in all IOs

Vdd - 0.2 – – V

Vdd - 0.4 – – V

Vdd - 0.2 – – V

Disabled for Port 1

OH4

High Output Voltage Port 0 or 1 Pins with LDO Regulator

IOH = 2 mA, maximum of 10 mA source current in all IOs

Vdd - 0.5 – – V

Disabled for Port 1

OH5A

High Output Voltage Port 1 Pins with LDO Enabled for 1.8V

IOH < 10 μA, Vdd > 2.4V, maximum of 20 mA source current in all IOs

1.50 1.80 2.1 V

Out

OH6A

High Output Voltage Port 1 Pins with LDO Enabled for 1.8V

IOH = 1 mA, Vdd > 2.4V, maximum of 20 mA source current in all IOs

1.20 – – V

Out

Low Output Voltage IOL = 10 mA, maximum of 30 mA sink

current on even port pins (for example,

– – 0.75 V

P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5])

Input Low Volt age – – 0.72 V Input High Voltage 1.4 – V Input Hysteresis Voltage – 80 – mV Input Leakage (Absolute Value) – 0.001 1 μA Capacitive Load on Pins Package and pin dep endent

Temp = 25

0.5

1.7 5 pF

Table 17. 1.71V to 2.4V DC GPIO Specifications

Symbol Description Conditions Min Typ Max Units

R V

PU OH1

OH2

OH3

Pull up Resistor 4 5.6 8 kΩ High Output Voltage

Port 2 or 3 Pins High Output Voltage

Port 0 or 1 Pins with LDO Regulator

IOH = 10 μA, maximum of 10 mA source current in all IOs

IOH = 0.5 mA, maximum of 10 mA source current in all IOs

IOH = 100 μA, maximum of 10 mA source current in all IOs

Vdd - 0.2 – – V

Vdd - 0.5 – – V

Vdd - 0.2 – – V

Disabled for Port 1

OH4

High Output Voltage Port 0 or 1 Pins with LDO Regulator

IOH = 2 mA, maximum of 10 mA source current in all IOs

Vdd - 0.5 – – V

Disabled for Port 1

Low Output Voltage IOL = 5 mA, maximum of 20 mA sink

current on even port pins (for example,

––0.4V

P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5])

Input Low Voltage – – 0.3 x Vdd V Input High Voltage 0.65 x Vdd – V

Document Number: 001-12696 Rev. *D Page 19 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Table 17. 1.71V to 2.4V DC GPIO Specifications (continued)

Symbol Description Conditions Min Typ Max Units

Input Hysteresis Voltage – 80 – mV Input Leakage (Absolute Value) – 0.001 1 μA Capacitive Load on Pins Package and pin dependent

Temp = 25

0.5

1.7 5 pF

Table 18.DC Characteristics – USB Interface

Symbol Description Conditions Min Typ Max Units

Rusbi USB D+ Pull Up Resistance With idle bus 0.900 - 1.575 kΩ Rusba USB D+ Pull Up Resistance While receiving tra ffic 1.425 - 3.090 kΩ Vohusb Static Output High 2.8 - 3.6 V Volusb Static Output Low -0.3V Vdi Differential Input Sensitivity 0.2 - V Vcm Differential Input Common Mode

0.8 - 2.5 V

Range Vse Single Ended Receiver Threshold 0.8 - 2.0 V Cin Transceiver Capacitance - 50 pF Iio Hi-Z State Data Line Leakage On D+ or D- line -10 - +10 μA Rps2 PS/2 Pull Up Resistance 3 5 7 kΩ Rext External USB Series Resistor In series with each USB pin 21.78 22.0 22.22 Ω

DC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 19. DC Analog Mux Bus Specifications

Symbol Description Conditions Min Typ Max Units

GND

The maximum pin voltage for measuring RSW and R

Switch Resistance to Common Analog

Bus

Resistance of Initialization Switch to

Vss

is 1.8V

GND

– – 800 Ω

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 20. DC Comparator Specifications

Symbol Description Conditions Min Typ Max Units

LPC

OSLPC

Low Power Comparator (LPC)

Maximum voltage limited to Vdd 0.0 – 1.8 V

common mode

LPC supply current – 10 40 μA

LPC voltage offset – 2.5 30 mV

Document Number: 001-12696 Rev. *D Page 20 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

DC POR and LVD Specifications

Notes

6. Always greater than 50 mV above V

PPOR1

voltage for falling supply.

7. Always greater than 50 mV above V

PPOR2

voltage for falling supply.

8. Always greater than 50 mV above V

PPOR3

voltage for falling supply.

9. Always greater than 50 mV above V

PPOR0

voltage for falling supply.

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 21. DC POR and LVD Specifications

Symbol Description Conditions Min Typ Max Units

Vdd must be greater than or equal to

1.71V during startup, reset from the XRES pin, or reset from watchdog.

1.61

2.40

2.64

2.85

2.95

3.06

1.84

1.75

4.62

1.66

2.36

–

2.60

2.82

[6] [7] [8]

2.45

2.71

2.92

3.02

3.13

[9]

1.90

1.80

4.73

1.71

2.41

2.66

2.95

2.51

2.78

2.99

3.09

3.20

2.32

1.84

4.83

PPOR0

PPOR1

PPOR2

PPOR3

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

Vdd Value for PPOR Trip PORLEV[1:0] = 00b, HPOR = 0 PORLEV[1:0] = 00b, HPOR = 1 PORLEV[1:0] = 01b, HPOR = 1 PORLEV[1:0] = 10b, HPOR = 1

Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 01 1b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 22. DC Programming Specifications

Symbol Description Conditions Min Typ Max Units

Vdd

DDP

ILP

IHP

ILP

IHP

OLP

OHP

Flash Flash

IWRITE

Supply Voltage for Flash Write

1.71 – – V

Operations Supply Current During

– 5 25 mA

Programming or Verify Input Low Voltage During

Programming or Verify Input High Voltage During

Programming or Verify

See the appropriate DC General Purpose

IO Specifications on page 18

See appropriate DC General Purpose IO

Specifications on page 18 table on pages

– – V

15 or 16

Input Current when Applying Vilp

Driving internal pull down resistor – – 0.2 mA to P1[0] or P1[1] During Programming or Verify

Input Current when Applying Vihp

Driving internal pull down resistor – – 1.5 mA to P1[0] or P1[1] During Programming or Verify

Output Low Voltage During

– – Vss + 0.75 V

Programming or Verify Output High Voltage During

Programming or Verify

Flash Write Endurance Erase/write cycles per block 50,000 – – -

ENPB

Flash Data Retentio n Following maximum Flash write cycles;

See appropriate DC General Purpose IO

Specifications on page 18 table on page

16. For Vdd > 3V use V

page 17.

in T able 13 on

OH4

ambient temperature of 55°C

– Vdd V

10 20 – Years

V V V V

V V V V V V V V

Document Number: 001-12696 Rev. *D Page 21 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 23. AC Chip-Level Specifications

Symbol Description Conditions Min Typ Max Units

MAX

CPU

32K1

IMO24

IMO12

IMO6

DC T

RAMP

XRST

XRST2

IMO

Maximum Operating Frequency 24 – – MHz Maximum Processing Frequency 24 – – MHz Internal Low Speed Oscillator Frequency 19 32 50 kHz Internal Main Oscillator Frequency at 24

22.8 24 25.2 MHz

MHz Setting Internal Main Oscillator Frequency at 12

11.4 12 12.6 MHz

MHz Setting Internal Main Oscillator Frequency at 6

5.7 6.0 6.3 MHz

MHz Setting Duty Cycle of IMO 40 50 60 % Supply Ramp Time 0 – – μs External Reset Pulse Width at Power Up After supply voltage is valid 1 ms External Reset Pulse Width after Power UpApplies after part has booted 10 μs

AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 24. AC GPIO Specifications

Symbol Description Conditions Min Typ Max Units

GPIO

GPIO Operating Frequency Normal Strong Mode Port 0, 1 0

–

6 MHz for

1.71V<Vdd<2.4V

MHz

TRise23 Rise Time, Strong Mode, Cload = 50 pF

Ports 2 or 3

TRise23L Rise Time, Strong Mode Low Supply,

Cload = 50 pF, Ports 2 or 3

TRise01 Rise Time, Strong Mode, Cload = 50 pF

Ports 0 or 1

TRise01L Rise Time, Strong Mode Low Supply,

Cload = 50 pF, Ports 0 or 1

TFall Fall Time, Strong Mode, Cload = 50 pF

All Ports

TFallL Fall Time, Strong Mode Low Supply,

Cload = 50 pF, All Ports

–

12 MHz for

2.4V<Vdd<5.5V

Vdd = 3.0 to 3.6V, 10% – 90% 15 – 80 ns

Vdd = 1.71 to 3.0V, 10% – 90% 15 – 80 ns

Vdd = 3.0 to 3.6V, 10% – 90%

10 – 50 ns

LDO enabled or disabled Vdd = 1.71 to 3.0V, 10% – 90%

10 – 80 ns

LDO enabled or disabled Vdd = 3.0 to 3.6V, 10% – 90% 10 – 50 ns

Vdd = 1.71 to 3.0V, 10% – 90% 10 – 70 ns

Document Number: 001-12696 Rev. *D Page 22 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Figure 11. GPIO T imin g Diagram

TFall

TRise23 TRise01

90%

10%

GPIO Pin

Output

Voltage

TRise23L TRise01L

TFallL

Table 25.AC Characteristics – USB Data Timings

Symbol Description Conditions Min Typ Max Units

Tdrate Full speed data rate Average bit rate 12–0.25% 12 12 + 0.25% MHz Tdjr1 Receiver data jitter tolerance To next transition -18.5 – 18.5 ns Tdjr2 Receiver data jitter tolerance To pair transition -9 – 9 ns Tudj1 Driver differential jitter To next transition -3.5 – 3.5 ns Tudj2 Driver differential jitter To pair transition -4.0 – 4.0 ns Tfdeop Source jitter for differential

To SE0 transition -2 – 5 ns

transition Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – ns Tfst Width of SE0 interval during

–14ns

differential transition

Table 26.AC Characteristics – USB Driver

Symbol Description Conditions Min Typ Max Units

Tr Transition rise time 50 pF 4 – 20 ns Tf Transition fall time 50 pF 4 – 20 ns TR Rise/fall time matching 90.00 – 111.1 % Vcrs Output signal crossover voltage 1.3 – 2.0 V

AC Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 27. AC Low Power Comparator Specifications

Symbol Description Conditions Min Typ Max Units

LPC

Comparator Response Time, 50

mV Overdrive

AC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 28. AC Analog Mux Bus Specifications

Symbol Description Conditions Min Typ Max Units

Switch Rate Maximum pin voltage when measuring

Document Number: 001-12696 Rev. *D Page 23 of 34

50 mV overdrive does not include offset voltage.

switch rate is 1.8Vp-p

100 ns

––6.3MHz

[+] Feedback

CY8C20x36/46/66, CY8C20396

AC External Clock Specifications

SCLK (P1[1])

RSCLK

FSCLK

SDATA (P1[0])

SSCLK

HSCLK

DSCLK

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 29. AC External Clock Specifications

Symbol Description Conditions Min Typ Max Units

OSCEXT

Frequency 0.750 –25.2MHz – High Period 20.6 – 5300 ns – Low Period 20.6 – Power Up IMO to Switch 150

– –ns – – μs

AC Programming Specifications

Figure 12. AC Waveform

The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 30. AC Programming Specifications

Symbol Description Conditions Min Typ Max Units

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

DSCLK2

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Bloc k ) – – 18 ms Flash Block Write Time – – 25 ms Data Out Delay from Falling Edge of SCLK 3.6 < Vdd – – 60 ns Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6 – – 85 ns Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0 – – 130 ns

Document Number: 001-12696 Rev. *D Page 24 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

AC SPI Specifications

SDA

SCL

Sr SP

BUFI2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

Note

10.A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus syste m, but the require ment t

SU;DAT

≥ 250 ns must then be me t. This automatica lly be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

rmax

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 31. AC SPI Specifications

Symbol Description Conditions Min Typ Max Units

SPIM

SPIS

Maximum Input Clock Frequency Selection,

2.4V<Vdd<5.5V

Master Maximum Input Clock Frequency Selection,

Master

(21)1.71V<Vdd<2.4V

Maximum Input Clock Frequency Selection, Slave 2.4<Vdd<5.5V

Maximum Input Clock Frequency Selection,

Output clock frequency is half of input clock rate.

Output clock frequency is half of input clock rate

– – 12 MHz

6 MHz

– – 12 MHz

6 MHz

Slave 1.71V<Vdd<2.4V

Width of SS_ Negated Between Transmissions 50 – – ns

AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 32. AC Characteristics of the I2C SDA and SCL Pins

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After this period, the first clock pulse is

generated. LOW Period of the SCL Clock 4.7 –1.3– μs HIGH Period of the SCL Clock 4.0 –0.6– μs Setup Time for a Repeated START Condition 4.7 –0.6– μs Data Hold Time 0 –0– μs Data Setup Time 250 –100

Standard Mode Fast Mode

Min Max Min Max

4.0 –0.6– μs

–ns

Units

SUSTOI2C

BUFI2C

SPI2C

Document Number: 001-12696 Rev. *D Page 25 of 34

Setup Time for STOP Condition 4.0 –0.6– μs Bus Free Time Between a STOP and START Condition 4.7 –1.3– μs Pulse Width of spikes are suppressed by the input filter. – –050ns

Figure 13. Definition for Timing for Fast/Standard Mode on the I

C Bus

[+] Feedback

CY8C20x36/46/66, CY8C20396

Packaging Information

001-09116 *D

001-13937 *B

This section illustrates the packaging specifications for the CY8C20x36/46/66, CY8C20396 PSoC device, along with the thermal impedances for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Figure 14. 16-Pin Chip On Lead 3x3 mm (Sawn)

Figure 15. 24-Pin (4x4 x 0.6 mm) QFN

Document Number: 001-12696 Rev. *D Page 26 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Figure 16. 32-Pin (5x5 x 0.6 mm) QFN

4. DIMENSIONS ARE IN MILLIMETERS

2. BASED ON REF JEDEC # MO-248

NOTES:

1. HATCH AREA IS SO LDER AB LE EXPO SED PAD

BOTTOM VIEW

TOP VIEW

SIDE VIEW

3. PACKAGE WEIGHT: 0.0388g

001-42168

LQ32

COMPANY CONFIDENTIAL

CYPRESS

TITLE

SIZE

PART NO. DWG NO REV

SEE NOTE 1

32L QFN 5 X 5 X 0.55 M M PACKAGE OU TLINE 3.5 X 3.5 EPAD (SAWN TYPE)

001-42168 *C

51-85061 *C

0.095

0.025

0.008

SEATING PLANE

0.420

0.088

.020

0.292

0.299

0.395

0.092

BSC

0.110

0.016

0.620

0.008

0.0135

0.630

DIMENSIONS IN INCHES MIN.

MAX.

0.040

0.024

0°-8°

GAUGE PLANE

.010

124

25 48

0.004

0.005

0.010

Figure 17. 48-Pin (300 MIL) SSOP

Document Number: 001-12696 Rev. *D Page 27 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Figure 18. 48-Pin (7x7 mm) QFN

001-13191 *C

Notes

11. T

= TA + Power x θJA.

12.To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.

13.Higher temperatures may be required based on the solder melting point. Typical temperatures for sold er are 220 ± 5

C with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications.

Important Notes

■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

■ Pinned vias for thermal conduction are not required for the low power PSoC device.

Thermal Impedances

Table 33. Thermal Impedances per Package

Package

16 QFN 24 QFN 32 QFN

48 SSOP

48 QFN

[12] [12]

[12]

Typical θJA

32.69oC/W

20.90oC/W

19.51oC/W 69oC/W

17.68oC/W

[11]

Solder Reflow Peak Temperature

This table lists the minimum solder reflow peak temperature to achieve good solderability.

Table 34. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature

16 QFN 240oC 260oC 24 QFN 240oC 260oC 32 QFN 240oC 260oC

48 SSOP 220oC 260oC

48 QFN 240oC 260oC

[13]

Maximum Peak Temperature

Document Number: 001-12696 Rev. *D Page 28 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Development Tool Selection

Software

PSoC Designer™

At the core of the PSoC development software suite is PSoC Designer. This is used by thousands of PSoC developers. This robust software is facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at

http://www.cypress.com under DESIGN RESOURCES >>

Software and Drivers.

PSoC Programmer

PSoC Programmer is flexible enough and is used on the b ench in development and is also suitable for factory programming. PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at

http://www.cypress.com/psocprogrammer.

C Compilers

PSoC Designer comes with a free HI-TECH C Lite C compiler. The HI-TECH C Lite compiler is free, supports all PSoC devices, integrates fully with PSoC Designer and PSoC Express, and runs on Windows versions up to 32-bit Vista. Compilers with additional features are available at additional cost from their manufactures.

■ HI-TECH C PRO for the PSoC is available from

http://www.htsoft.com.

■ ImageCraft Cypress Edition Compiler is available from

http://www.imagecraft.com.

Development Kits

All development kits are sold at the Cypress Online Store.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

CY3210-ExpressDK PSoC Express Development Kit

The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules, and more. The kit includes:

■ PSoC Express Software CD

■ Express Development Board

■ Four Fan Modules

■ Two Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

■ USB 2.0 Cable

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

Document Number: 001-12696 Rev. *D Page 29 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Evaluation Tools

All evaluation tools are sold at the Cypress Online Store.

CY3210-MiniProg1

The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Device Programmers

All device programmers are purchased from the Cypress Online Store.

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ Three Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

Document Number: 001-12696 Rev. *D Page 30 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Accessories (Emulation and Programming)

Notes

14.Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

15.Foot kit includes surface mount feet that can be soldered to the target PCB.

16.Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Table 35. Emulation and Programming Accessories

Part Number Pin Package

Flex-Pod Kit

[14]

Foot Kit

CY8C20236-24LKXI 16 QFN CY3250-20266 QFN CY3250-16QFN-RK See note 15 CY8C20336-24LQXI 24 QFN CY3250-20366QFN CY3250-2 0366QFN See note 15 CY8C20436-24LQXI 32 QFN CY3250-20466QF N CY3250-32QFN-RK See note 15 CY8C20396-24LQXI Not Available CY8C20246-24LKXI 16 QFN CY3250-20266 QFN CY3250-16QFN-FK See note 16 CY8C20346-24LQXI 24 QFN CY3250-20366QF N CY3250-24QFN-FK See note 16 CY8C20446-24LQXI 32 QFN CY3250-20466QF N CY3250-32QFN-FK See note 16 CY8C20466-24LQXI 32 QFN CY3250-20466QF N CY3250-32QFN-FK See note 16 CY8C20566-24PVXI 48 SSOP CY3250-20X66 CY3250-48SSOP-FK See note 16 CY8C20666-24LTXI 48 QFN CY3250-20666QFN CY3250-48QFN-FK See note 16

[15]

Adapter

[16]

Third-Party Tools

Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation >> Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/

AN2323.

Document Number: 001-12696 Rev. *D Page 31 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Ordering Information

Notes

17.Dual-function Digital IO Pins also connect to the common analog mux.

The following table lists the CY8C20x36/46/66, CY8C20396 PSoC devices key package features and ordering codes.

Table 36. PSoC Device Key Features and Ordering Information

Package Orderin g Code

Flash

(Bytes)

16-Pin (3x3x0.6mm) QFN CY8C20236-24LKXI 8K 1K 1 13 13 Yes No 16-Pin (3x3x0.6mm) QFN

CY8C20236-24LKXIT 8K 1K 1 13 13 Yes No

(Tape and Reel) 24-Pin (4x4x0.6mm) QFN CY8C20336-24LQXI 8K 1K 1 20 20 Yes No 24-Pin (4x4x0.6mm) QFN

CY8C20336-24LQXIT 8K 1K 1 20 20 Yes No

(Tape and Reel) 32-Pin (5x5x0.6mm) QFN CY8C20436-24LQXI 8K 1K 1 28 28 Yes No 32-Pin (5x5x0.6mm) QFN

CY8C20436-24LQXIT 8K 1K 1 28 28 Yes No

(Tape and Reel) 24-Pin (4x4x0.6mm) QFN CY8C20396-24LQXI 16K 2K 1 19 19 Yes Yes 24-Pin (4x4x0.6mm) QFN

CY8C20396-24LQXIT 16K 2K 1 19 19 Yes Yes

(Tape and Reel) 16 Pin (3x3 x 0.6 mm) QFN CY8C20246-24LKXI 16K 2048 1 13

16 Pin (3x3 x 0.6 mm) QFN

CY8C20246-24LKXIT 16K 2048 1 13

(Tape and Reel) 24 Pin (4x4 x 0.6 mm) QFN CY8C20346-24LQXI 16K 2048 1 20

24 Pin (4x4 x 0.6 mm) QFN

CY8C20346-24LQXIT 16K 2048 1 20

(Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN CY8C20446-24LQXI 16K 2048 1 28

32 Pin (5x5 x 0.6 mm) QFN

CY8C20446-24LQXIT 16K 2048 1 28

(Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN CY8C20466-24LQXI 32K 2048 1 28

32 Pin (5x5 x 0.6 mm) QFN

CY8C20466-24LQXIT 32K 2048 1 28

(Tape and Reel) 48-Pin SSOP CY8C20566-24PVXI 32K 2048 1 36

48-Pin SSOP

CY8C20566-24PVXIT 32K 2048 1 36

(Tape and Reel) 48 Pin (7x7 mm) QFN CY8C20666-24LTXI 32K 2048 1 36

48 Pin (7x7 mm) QFN

CY8C20666-24LTXIT 32K 2048 1 36

(Tape and Reel) 48 Pin (7x7 mm) QFN (OCD)

[4]

CY8C20066-24LTXI 32K 2048 1 36

SRAM

(Bytes)

CapSense

Blocks

Digital IO

Pins

Analog

Inputs

[17]

XRES

Yes No Yes No

Yes Yes Yes Yes

Yes Yes

USB

Document Number: 001-12696 Rev. *D Page 32 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Document History Page

Document Title: CY8C20x36/46/66, CY8C20396 CapSenseTM Applications Document Number: 001-12696

Revision ECN Origin of Change Submission Date Description of Change

** 766857 HMT See ECN New silicon and document (Revision **). *A 1242866 HMT See ECN Add features. Update all applicable sections. Update specs.

Fix 24-pin QFN pinout moving pins inside. Update package revisions. Update and add to Emulation and Programming Accessories table.

*B 2174006 AESA See ECN Added 48-Pin SSOP Part Pinout

Modified symbol R Specification Added footnote in Table DC Analog Mux Bus Specification Added 16K FLASH Parts. Updated Notes, Package Diagrams and Ordering Information table. Updated Thermal Impedance and Solder Reflow tables

*C 2587518 TOF/JASM/MNU/

HMT

10/13/08 Converted from Preliminary to Final

Fixed broken links. Updated data sheet template. Added operating voltage ranges with USB ADC resolution changed from 10-bit to 8-bit Included ADC specifications table Included Comparator specification table Included Voh7, Voh8, Voh9, Voh10 specs Flash data retention – condition added to Note Input leakage spec changed to 1 μA max GPIO rise time for ports 0,1 and ports 2,3 made common AC Programming specifications updated Included AC Programming cycle timing diagram AC SPI specification updated The VIH for 3.0<Vdd<2.4 changed to 1.6 from 2.0 Added USB specification Added SPI CLK to P1[0] Updated package diagrams Updated thermal impedances for QFN packages Updated F Updated voltage ranges for F

GPIO

Update Development Tools, add Designing with PSoC Designer. Edit, fix links, notes and table format. Update R formula, fix TRise parameter names in GPIO figure, fix Switch Rate note. Update maximum data in Table 20. DC POR and LVD Specifications.

*D 2649637 SNV/AESA 03/17/2009 Changed title to “CY8C20x36/46/66, CY8C20396

CapSense™ Applications”. Updated data sheet Features, pin information, and ordering information sections. Updated package diagram 001-42168 to *C.

VDD

to R

in Table DC Analog Mux Bus

GND

parameter in Table 23

and F

SPIM

in Table 30

SPIS

Document Number: 001-12696 Rev. *D Page 33 of 34

[+] Feedback

CY8C20x36/46/66, CY8C20396

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb

CapSense™, PSoC Designer™, and Progr ammable System-on-C hip™ are trademar ks and PSoC® is a reg istered trademark o f Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.

© Cypress Semiconductor Corporation, 2007- 2009. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress pro d ucts ar e not war ran t ed no r int end ed to be used fo r medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express written agre em en t with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify , create d erivative works of , and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cy press integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-12696 Rev. *D Revised March 17, 2009 Page 34 of 34

[+] Feedback

Cypress CapSense CY8C20396, CapSense CY8C20x36, CapSense CY8C20x46, CapSense CY8C20x66 Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual