Cypress AN220224 User Manual
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to oer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon oers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
www.cypress.com Document Number: 002-20224 Rev. *B 1
AN220224
How to Use Timer, Counter, and PWM (TCPWM) in Traveo II Family
Author: Masahiro Niimi
Associated Part Family: Traveo™ II Family CYT2/CYT3/CYT4 Series
Related Application Notes: see Related Documents
This application note describes how to use Timer, Counter, and Pulse Width Modulator (TCPWM) in Cypress
Traveo II Family MCUs. The TCPWM is a multifunctional timer component that supports several functional modes. The
application note explains how to configure TCPWM.
Contents
1 Introduction .................................................................. 1
1.1 Features .............................................................. 1
1.2 Block Diagram ..................................................... 2
2 Operation Overview ..................................................... 3
2.1 Configuring Counter in TCPWM .......................... 3
2.2 Selecting Clock for Counter ................................ 3
3 TCPWM Operation Examples...................................... 5
3.1 Timer Mode ......................................................... 5
3.2 Capture Mode ..................................................... 7
3.3 PWM Mode ......................................................... 9
3.4 PWM Dead Time (PWM_DT) Mode .................. 11
3.5 Relation of Trigger Multiplexer .......................... 13
4 Glossary .................................................................... 14
5 Related Documents ................................................... 15
Document History............................................................ 16
Worldwide Sales and Design Support ............................. 17
1 Introduction
This application note describes how to use TCPWM in Cypress Traveo II family MCUs.
The CYT2 series has one Arm® Cortex®-M4F-based CPU (CM4) and one Cortex-M0+-based CPU (CM0+). The CYT4
series has two Arm Cortex-M7-based CPUs (CM7) and one CM0+, and The CYT3 series has one Arm CM7 and one
CM0+.
TCPWM is a multifunctional counter component, which supports several functional modes.
TCPWM counter width is 16-bit or 32-bit. In addition, 16-bit counters support special functions optimized for Motor
Control.
See the device datasheet for the number of TCPWM channels available for each device.
This application note explains the functioning of TCPWM in the series, initial configuration, and several functional modes
with use cases.
To understand the functionality described and terminology used in this application note, see the “Timer, Counter, and
PWM” chapter of the Architecture Technical Reference Manual (TRM).
1.1 Features
Table 1 shows the TCPWM function modes.
Table 1. TCPWM Function Modes
Mode
Description
Timer
Counter increments or decrements by every counter clock cycle in which a count event is detected.
Capture
Counter increments or decrements by every counter clock cycle in which a count event is detected. A
capture event copies the counter value into the capture register.
How to Use Timer, Counter, and PWM (TCPWM) in Traveo II Family
www.cypress.com Document Number: 002-20224 Rev. *B 2
Mode
Description
QUAD
Quadrature decoding. Counter is decremented or incremented based on two phases according to X1, X2,
X4 or up/down rotary encoding scheme. Quadrature mode will have four sub-modes to move the counter
between 0 and PERIOD or between 0x8000 and 0x0000/0xffff in combination with compare or capture
functionality.
PWM
Pulse width modulation with clock pre-scaling.
PWM_DT
Pulse width modulation with dead time.
PWM_PR
Pseudo-random PWM using 16- or 32-bit Linear Feedback Shift Register (LFSR) with programmable length
to generate pseudo-random noise.
SR
Shift Register functionality shifts the counter value in the right direction. The capture0 input is used to
generate the MSB of the next counter value. The line output signal is driven from a programmable tab of the
shift register (counter).
Each counter supports multiple function modes. At any time, a single counter is operating in one mode. Different
counters can operate in different modes.
See the Timer, Counter, and PWM chapter of the Architecture TRM for more details.
1.2 Block Diagram
Figure 1 shows a simplified TCPWM block diagram.
Figure 1. TCPWM Block Diagram
Trigger
Synchronization
Counter Group
Event
Generation
16-bit or 32-bit counter
Configuration
Register
Counter
1
2 ...
1
2
...
Trigger inputs
Trigger outputs:
tr_out0
tr_out1
interrupt
line_out
line_compl_out
For each
Counter
TCPWM consists of Trigger Synchronization and Counter Group. Each Counter Group consists of counters, and each
counter consists of Event Generation, 16-bit or 32-bit counter, and a Configuration Register.
Each counter has two trigger outputs (tr_out0, tr_out1), two line outputs (line_out, line_compl_out), and one interrupt.
16-bit counter has an additional option for Motor Control. This counter has functions which are optimized for motor
control operations.
Event Generation generates counter events for 16-bit or 32-bit counter as Reload, Start, Stop, Count, and Capture
event. Those events can relate to Trigger inputs.
The trigger input is synchronized by the Trigger Synchronization block and input to the Counter block.
Several trigger inputs are connected to TCPWM. Those trigger inputs are GPIO ports, SAR ADC Range violation
detected, constant 0 and 1, and general triggers output from Trigger Multiplexer.
How to Use Timer, Counter, and PWM (TCPWM) in Traveo II Family
www.cypress.com Document Number: 002-20224 Rev. *B 3
See the "Trigger Multiplexer” chapter of the Architecture TRM for more details.
Figure 2 shows a TCPWM and Clock supplied block diagram.
Figure 2. TCPWM and Clock
TCPWM
Divider
(1-256)
Peripheral
Clock Dividers
clk_counter
CLK_GR3
CLK_PERI
System clock for TCPWM is in group 3, which is supplied from CLK_PERI through the Divider to CLK_GR3. This
clock is used in Trigger Synchronization.
Counter clock for each counter in TCPWM is supplied from CLK_PERI through the Peripheral Clock Dividers to
clk_counter.
See the Clocking System chapter of the Architecture TRM for more details.
2 Operation Overview
2.1 Configuring Counter in TCPWM
1. Select the clock for the counter.
Configure a clock divider and select a clock for each counter.
2. Configure counter.
Configure relating registers.
Select a mode, set up a counter configuration such a counter period and counter direction.
3. Enable counter.
4. Start counter with this configuration.
2.2 Selecting Clock for Counter
Before enabling the counter, a clock should be selected for a counter. This clock is generated by Peripheral Clock
Dividers.
Figure 3 shows Peripheral Clock Dividers block diagram.
How to Use Timer, Counter, and PWM (TCPWM) in Traveo II Family
www.cypress.com Document Number: 002-20224 Rev. *B 4
Figure 3. Peripheral Clock Dividers
8.0 divider 8.0 divider 8.0 divider
CLOCK_CTL[32]
CLK_PERI
DIV_CMD
Enable Selected Divider
Peripheral Clock Dividers
Group0
Counter1
CLOCK_CTL[31]
Group0
Counter0
Group0
Counter2
CLOCK_CTL[33]
CLOCK_CTL[107]
Group2
Counter1
CLOCK_CTL[106]
Group2
Counter0
.. .. ..
16.0 divider 16.0 divider 16.0 divider
.. .. ..
24.5 divider 24.5 divider 24.5 divider
.. .. ..
clk_counter
clk_counter
clk_counter
clk_counter
clk_counter
TCPWM
.. .. ..
...
...
#0 #1 #l
#0 #1 #m
#0 #1 #n
PERI_DIV_24_5_CTL
PERI_DIV_16_CTL
PERI_DIV_8_CTL
Peripheral clock dividers include three types of dividers: 8-bit divider (8.0 divider), 16-bit divider (16.0 divider), and
24.5-bit divider (24.5 divider). See the device datasheet for the number of each divider channels available for each
device.
Each divider makes a clock to divide clock CLK_PERI. 8-bit divider can divide CLK_PERI by 1 to 28 and 16-bit divider
can divide CLK_PERI by 1 to 216. And 24.5-bit divider is a divider which has 24 integer bits and 5 fractional bits.24-5bit
divider can divide CLK_PERI by 1 to 224 for integer and 1 to 25 for fractional.
That is, some counters run at the same clock frequency while another counter runs at a different clock frequency.
The following is an example for configuring peripheral clock dividers. This example shows the generation of three types
of clock frequencies: 40 MHz, 20 MHz, and 16 MHz. The source of those clocks is CLK_PERI 80 MHz.
1. Select the divider and set the divide number.
PERI_DIV_8_CTL_0.INT8_DIV = 1 /* set DVI_8[0] divider to 2. 80 MHz/2 = 40 MHz */
PERI_DIV_8_CTL_0.EN = 1
PERI_DIV_8_CTL_1.INT8_DIV = 3 /* set DVI_8[1] divider to 4. 80 MHz/4 = 20 MHz */
PERI_DIV_8_CTL_1.EN = 1
PERI_DIV_8_CTL_2.INT8_DIV = 4 /* set DVI_8[2] divider to 5. 80 MHz/5 = 16 MHz */
PERI_DIV_8_CTL_2.EN = 1
2. Enable the dividers.
PERI_DIV_CMD.DIV_SEL = 0 /* select divider number 0 */
PERI_DIV_CMD.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI_DIV_CMD.ENABLE = 1 /* enable DIV_8[0] */
PERI_DIV_CMD.DIV_SEL = 1 /* select divider number 1 */
PERI_DIV_CMD.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI_DIV_CMD.ENABLE = 1 /* enable DIV_8[1] */
How to Use Timer, Counter, and PWM (TCPWM) in Traveo II Family
www.cypress.com Document Number: 002-20224 Rev. *B 5
PERI_DIV_CMD.DIV_SEL = 2 /* select divider number 2 */
PERI_DIV_CMD.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI_DIV_CMD.ENABLE = 1 /* enable DIV_8[2] */
Following shows an example where the counter in TCPWM selects a clock configured in the peripheral clock
dividers example.
16-bit counter group0 counter0 selects a 16 MHz clk_counter clock, 16-bit counter group0 counter1 and counter2
select 20 MHz clk_counter clock, and 32-bit counter gropup2 counter0 to counter1 select 40 MHz clk_counter clock.
3. Select a clk_counter clock for each counter in TCPWM.
PERI _CLOCK_CTL_31.DIV_SEL = 0 /* select divider number 0 */
PERI _CLOCK_CTL_31.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI _CLOCK_CTL_32.DIV_SEL = 1 /* select divider number 1 */
PERI _CLOCK_CTL_32.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI _CLOCK_CTL_33.DIV_SEL = 1 /* select divider number 1 */
PERI _CLOCK_CTL_33.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI _CLOCK_CTL_106.DIV_SEL = 2 /* select divider number 2 */
PERI _CLOCK_CTL_106.TYPE_SEL = 0 /* select divider type DIV_8 */
PERI _CLOCK_CTL_107.DIV_SEL = 2 /* select divider number 2 */
PERI _CLOCK_CTL_107.TYPE_SEL = 0 /* select divider type DIV_8 */
The output of the peripheral clock divider, clk_counter clock, has a unique number for each peripheral module. The
counter in TCPWM has a unique counter number. Table 2 shows the counter number in TCPWM of CYT2B7 series.
Regarding other series, see the device datasheet for Peripheral Clocks.
Table 2. CYT2B7 Series: Counter Number in TCPWM
Clock Number
Description
31:93
TCPWM group #0, 16-bit counter #0 to #62 (63 ch)
94:105
TCPWM group #1, 16-bit counter for motor #0 to #11 (12 ch)
106:109
TCPWM group #2, 32-bit counter #0 to #3 (4 ch)
3 TCPWM Operation Examples
3.1 Timer Mode
This section describes how to set up Timer Mode.
Timer Mode is for a basic counter application. This is ordinary counter usage to count the clock for timer.
The following are the different modes of counters based on the direction:
▪
COUNT_UP: Counting mode in the upward direction
▪
COUNT_DOWN: Counting mode in the downward direction
▪
UPDOWN-COUNTER1 and UPDOWN-COUNTER2: Counting mode in the upward and downward directions
Figure 4 shows Timer Mode in upward counting mode.
Loading...