Contents
1 Introduction .................................................................. 1
1.1 Features .............................................................. 2
1.2 Block Diagram ..................................................... 3
2 Operation Overview ..................................................... 5
2.1 Disable/Enable P-DMA/M-DMA .......................... 5
2.2 Configure Channel .............................................. 5
2.3 Configure Descriptor ........................................... 6
2.4 Disable/Enable P-DMA/M-DMA Channel .......... 12
3 P-DMA Use Cases .................................................... 12
3.1 1D Transfer (Memory-to-Peripheral) ................. 12
3.2 1D Transfer (Peripheral-to-Memory) ................. 14
3.3 Descriptor Chaining .......................................... 15
3.4 2D Transfer (Peripheral-to-Memory) ................. 18
3.5 CRC Transfer .................................................... 19
4 M-DMA Use Case ..................................................... 21
4.1 Memory-to-Memory (Memory Copy) ................. 21
5 Glossary .................................................................... 23
6 Related Documents ................................................... 24
Document History ............................................................ 25
Worldwide Sales and Design Support ............................. 26
1 Introduction
This application note describes how to use the Direct Memory Access (DMA) Controller in Cypress Traveo II family
MCUs.
DMA controllers can seamlessly transfer data between memory and on-chip peripherals, or between memories without
CPU intervention. This allows the CPU to handle other tasks while the DMA controller transfers data.
Both P-DMA and M-DMA have multiple independent DMA channels. Each DMA channel has a separate DMA request
input that initiates the transaction and can independently transfer data. See the device datasheet for the number of
DMA channels available for each device.
This series supports two types of DMA controllers: Peripheral DMA (P-DMA) and Memory DMA (M-DMA). P-DMA is
used for peripheral-to-memory and memory-to-peripheral low-latency data transfers for many channels. M-DMA is used
for memory-to-memory high-memory-bandwidth data transfer for a small number of channels.
These DMA controllers have a descriptor that specifies the transfer operation, and it corresponds flexibly to various
applications. Descriptors can be chained; it is possible to have circular lists.
This application note explains the functioning of DMA controllers in the series, initial configuration, and data transfer
operations with use cases.
To understand the functionality described and terminology used in this application note, see the “Direct Memory Access”
chapter of the Architecture Technical Reference Manual (TRM).