Cypress AN220191 User Manual

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www.cypress.com Document Number. 002-20191 Rev. *D 1
AN220191
How to Use Direct Memory Access (DMA) Controller in Traveo II Family
Author: Hitoshi Ogawa
Associated Part Family: Traveo II Family CYT2/CYT3/CYT4 Series
Related Application Notes: See Related Documents
This application note describes how to use DMA controllers (P-DMA and M-DMA) in Cypress Traveo II Family MCUs. DMA controllers can transfer data from a source to a destination without CPU intervention. The application note illustrates how to configure DMA for peripheral-to-memory, memory-to-peripheral, and memory-to-memory data transfers.
Contents
1 Introduction .................................................................. 1
1.1 Features .............................................................. 2
1.2 Block Diagram ..................................................... 3
2 Operation Overview ..................................................... 5
2.1 Disable/Enable P-DMA/M-DMA .......................... 5
2.2 Configure Channel .............................................. 5
2.3 Configure Descriptor ........................................... 6
2.4 Disable/Enable P-DMA/M-DMA Channel .......... 12
3 P-DMA Use Cases .................................................... 12
3.1 1D Transfer (Memory-to-Peripheral) ................. 12
3.2 1D Transfer (Peripheral-to-Memory) ................. 14
3.3 Descriptor Chaining .......................................... 15
3.4 2D Transfer (Peripheral-to-Memory) ................. 18
3.5 CRC Transfer .................................................... 19
4 M-DMA Use Case ..................................................... 21
4.1 Memory-to-Memory (Memory Copy) ................. 21
5 Glossary .................................................................... 23
6 Related Documents ................................................... 24
Document History ............................................................ 25
Worldwide Sales and Design Support ............................. 26

1 Introduction

This application note describes how to use the Direct Memory Access (DMA) Controller in Cypress Traveo II family MCUs.
DMA controllers can seamlessly transfer data between memory and on-chip peripherals, or between memories without CPU intervention. This allows the CPU to handle other tasks while the DMA controller transfers data.
Both P-DMA and M-DMA have multiple independent DMA channels. Each DMA channel has a separate DMA request input that initiates the transaction and can independently transfer data. See the device datasheet for the number of DMA channels available for each device.
This series supports two types of DMA controllers: Peripheral DMA (P-DMA) and Memory DMA (M-DMA). P-DMA is used for peripheral-to-memory and memory-to-peripheral low-latency data transfers for many channels. M-DMA is used for memory-to-memory high-memory-bandwidth data transfer for a small number of channels.
These DMA controllers have a descriptor that specifies the transfer operation, and it corresponds flexibly to various applications. Descriptors can be chained; it is possible to have circular lists.
This application note explains the functioning of DMA controllers in the series, initial configuration, and data transfer operations with use cases.
To understand the functionality described and terminology used in this application note, see the “Direct Memory Access chapter of the Architecture Technical Reference Manual (TRM).
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1.1 Features

Table 1 compares P-DMA with M-DMA, which have similar registers and descriptor structures.
Table 1. P-DMA/M-DMA Features
Feature
P-DMA
M-DMA
Focuses on
Low latency
High memory bandwidth
Useful for
Transfer between peripheral and memory
Transfer between memories
Transfer engine
Shared all channels
Dedicated for each channel
Transfer size
8-bit, 16-bit, 32-bit
8-bit, 16-bit, 32-bit
Channel priority
Four levels Preemptable
Four levels
Descriptor Type
Single transfer 1D / 2D transfer CRC transfer
Single transfer 1D/2D transfer Memory copy Scatter
Descriptor
Source and destination address Transfer size Descriptor type Trigger-in type (four types) Trigger-out type (four types) Interrupt type (four types) Descriptor chaining
Source and destination address Transfer size Descriptor type Trigger-in type (four types) Trigger-out type (four types) Interrupt type (four types) Descriptor chaining
Trigger input
Hardware trigger Software trigger Trigger output (tr_out)
Software trigger Trigger output (tr_out)
P-DMA can be also used for transfers between memories, but the transfer bandwidth may not be enough when compared with M-DMA. M-DMA can also be used for transfers between memory and peripherals, but the transfer latency may not be low when compared with P-DMA.
In P-DMA, when preemptable, a higher-priority pending channel can preempt the current channel between single transfers. M-DMA does not have the preemptable functionality because it would degrade the overall memory bandwidth.
The descriptor determines the DMA transfer specification. The descriptor type determines the type of DMA transfer operation. Both DMAs support single transfer, 1D transfer, and 2D transfer as descriptor types. In addition, P-DMA supports CRC transfer, while M-DMA supports memory copy and scatter. See Section 2.3.1 for details of each descriptor type. Descriptors can be chained by storing the pointer of the next descriptor in the current descriptor. A descriptor chain is also referred to as a descriptor list.
Trigger inputs such as hardware trigger, software trigger, and trigger output (tr_out) are input via the trigger multiplexer, which is a peripheral function outside DMA. The trigger multiplexer routes triggers from potential sources to destinations. See the “Trigger Multiplexer” chapter of the Architecture TRM for more details.
P-DMA supports hardware trigger, software trigger, and trigger output (tr_out) as trigger inputs, while M-DMA supports only software trigger and trigger output (tr_out). See the device datasheet for hardware triggers available. The software trigger is implemented by the trigger multiplexer function. Both DMAs can use the trigger output as their own input trigger. See Section 2.3.2 for each trigger functionality.
How to Use Direct Memory Access (DMA) Controller in Traveo II Family
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1.2 Block Diagram

Figure 1 shows the P-DMA block diagram.
Figure 1. P-DMA Block Diagram
P-DMATrigger
Multiplexer
tr_in[]
Pending Triggers
Priority
Decoder
Data Transfer Engine
Bus Master I/FBus
Slave I/F
MMIO
Registers
Interrupt
Logic
Status Control
tr_out[]
Interrupts[]
Memory
Hardware Triggers
CH 1
CH 0
CH n
tr_in[0] tr_in[1]
tr_in[n]
・ ・ ・
・ ・ ・
Software Triggers
P-DMA consists of channels (CH0 – CHn), a pending trigger block, priority decoder, data transfer engine, and the interrupt logic. The P-DMA transfer engine is shared by all channels. See the Architecture TRM for details of each block.
As mentioned earlier, P-DMA trigger inputs can be a hardware trigger, software trigger, or trigger output (tr_out). These triggers are input via the trigger multiplexer.
The trigger output (tr_out) can be used as its own trigger input, or it can be used as the trigger input to trigger different transfers of other channels.
The memory that is used to store descriptors is outside the DMA block. When the transfer engine activates the next pending channel, the transfer engine reads the descriptor corresponding to the channel from the memory and starts the transfer.
Figure 2 shows M-DMA block diagram.
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Figure 2. M-DMA Block Diagram
M-DMA
Pending Trigger
Channel Logic
Priority
Decoder
Bus Master
I/F
Data Transfer
Engine
Bus Slave I/F MMIO Registers
Channel Logic
Channel Logic
……...
Memory
Trigger
Multiplexer
tr_in[]
Software Triggers
tr_in[0]
tr_in[1]
tr_in[CH_NR-1]
Channel State
Interrupt
Logic
Interrupts[]
tr_out[]
The M-DMA block consists of the channel logic, priority decoder, and registers. The channel logic itself stores the pending trigger and hosts the current channel state and data transfer engine. M-DMA has transfer engines dedicated for each channel. See the Architecture TRM for details of each block.
As trigger inputs, M-DMA supports software trigger and its own trigger output (tr_out). These trigger inputs are input via the trigger multiplexer. Note that unlike P-DMA, M-DMA does not support hardware triggers.
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2 Operation Overview

Figure 3 shows how to configure P-DMA and M-DMA.
Figure 3. General Configuration of P-DMA/M-DMA
Start
Disable P-DMA/M-DMA
Configure Channel
Configure Descriptor
Enable P-DMA/M-DMA
End
Enable P-DMA/M-DMA Channel
Enable peripherals for triggering
DMAs
Is setting of all channel to be used completed ?
Yes
No
In this example, channel, descriptor, and channel enable are configured for each channel. It is also possible to configure all channels to be used within each step.
A peripheral trigger is required after setting the corresponding DMA channel.

2.1 Disable/Enable P-DMA/M-DMA

P-DMA and M-DMA can be enabled/disabled using the respective bits as shown in Table 2. The default setting after reset is ‘0’ (Disabled).
Table 2. P-DMA/M-DMA Disable/Enable
DMA Type
Register (Bit)
Description
P-DMA
DW_CTL.ENABLED (bit31)
0: Disable, 1: Enable
M-DMA
DMAC_CTL.ENABLED (bit31)
0: Disable, 1: Enable

2.2 Configure Channel

In this step, P-DMA/M-DMA channel settings such as the channel priority and pointer address of the descriptor corresponding to the channel are configured.
In addition, in P-DMA, the preemptable function and CRC calculation mode for CRC transfer are configured, if necessary.
See Section 2.1 for more details
See Section 2.2 for more details
See Section 2.1 for more details
See Section 2.3 for more details
See Section 2.4 for more details
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Table 3 and Table 4 show the registers that are used for configuring a channel in P-DMA and M-DMA, respectively.
The registers corresponding to the channel number are configured. See the Architecture TRM and Registers Technical
Reference Manual (Registers TRM) for more details.
Table 3. Channel Configuration for P-DMA
Register (Bit)
Description
DW_CH_STRUCT_CH_CURR_PTR
Sets the channel current descriptor pointer. Software needs to initialize this register.
DW_CH_STRUCT_CH_CTL.PREEMPTABLE (bit11)
Specifies whether the channel is preemptable.
DW_CH_STRUCT_CH_CTL.PRIO (bit9:8)
Sets the channel priority.
DW_CH_STRUCT_CH_IDX.X_IDX (bit7:0)
Sets the X indices of the channel into the current descriptor. Software needs to initialize this register.
DW_CH_STRUCT_CH_IDX_Y_IDX (bit15:0)
Sets the Y indices of the channel into the current descriptor. Software needs to initialize this register.
Required only for CRC transfer:
DW_CRC_CTL.DATA_REVERSE (bit0)
Specifies the bit order (MSb or LSb first) in which a data byte is processed.
DW_CRC_CTL.REM_REVERSE (bit8)
Specifies whether the remainder is bit reversed.
DW_CRC_DATA_CTL.DATA_XOR (bit7:0)
Sets the byte mask with which each data byte is XORed. You can choose this 8-bit value randomly.
DW_CRC_POL_CTL.POLYNOMIAL
Sets the CRC polynomial.
DW_CRC_LFSR_CTL.LFSR32
Sets the seed value for CRC calculation.
DW_CRC_REM_CTL.REM_XOR
Sets a mask with which the CRC_LFSR_CTL.LFSR32 register is XORed.
Table 4. Channel Configuration for M-DMA
Register (Bit)
Description
DMAC_CH_CH_CURR_PTR
Sets the channel current descriptor pointer. Software needs to initialize this register.
DMAC_CH_CH_CTL.PRIO (bit9:8)
Sets the channel priority.

2.3 Configure Descriptor

In this step, the descriptor is configured. The descriptor specifies the DMA channels transfer details. A descriptor is stored in the memory outside DMA and read by the transfer engine. The transfer engine transfers the data according to the descriptor. The descriptor pointer position for each channel is stored in the descriptor pointer register (see Section 2.2).
Figure 4 shows the descriptor structure for P-DMA and M-DMA. The P-DMA descriptor consists of six 32-bit words,
while the M-DMA descriptor consists of eight 32-bit words. However, descriptors of both DMAs have similar functions.
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Figure 4. P-DMA/M-DMA Descriptor Structure
Descriptor Control
Descriptor Pointer +00
Source Address
+04
Destination Address
+08
X Loop Control
+0c
Y Loop Control
+10
Descriptor Next Pointer
+14
Descriptor 0
Descriptor Control
Descriptor Pointer +00
Source Address
+04
Destination Address
+08
X Loop Count
+0c
Y Loop Count
+10
+14
Descriptor next pointer
X Loop Control
Y Loop Control
+18
+1c
M-DMA Descriptor
Structure
P-DMA Descriptor
Structure
Configure Descriptor Parameters
Descriptor control: This word describes DMA parameters such as descriptor type, transfer size, trigger-in/out, and interrupt setting.
Source address and destination address: These words specify the base addresses of the source and destination locations.
X loop control and X loop count: These words control the loop in 1D transfer or the inner loop in 2D transfer. The X loop control specifies the increment of the source and destination addresses for each X loop iteration. The X loop count specifies the number of iterations of the X loop.
Y loop control and Y loop count: These words control the outer loop in 2D transfer. The Y loop control specifies the increment of the source and destination addresses for each Y loop iteration. The Y loop count specifies the number of iterations of the Y loop.
Descriptor next pointer: This word specifies the address of the next descriptor. Descriptors can be chained by storing the descriptor of the next pointer in the current descriptor. The last descriptor in the descriptor list has 0 (NULL) in this word.
See the Architecture TRM and Registers TRM for descriptor details. The number of descriptor words used varies depending on the descriptor type. A word address is shifted forward if
there is any unused descriptor word.
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2.3.1 Descriptor Type

This section explains the descriptor type, which determines the type of DMA transfer. P-DMA has four descriptor types, and M-DMA has five descriptor types. The number of descriptor words used varies
depending on the descriptor type. Table 5 shows each descriptor type. In Table 5, the Transfer Example column shows the outline and pseudocode of each descriptor type. The Using Descriptor column shows the descriptor word used by the descriptor types in each DMA. Note that a word address is shifted forward if there is any unused descriptor word.
Table 5. P-DMA/M-DMA Transfer Example and Using Descriptor for Each Descriptor Type
Descriptor
Type
Transfer Example
Using Descriptor
P-DMA
M-DMA
Single transfer
This transfers a single data element:
DST_ADDR = (DATA_SIZE) SRC_ADDR
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop control
Y(Outer) Loop control
Next descriptor pointer
+0c
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop Count
Y(Outer) Loop Count
+0c
Next descriptor pointer
X(Inner) Loop control
Y(Outer) Loop control
1D transfer
One-dimensional “for loop” transfer:
for (X_IDX =0; X_IDX <= COUNT; X_IDX++) {
DST_ADDR[DST_INCR] = (DATA_SIZE) SRC_ADDR[SRC_INCR]
}
*DST_INCR/SRC_INCR depend on X_INCR DST_ADDR
= (DATA_SIZE) SRC_ADDR
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop control
+0c
Y(Outer) Loop control
+10
Next descriptor pointer
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop Count
+0c
Y(Outer) Loop Count
+10
Next descriptor pointer
X(Inner) Loop control
Y(Outer) Loop control
2D transfer
Two-dimensional “for loop” transfer:
for (Y_IDX =0; Y_IDX <= Y_COUNT; Y_IDX++) {
for (X_IDX =0; X_IDX <= X_COUNT; X_IDX++) {
DST_ADDR[DST_INCR] = (DATA_SIZE) SRC_ADDR[SRC_INCR]
}
}
*DST_INCR/SRC_INCR depend on X/Y_INCR
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop control
+0c
Y(Outer) Loop control
+14
Next descriptor pointer
+10
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop Count
+0c
Y(Outer) Loop Count
Next descriptor pointer
X(Inner) Loop control
Y(Outer) Loop control
+10
+14
+18
+1c
CRC transfer
Calculate CRC of the specified area.
Note that for CRC transfer, CRC must be configured with memory mapped I/O (MMIO) registers.
Descriptor control
+00
Source Address
+04
Destination address
+08
X(Inner) Loop control
+0c
Y(Outer) Loop control
+10
Next descriptor pointer
Not supported
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