Cypress AN220152 User Manual
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to oer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon oers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
www.cypress.com Document Number: 002-20152 Rev. *C 1
AN220152
How to Retain RAM Data in Reset Procedure and Low-Power Mode Transition in
Traveo II Family
Author: Masahide Karino
Associated Part Family: Traveo™ II Family CYT2/CYT3/CYT4 Series
Related Documents: see Related Documents
AN220152 explains the procedure to ensure RAM retention in Traveo™ II Family MCU when a software reset or lowpower mode transition occurs.
1 Introduction
This application note describes the procedure for reset and low-power mode transitions in Cypress Traveo II family
CYT2/CYT3/CYT4 series devices to ensure RAM retention.
In these devices, a reset is performed asynchronously regardless of the RAM access status. Thus, if a reset occurs
during operation, the RAM data might be lost. In addition, if the device power mode transitions from active to low-power,
you should follow the appropriate procedure for RAM retention. This document describes the procedures to ensure
RAM data retention after a software reset or low-power mode transition. However, in Hibernate mode, the RAM data
cannot be retained. Therefore, the RAM data should be transferred to the application flash once. After returning to
Active mode, it is necessary to return the RAM data from the application flash to RAM. In this case, the transition data
is defined as backup memory data.
To understand the functionality described and terminology used in this application note, refer to the “SRAM
Interface” and “Work Flash” chapter of the Architecture Technical Reference Manual (TRM).
2 RAM Retention Procedure Overview
2.1 Reset Procedure
Figure 1 shows the flow of RAM retention when a reset occurs. This example shows the case of retaining RAM0 data.
Figure 1. Example of RAM0 Retention Procedure
Start
End
CPUSS_RAM0_PWR_MACRO_CTLx
- PWR_MODE: RETAINED
CPUSS_RAM0_STATUS
- WB_EMPTY: Wait until the WB_EMPTY bit becomes ’1'
'0': Write buffer NOT empty.
'1': Write buffer empty.
Set RETAINED Mode
Write Buffer Empty?
No
Yes
Check BOD
Check BOD reset cause
- SRSS_RES_CAUSE: RESET_BODVDDD
Set Software Reset
Reset release
Set software reset
- CM0P_SCS_AIRCR.SYSRESETREQ=‘1’
First, in the case of RAM0, check the write buffer status of the WB_EMPTY bit of the CPUSS_RAM0_STATUS register.
The WB_EMPTY bit indicates whether there is any data in the write buffer or it is empty.
How to Retain RAM Data with Software Reset and Low-Power Mode Transition in Traveo II Family
www.cypress.com Document Number: 002-20152 Rev. *C 2
In CYT2 series MCU, ECC is added to the 32-bit data. Thus, if a partial AHB-Lite writing (8-bit/16-bit) occurs to the
RAM, the missing data is read from the RAM. Then, the missing data and partial write data are merged to generate the
32-bit complete data. ECC is calculated over the 32-bit complete data, and written to the RAM with the 32-bit data. The
CYT3/CYT4 series MCUs have the AXI bus interface. ECC of AXI bus interface is added to the 64-bit data. Therefore,
when a partial writing (8-bit/16-bit/32-bit) occurs to the RAM, the missing data is read from the RAM. Then, the missing
data and partial write data are merged to generate the 64-bit complete data. ECC is calculated over the 64-bit complete
data.
The write buffer is used in this operation. Therefore, there is a possibility that write buffer has data that is not yet written
to the RAM. To prevent missing of unwritten data in the write buffer, it is necessary to check the status of the write
buffer.
If there is valid data, wait until it is written to RAM0. When there is no valid data in the write buffer, set the PWR_MODE
bit of the CPUSS_RAM0_PWR_MACRO_CTLx register to RETAINED mode. Finally, generate a software reset. By
performing such a procedure, it is possible to retain the RAM0 data and execute a reset. However, note that the RAM0
data cannot be retained if the voltage is lower than the Brown-Out Detection (BOD: 2.7 V) level. Therefore, it is the
necessary to confirm that BOD has not occurred after returning from a reset.
Table 1 shows the RAM0 status register. It is necessary to confirm that the WB_EMPTY bit is set to '1' before initiating
a software reset.
Table 1. RAM0 Status Register
Register
Bit Field
Bit
Value
Description
CPUSS_RAM0_STATUS
WB_EMPTY [0]
0
Write buffer not empty.
1
Write buffer empty.
Table 2 shows the Power Control register, which controls system RAM0 power states with a single macro.
Table 2. Power Control Register
Register
Bit Field
Bit
Value
Description
CPUSS_RAM0_PWR_MACRO_CTLx
*PWR_MODE [1:0]
0
OFF mode: Turn OFF the SRAM. This will turn OFF both
array and periphery power of the SRAM; SRAM memory
contents are lost.
1
Reserved
2
RETAINED mode: Keep the SRAM in Retained mode. This
will turn OFF the SRAM periphery power, but array power is
ON to retain memory contents. SRAM contents will be
retained in DeepSleep system power mode.
3
ENABLE mode: Enable the SRAM for regular operation.
SRAM contents will be retained in DeepSleep system power
mode. (Default)
* To set the PWR_MODE bit field, use word access in the CPUSS_RAM0_PWR_MACRO_CTLx register. See the
Registers TRM for details.
This register is for the CPUSS system’s RAM0 controller. This information is used when the RAM0 RETAINED mode
is set.
How to Retain RAM Data with Software Reset and Low-Power Mode Transition in Traveo II Family
www.cypress.com Document Number: 002-20152 Rev. *C 3
2.2 Low-Power Mode (DeepSleep Mode) Transition Procedure
Figure 1 shows the flow of RAM retention for low-power mode transition. In this method, when transitioning to a low-
power mode, settings for RAM retention are performed. The procedure to check the status of the Write Buffer and the
RETAINED mode setting of RAM is the same. When the MCU enters a low-power mode, the main program execution
stops. If a wakeup interrupt is generated, the MCU returns to Active mode.
Figure 2. Example of RAM0 Retention Procedure for Low-Power Mode
Start
End
CPUSS_RAM0_PWR_MACRO_CTLx
- PWR_MODE: RETAINED
CPUSS_RAM0_STATUS
- WB_EMPTY: Wait until the WB_EMPTY bit becomes ’1'
'0': Write buffer NOT empty.
'1': Write buffer empty.
Set RETAINED Mode
Write Buffer Empty?
No
Yes
Active mode
Low Power mode
Interrupt
Low power mode
transition
Active mode
2.3 Low-Power Mode (Hibernate Mode) Transition Procedure
Figure 1 shows how the backup memory data for is backed up for Hibernate mode transition. In this method, when
transitioning to Hibernate mode, the backup memory data of the RAM is transferred to the application flash. When the
MCU enters Hibernate mode, the main program execution stops. If a Hdibernate wakeup reset is generated, the MCU
returns to active mode, and the backup memory data is transferred to the RAM from the application flash. The transfer
of data from the RAM to application flash and back are handled by the user software.
To prevent unintentional overwriting of the backup data, you should consider not allowing other programs to access the
backup data area of the application flash and RAM during data backup. In addition, you should ensure that the data
transition time between the RAM and application flash meets your system requirements.
Figure 3. Example of Backup Procedure for Hibernate Mode
Start
End
Transfer data from RAM
to application flash
Active mode
Hibernate mode
Hibernate Wakeup
Hibernate mode
transition (*)
Active mode
Transfer data from application
flash to RAM
Read RAM data and
write to application
flash
Read application
flash and write to
RAM
Note: (*) Hibernate mode transition
is handled by the user software
How to Retain RAM Data with Software Reset and Low-Power Mode Transition in Traveo II Family
www.cypress.com Document Number: 002-20152 Rev. *C 4
3 RAM Retention Procedure in Reset
This section shows two examples for reset procedure with a block diagram, timing chart, and flowchart. One method
uses the Low-Voltage Detection (LVD) interrupt. The other method uses the external reset input signal of the external
LVD IC.
3.1 Reset Using LVD Interrupt
In this case, LVD1 and LVD2 are used. LVD1 is a system low-level voltage detector that ensures that a reset occurs
with guaranteed RAM0 retention. Also, LVD1 is used to detect a VDDD supply voltage drop. In addition, the user
application starts by checking LVD2. LVD2 is used to check whether the VDDD supply voltage has recovered by setting
the rising trip point.
Figure 3. Block Diagram for Reset Procedure for RAM0 Retention with the LVD Interrupt Method
MCU
Software Reset Generation
LVD1,
LVD2
Low Voltage
Detection
RAM0
Retain Mode Setting
Interrupt
5 V
In Figure 3, first, an interrupt is generated when a falling edge is detected from LVD1. After the interrupt has occurred,
RAM0 status needs to be checked and set to RETAINED mode. After these steps, perform a software reset. Then,
after the MCU starts up from reset, check for VDDD exceeding the LVD2 rising edge with the SRSS_INTR register.
Finally, confirm that a BOD reset has not occurred. If a BOD reset occurred, RAM0 data retention is not guaranteed.
Therefore, RAM0 data must be discarded.
Figure 4. Example of Reset Procedure Timing Chart in RAM0 by LVD Interrupt
Interrupt Routine
Interrupt Signal (LVD1)
Main Routine
Interrupt
Normal Operation
Retain
Mode
Setting
Reset
Normal Operation
RAM0 state
Retain Mode
Enable Mode
Restart
RAM
Status
Check
Software
Reset
Setting
Enable Mode
Power Supply (VDDD)
LVD1 Falling
Edge Detection
VDDD
rising
check
LVD2 Rising
Edge Detection
Interrupt
Interrupt Signal (LVD2)
●
●
BOD
●
Not Retain
BOD detection level
In Figure 4, when the VDDD drops, the interrupt routine is called. Then, the interrupt routine checks the RAM0 status,
RETAINED mode setting, and software reset setting (reset generation). After the reset is completed, ensure that VDDD
is rising with the LVD2 detection method, and resume normal operation.
Loading...