Cypress AN218629 User Manual
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www.cypress.com Document Number: 002-18629 Rev. *C 1
AN218629
Comparison of Traveo and Traveo II
Author: Go Shimada
Associated Part Family: Traveo™ Family, Traveo II Family
Related Documents: For a complete list, see Related Documents
AN218629 compares MCUs of the Traveo family with MCUs of the Traveo II family CYT2/CYT3/CYT4 series.
Contents
1 Introduction .................................................................. 1
2 Body Entry/High Products ........................................... 2
2.1 Traveo II Family MCU Features .......................... 2
2.2 Product Overview ................................................ 2
2.3 On-chip System Features ................................... 4
2.4 Peripherals ........................................................ 17
2.5 Development Tools and Flash Programming
Tools ................................................................. 40
2.6 MCAL Support .................................................. 41
3 Cluster Products ........................................................ 41
3.1 Target Products and Traveo II Family MCU
Features ............................................................ 41
3.2 Product Overview ............................................. 42
3.3 On-chip System Features ................................. 43
3.4 Peripherals ........................................................ 49
3.5 Development Tools and Flash Programming
Tools ................................................................. 53
3.6 MCAL Support .................................................. 53
4 Related Documents ................................................... 54
Document History ............................................................ 55
Worldwide Sales and Design Support ............................. 56
1 Introduction
This application note compares Traveo family MCUs with Traveo II family MCUs. Both Traveo and Traveo II families
are manufactured in 40-nm CMOS technology with embedded flash.
Several global system configurations are different between these two product families. While several resources have
been enhanced, downward compatibility is maintained.
This application note consists of two main sections: one for automotive body segment, and the other for automotive
cluster segment. The Body Entry/High Products section compares body products, while the Cluster Products section
compares cluster products. The product lineup is listed Table 1.
Table 1. MCU List for Comparison
Products
Traveo Family
Traveo II Family
Body Entry/High Products
S6J3428, S6J3429, and S6J342A Series
CYT2B7, CYT2B9, and CYT4BF Series
Cluster Products
S6J3200 Series
CYT4DN and CYT2C9 Series
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 2
2 Body Entry/High Products
2.1 Traveo II Family MCU Features
Table 2. Features of Traveo II Family MCUs
Function
CYT2B7 Series
CYT2B9 Series
CYT4BF Series
Flash Memory (Code Flash)
Up to 1088 KB
2112 KB
8256 KB
Flash Memory (Work Flash)
Up to 96 KB
128 KB
512 KB
SRAM0
Up to 64 KB
128 KB
512 KB
SRAM1
Up to 64 KB
128 KB
512 KB
CXPI
Not Supported
Supported
Not Supported
FlexRay
Not Supported
Not Supported
Supported
Secure Digital High Capacity
(SDHC) Host Controller
Not Supported
Not Supported
Supported
Serial Memory Interface
Not Supported
Not Supported
Supported
Ethernet
Not Supported
Not Supported
Supported
2.2 Product Overview
Traveo II Family is a family of 32-bit MCUs based on the high-performance Arm® Cortex®-M series of CPUs, as
Figure 1 shows, intended for automotive body-control applications.
The Cortex-M4 processor is the main CPU designed for a short interrupt response time, high code density, and high
32-bit throughput while maintaining a strict cost and power consumption budget. A secondary Cortex-M0+ based CPU
can implement security, safety, and protection features. Note that the CYT4BF series uses two Cortex-M7 processors
for primary processing.
Figure 1 through Figure 3 show the major architecture components of the CYT2B7 series, CYT2B9 series, and CYT4BF
series. There are four major subsystems: CPU subsystem, system resources, peripheral blocks, and I/O subsystem.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 3
Figure 1. Block Diagram (CYT2B7 Series)
I/O Subsystem
Peripheral Interconnect (MMIO, PPU)
IOSS GPIO
PCLK
7x SCB
I
2
C, SPI, UART
Up to 146x GPIO std, Up to 6x GPIO Enh
CPU Subsystem
High Speed I/O Matrix, Smart I/O, Boundary Scan
1x SCB
I
2
C, SPI, UART
CYT2B7
MXS40-HT
ASIL-B
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-HT
REF
POR
Reset Control
TestMode Entry
XRES
LVD
BOD
DeepSleep
Hibernate
Active/Sleep
LowPowerActive/Sleep
Power Modes
OVP
LDO
Clock
Clock Control
IMO
WDT
CSV
1xPLL
ECO
2xILO
FLL
79x TCPWM
Timer, CTR, QD, PWM
5x Smart IO
6x CANFD
CAN-FD Interface
EFUSE
1,024-bit
8x LIN
LIN/UART
Prog.
Analog
SAR
ADC
(12-bit)
x3
SARMUX
64-ch
System Interconnect (Multi-Layer AHB, IPC, MPU/SMPU)
Crypto
AES, SHA, CRC,
TRNG, RSA,
ECC
Initiator/MMIO
SWJ/MTB/CTI
MUL, NVIC, MPU
Arm
Cortex M0+
100 MHz
SWJ/ETM/ITM/CTI
Arm Cortex M4
160 MHz
FPU, NVIC, MPU
eCT Flash
Up to 1088 KB Code flash
+ Up to 96 KB Work flash
Flash Controller
8KB $ 8KB $
SRAM0
Up to 64KB
SRAM Controller
ROM
32KB
ROM Controller
SRAM1
Up to 64KB
SRAM Controller
M-DMA0
4-Channel
P-DMA1
33-Channel
P-DMA0
89-Channel
EVTGEN
Event Generator
WCO
RTC
Figure 2. Block Diagram (CYT2B9 Series)
I/O Subsystem
Peripheral Interconnect (MMIO, PPU)
IOSS GPIO
PCLK
7x SCB
I
2
C, SPI, UART
Up to 148x GPIO std, Up to 4x GPIO Enh
CPU Subsystem
High Speed I/O Matrix, Smart I/O, Boundary Scan
1x SCB
I
2
C, SPI, UART
CYT2B9
MXS40-HT
ASIL-B
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-HT
REF
POR
Reset Control
TestMode Entry
XRES
LVD
BOD
DeepSleep
Hibernate
Active/Sleep
LowPowerActive/Sleep
Power Modes
OVP
LDO
Clock
Clock Control
IMO
WDT
CSV
1xPLL
ECO
2xILO
FLL
83x TCPWM
Timer, CTR, QD, PWM
5x Smart IO
8x CANFD
CAN-FD Interface
EFUSE
1,024-bit
12x LIN
LIN/UART
Prog.
Analog
SAR
ADC
(12-bit)
x3
SARMUX
64-ch
WCO
System Interconnect (Multi-Layer AHB, IPC, MPU/SMPU)
Crypto
AES, SHA, CRC,
TRNG, RSA,
ECC
Initiator/MMIO
SWJ/MTB/CTI
MUL, NVIC, MPU
Arm
Cortex M0+
100 MHz
SWJ/ETM/ITM/CTI
Arm Cortex M4
160 MHz
FPU, NVIC, MPU
eCT Flash
2112 KB Code flash +
128 KB Work flash
Flash Controller
8KB $ 8KB $
SRAM0
128 KB
SRAM Controller
ROM
32KB
ROM Controller
SRAM1
128 KB
SRAM Controller
M-DMA0
4-Channel
P-DMA1
44-Channel
P-DMA0
92-Channel
EVTGEN
Event Generator
4x CXPI
CXPI Interface
RTC
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 4
Figure 3. Block Diagram (CYT4BF Series)
I/O Subsystem
Up to 196x GPIO_STD, 4x GPIO_ENH, 40xHSIO
High Speed I/O Matrix, Smart I/O, Boundary Scan
CYT4BF
MXS40-HT
ASIL-B
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-HT
REF
POR
Reset Control
TestMode Entry
XRES
LVD
BOD
DeepSleep
Hibernate
Active/Sleep
LowPowerActive/Sleep
Power Modes
OVP
LDO
Clock
Clock Control
IMO
WDT
CSV
4xPLL
ECO
2xILO
FLL
5x Smart IO
WCO
RTC
Peripheral Interconnect (MMIO,PPU)
IOSS GPIO
PCLK
CPU Subsystem
System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)
115x TCPWM
TIMER,CTR,QD, PWM
10x CANFD
CAN-FD Interface
EFUSE
1x FLEXRAY
FlexRay Interface
SWJ/ETM/ITM/CTI
NVIC, MPU, AXI
Cortex M7
350 MHz
FPU
(SP/DP)
D$
16KB
I$
16KB
AHBSAHBP
ITCM
16 KB
DTCM
16 KB
SWJ/ETM/ITM/CTI
NVIC, MPU, AXI
Cortex M7
350 MHz
FPU
(SP/DP)
D$
16 KB
I$
16 KB
AHBSAHBP
ITCM
16 KB
DTCM
16 KB
eCT FLASH
8384 KB Code flash
+ 256 KB Work flash
FLASH Controller
8 KB $
10x SCB
I2C,SPI,UART,LIN
1x SCB
I2C,SPI,UART,LIN
20x LIN
LIN/UART
CRYPTO
AES,SHA,CRC,
TRNG,RSA,ECC
Initiator/MMIO
SWJ/MTB/CTI
MUL, NVIC, MPU
Cortex M0+
100 MHz
SRAM0
512 KB
SRAM
Controller
ROM
64 KB
ROM Controller
M-DMA0
8 Channel
P-DMA1
65 Channel
P-DMA0
143 Channel
1x SMIF
Serial Memory Interface (Hyperbus, Single SPI,
Dual SPI, Quad SPI, Octal SPI)
2x ETH
10/100/1000 Ethernet + AVB
SDHC
SD/SDIO/eMMC
EVTGEN
Event Generator
3x AUDIOSS
I2S/TDM In/Out
SRAM1
256 KB
SRAM
Controller
SRAM2
256 KB
SRAM
Controller
Prog.
Analog
SAR
ADC
(12-bit)
x3
SARMUX
96 ch
2.3 On-chip System Features
2.3.1 CPU
Both Traveo and Traveo II family are based on 32-bit Arm Cortex processors.
Traveo family has a single Cortex-R5 processor, while Traveo II family is a dual-CPU with Cortex-M4 and Cortex-M0+
processors. In Traveo II, two CPUs are configured as the CPU subsystem; Cortex-M4 or Cortex-M7 processor is the
main CPU and Cortex-M0+ processor is the secondary CPU that can implement security, safety, and protection features.
Note that as the CPU core changes, MCU features change according to the core specification.
Table 3. Differences in CPU
Item
Traveo Family
Traveo II Family
Remarks
Main CPU
Secondary
CPU
CYT2B7/B9 Series
CYT4BF Series
CPU Core
Cortex-R5F
Cortex-M4
Cortex-M7 (x2)
Cortex-M0+
Operation
Frequency
Up to 132 MHz
Up to 160 MHz
Up to 350 MHz
Up to 100 MHz
Product
specifications
FPU
Single/Double precision
Single precision
Single/Double precision
None
MPU
16 regions
8 regions
16 regions
8 regions
1
Cache Memory
I-cache 16 KB / D-cache 16 KB
None
I-cache 16 KB / D-cache 16 KB
None
TCM Interface
Supported
Implemented TCRAM
Not supported
Supported (ITCM, DTCM)
Not supported
1
Traveo II family has SMPU as memory protection in addition to the CPU's internal MPU. Refer to 2.3.14 Protection.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 5
Item
Traveo Family
Traveo II Family
Remarks
Main CPU
Secondary
CPU
CYT2B7/B9 Series
CYT4BF Series
Support for
Interrupt
Controller
Vector Interrupt Controller (VIC)
Nested Vector Interrupt Controller (NVIC)
2.3.2 Memory Design
Table 4 lists the Code Flash features. The main differences are in program size, Read-While-Write operation, and
redundancy.
Table 4. Differences in Code Flash
Code Flash
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
ECC
SEC/DED
SEC/DED
Sector Size
32 KB, 8 KB
32 KB, 8 KB
Program Size
32 bits, 64 bits, 256 bits
64 bits, 256 bits, 4096 bits
Program and Erase
Cycles/Retention
1000/20 years
1000/20 years
Read-While-Write Operation
Not supported
Supported
Table 5 lists the Work Flash features. The main differences are in the sector size, program and erase cycles, Read-
While-Write operation, and redundancy. When compared to Traveo, Traveo II families support smaller sector size and
higher program and erase cycles.
Table 5. Differences in Work Flash
Work Flash
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
ECC
SEC/DED
SEC/DED
Sector Size
4 KB
2 KB, 128 B
Program Size
32 bits
32 bits
Program and Erase
Cycles/Retention
1000/20 years
10000/10 years
100000/5 years
125000/20 years
250000/10 years
Read-While-Write
Operation
Not supported
Supported
Table 6 lists the SRAM features. The main difference is the data retention in low power mode. Traveo II family supports
data retention in DeepSleep mode.
Table 6. Differences in SRAM
SRAM
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
ECC
SEC/DED
SEC/DED
Data Retention in Low
Power Mode
Not supported
(TCRAM and SRAM are not retained in
Shutdown mode. Backup RAM is retained in
Shutdown mode)
Supported
(SRAM is retained in DeepSleep mode)
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 6
2.3.3 Debug
Traveo and Traveo II families support JTAG and SWD Debug Interface. Table 7 shows the main differences in
debugging.
Table 7. Differences in Debugging
Item
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
Debug interface
JTAG
SWD
JTAG
SWD
2.3.4 Mode Setting
Traveo II family does not support the serial programming mode; therefore, there is no mode pin in Traveo II family.
When the debugger is connected to JTAG, Traveo II family transitions to Debug mode and enables programming to
flash.
Table 8. Differences in Mode Setting
Item
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
Normal Mode
Setting by mode pin
• User Mode
Debugger is not connected (SWD or JTAG)
• Boot mode/user mode/trusted mode
• Life cycle stage (Secure)
Board mode
Setting by mode pin
• Serial programming mode
• Parallel programming mode
Debugger is connected (SWD or JTAG)
• Debug mode
• Life cycle stage (Normal_Provisioned
/Secure/Secure_With_Debug/RMA/
Corrupted)
2.3.5 Power Supply and Monitoring
The power supply of Traveo II family is the same as that of Traveo family, but signal names of power supply are
different. Also, the type of power monitoring mode has been enhanced in Traveo II family.
2.3.5.1 Power Supply
Table 9 lists the power supply and differences in functionality.
Table 9. Power Supply
Power Supply
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
External
Digital
VCC
2.7 to 5.5 V
V
DDD
2.7 to 5.5 V
I/O
V
DDIO_1/2
2.7 to 5.5 V
V
DDIO_3/4
2.7 to 3.6 V (only for CYT4BF series)
Analog
AVCC0/1
2.7 to 5.5 V
V
DDA
2.7 to 5.5 V
Internal
C
1.2 V
V
CCD
1.1 V
V
CCD
of CYT4BF can be also external
power supply (typical 1.15 V when V
CCD
is
external power supply)
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 7
2.3.5.2 Monitoring
Table 10 lists the differences in voltage between Traveo and Traveo II families.
Table 10. Voltage Monitoring
Monitoring
S6J3428/9/A Series
CYT2B7/B9, CYT4BF Series
Voltage Monitoring
• Power-on reset (POR)
• LVD
• POR
• LVD
• Brownout detection (BOD)
• Overvoltage detection (OVD)
• Overcurrent detection (OCD)
2.3.6 Reset Factor
Note that all resets in Traveo II family are asynchronous resets. This difference is because the reset factor is optimized
according to the Traveo II system. If you need the RAM retention Reset, see the Architecture Technical Reference
Manual (TRM). Table 11 lists the main differences in Reset Factor.
Table 11. Differences in Reset Factors
Reset Sources
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Remarks
POR
Yes
Yes
BOD Reset
• External LVD Reset
• Internal LVD Reset
• RAM retention LVD Reset
• External voltage BOD Reset
2
• Internal voltage BOD Reset
3
• Analog input voltage BOD Reset
2,4
OVD Reset
No
• External voltage OVD Reset
2
• Internal voltage OVD Reset
3
• Analog input voltage OVD Reset
2,4
OCD Reset
No
Internal voltage OCD Reset3
External Reset
RSTX pin
XRES_L pin
Clock Stop Wait
Timeout Reset
Yes
No, does not support synchronous reset
Illegal Mode Detection
Reset
Yes
No, does not have MD pin
Profile Error Reset
Yes
No, does not support Profile setting
Watchdog Timer (WDT)
Reset
• Hardware WDT Reset
• Software WDT Reset
• WDT Reset
• Multi-Counter WDT Reset
See 2.3.8
Watchdog Timer
Internal System
(Software) Reset
• Software Reset
• Software trigger hard Reset
• Software Reset
Fault Detection Reset
No
Yes: via Fault report
2
Programmable Trip point (2 points)
3
Fixed Trip point
4
Reset or Fault report can be selected
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 8
Reset Sources
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Remarks
Clock Supervision
(CSV) Reset
• Main Clock CSV Reset
• Sub Clock CSV Reset
• PLL Clock CSV Reset
• SSCG Clock CSV Reset
• Fast CR CSV Reset
• Slow CR CSV Reset
• CLK_REF CSV Reset
• ILO0 CSV Reset
• CLK_HF CSV Reset
• CLK_LF CSV Reset
Wakeup Reset
Yes (Power Domain Reset)
Yes (Hibernate Wake up Reset)
Debugger Reset
• TRSTX
• Software Reset
• NTRST
• Software Reset
2.3.7 Clock System
Compared to Traveo family clock system, Traveo II family (only CYT4B Series) has Spread Spectrum Clock Generator
functions. In Traveo II family, frequency-locked loop (FLL) featuring fast startup and low power is implemented.
Table 12 lists the main differences in clock system.
See the datasheet for the AC characteristics of each clock.
Table 12. Differences in Clock System
Clock System
Traveo Family
(S6J3428/9/A Series)
Traveo II Family
(CYT2B Series)
Traveo II Family
(CYT4B Series)
Internal Clock Source
Fast CR: 4 MHz
(Using source clock after
reset)
Slow CR: 100 kHz
IMO: 8 MHz
(Using source clock after reset)
ILO0/1: 32 kHz
External Clock Source
Main clock: 3.6 to 16 MHz
Sub clock: 32.768 kHz
ECO: 3.988 to 33.33 MHz
WCO: 32.768 kHz
EXT_CLK5 : 0.25 to 100 MHz
High-Speed
Clock Generation
PLL
PLL x1
Input: 3.6 to 17.6 MHz
Output: 200 to 320 MHz
SSCG PLL x1
Input: 3.6 to 32MHz
Output:200 up to 320 MHz
PLL x1
Input: 3.988 to 33.34 MHz
Output: 11 to 160 MHz
SSCG not supported
PLL without SSCG x2
Input: 3.988 to 33.34 MHz
Output: 11 to 200 MHz
PLL with SSCG x2
Input: 3.988 to 33.34 MHz
Output: 25 to 400 MHz
FLL
Not implemented
FLL x1
Input: 0.25 to 80 MHz
Output: 24 to 100 MHz
FLL x1
Input: 0.25 to 80 MHz
Output: 24 to 100 MHz
Clock Gear
Supported
Not implemented
Clock Supervision
Main clock
Sub clock
PLL clock
SSCG clock
Slow CR
Fast CR
CLK_REF (IMO or ECO or EXT_CLK)
CLK_HF (PLL and FLL)
ILO0
CLK_LF (ILO1 or WCO)
5
It can be sourced from a designated I/O pin.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 9
2.3.8 Watchdog Timer
Table 13 lists the watchdog timer (hardware) features. The main differences are counter clock, maximum timeout, and
the behavior during low-power mode and debugging.
Table 13. Differences in Watchdog Timer (Hardware)
Watchdog Timer
(Hardware)
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Trigger
Reset
Reset
Counter Clock
• Fast internal clock: 4 MHz
• Slow internal clock: 100 kHz
• Internal low speed oscillator: 32 kHz
Counter
32 bits
32 bits
Maximum Timeout
12 hours
38.33 hours
Window Function
Supported
Supported
Warning Interrupt
Supported
Supported
Timeout Expiration Action
Reset or nonmaskable interrupt (NMI)
Reset
Behavior During Low-Power
Mode
Stop
Register can select stop or run
Behavior During Debugging
Stop at debugging state
Register can select stop or run
Table 14 lists the multi-counter watchdog timer (software) features. The main differences are counter clock, counter,
maximum timeout, and the behavior during debugging.
Table 14. Differences in Multi-Counter Watchdog Timer (Software)
Multi-counter Watchdog
Timer (Software)
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Trigger
User program
User program
Counter Clock
• Fast internal clock: 4 MHz
• Slow internal clock: 100 kHz
• Main clock: 4 to 16 MHz
• Sub clock: 32 kHz
• Internal low-speed oscillator: 32 kHz
• Watch crystal oscillator: 32 kHz
Counter
32 bits
2 * 16-bit, 32 bits only for interrupt
Maximum Timeout
36.4 hours
2.11 seconds
Window Function
Supported
Supported
Warning Interrupt
Supported
Supported
Timeout Expiration Action
Reset or NMI
Reset or Fault
Behavior During Low-Power
Mode
Register can select stop or run.
Register can select stop or run.
Behavior During Debugging
Stop at debugging state
Register can select stop or run.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 10
2.3.9 Low-Power Mode
Table 15 lists the low-power modes. Traveo II family supports almost all low-power modes with DeepSleep mode.
Table 15. Differences of Low-Power Modes
Low Power Mode
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Sleep
• CPU: Halt
• Peripheral: Active
• SRAM retention
Supported: Sleep
• TCRAM/SRAM/Backup RAM retention
Supported: Sleep
• SRAM retention
Timer
• CPU: Halt
• Peripheral: Halt except RTC,
GPIO
• SRAM retention
Supported: Timer
• TCRAM/SRAM/Backup RAM retention
Supported: DeepSleep
• Peripheral: OFF except RTC, Event
generator, GPIO
• SRAM retention
Stop
• CPU: Halt
• Peripheral: Halt except
GPIO
• SRAM retention
Supported: Stop
• TCRAM/SRAM/Backup RAM retention
Supported: DeepSleep
• Peripheral: OFF except RTC, Event
generator, GPIO
• SRAM retention
Partial wakeup (Shutdown)
• CPU: OFF
• Peripheral: OFF except
RTC, ADC, GPIO
• Partial RAM retention
Supported: Partial wakeup
• ADC is triggered by RTC
• Backup RAM retention
Supported: DeepSleep
• Peripheral: OFF except RTC, Event
generator, GPIO
• ADC and LIN are triggered by Event
generator
• SRAM retention (Full/Partial)
Timer (Shutdown)
• CPU: OFF
• Peripheral: OFF except
RTC, GPIO
• Partial RAM retention
Supported: Timer (Shutdown)
• Backup RAM retention
Supported: DeepSleep
• Peripheral: OFF except RTC, Event
generator, GPIO
• SRAM retention (Full/Partial)
Stop (Shutdown)
• CPU: OFF
• Peripheral: OFF except
GPIO
• Partial RAM retention
Supported: Stop (Shutdown)
• Backup RAM retention
Supported: DeepSleep
• SRAM retention (Full/Partial)
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 11
2.3.10 Interrupt Structure
The interrupt structure of Traveo and Traveo II families differ based on the CPU. Traveo family (Cortex-R5) interrupt
controller used vector interrupt controller (VIC), while Traveo II family (Cortex-M4//M7/M0+) uses nested vector interrupt
controller (NVIC). Table 16 lists the main differences in interrupt structure.
Traveo family controls system interrupts such as enable/disable, levels, and level masks with an external interrupt
controller. Each CPU of Traveo II family has eight interrupt inputs, and controls interrupts within the CPU, thereby
performing high-speed interrupt processing.
Traveo II family uses up to 1023 system interrupts assigned to eight groups. All interrupts within a group has the same
priority. Four of the 1023 system interrupts can be assigned as NMI.
Traveo II family implements wakeup interrupt controller (WIC), which enables interrupt detection for CPU wakeup in
DeepSleep power mode.
Table 16. Differences of Interrupt Structure
Item
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Remarks
CPU core
Cortex-R5F
Cortex-M4/M7
Cortex-M0+
Supported Interrupt
Controller in CPU
VIC
NVIC
Number of IRQ
inputs of CPU
1 8 8
Number of NMI
Inputs of CPU
1 1 1
Priority Level
Interrupt: 32 levels
NMI: 16 levels
Interrupt: 8 levels
NMI: None
Interrupt: 4 levels
NMI: None
Number of System
Interrupts
Up to 512
Up to 1023
6
Vector Address
Assigned for each system
interrupt
Assigned for each IRQ input.
Multiple system interrupts share a CPU
interrupt handler as provided by the VTOR
table.
WIC
Not Supported
Supported
6
System Interrupts are interrupts generated from peripheral functions and external inputs. For the list of system interrupts supported
by the device variants, see the following documents:
- Traveo Family: Hardware Manual by the device variants.
- Traveo II Family: Architecture Technical Reference Manual by the device variants
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 12
2.3.11 Data Transfer
For data transfer, Traveo II family has two types of DMA with different purposes: Peripheral DMA (P-DMA) and Memory
DMA (M-DMA). Table 17 lists the main differences in data transfer.
P-DMA focuses on achieving low latency for a large number of channels. P-DMA has a single data transfer engine that
is shared by all channels.
M-DMA focuses on achieving high memory bandwidth for a small number of channels. M-DMA has a dedicated data
transfer engine for each channel.
The DMA transfer specification of Traveo family is set by the register. In Traveo II family, transfer is specified by the
descriptor in SRAM. P/M-DMA of Traveo II family can perform transfer chaining with descriptor setting.
Table 17. Differences of Data Transfer
Item
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Remarks
Function Name
DMAC
P-DMA
M-DMA
Data Transfer Specifics
Register
Descriptor in memory
Data Size
8-/16-/32-/64-bit
8-/16-/32-bit
Transfer Mode
• Single
• Block
• Burst
• Single
• 1D/2D
• CRC transfer
• Descriptor chaining
• Single
• 1D/2D
• Memory copy
• Scatter
• Descriptor chaining
Activation Trigger
• Hardware
• Software
• Hardware
• Software
• Transfer completion
trigger output
• Software
• Transfer completion
trigger output
Channel Arbitration
Schemes
• Fixed
• Dynamic
• Round robin
• Fixed four levels
• Round-robin in the same priority group
Interrupt Generation
• Transfer
Completion
• Error occurrence
• Transfer completion
• Error occurrence
Protection Schemes
Dedicated MPU
• Access range
• User/Privilege
• Read/Write
SMPU and PPU
• Access range
• User/Privileged
• Read/Write
• Secure/Non-secure
• Protection Contexts
See Protection.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 13
2.3.12 TPU
Traveo family has a dedicated timer for timing protection (TPU). However, Traveo II family does not have a dedicated
timer. Traveo II family uses a TCPWM timer for timing protection.
The TCPWM timer is a general-purpose timer that can generate interrupts for overflow, underflow, and compare
matches. This interrupt can be implemented as NMI, which can provide the TPU function. Figure 4 shows the
configuration of the TPU and Figure 5 shows an example of the operation.
Figure 4. Timing Protection Implementation Example
CPU tcpwmInterrupt
Controller
NMI
Timer
(5) Underflow
(1),(3),(4)
(5)
(2)
(3) Start Down Count
1. Configure the TCPWM initial values (for example, using DownCount mode), and set the upper limit of the
measurement time as the initial time.
2. Set the TCPWM interrupt to NMI.
3. Software starts the timer at the start point of the measurement process.
4. Software stops the timer at the end point of the measurement process.
5. If the counter under-flowed before the software stops the timer, the Underflow interrupt of the TCPWM is notified
as an NMI to the CPU via the interrupt controller.
Note: The interrupt controller can notify the system interrupt as NMI, including the TCPWM interrupt.
Figure 5. Timing Protection Example (Monitoring of the Interrupt Service Routine Operation Time)
Timer
Initial value
Interrupt
Timer
Start
Timer
Stop
Interrupt operation
Interrupt
Timer
Start
Interrupt operation
||||
||
||
Under flow
Interrupt
Service Routine
NMI
Interrupt Timeout
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 14
2.3.13 Fault Report
Fault report is a new feature of Traveo II family. Figure 6 shows a block diagram of the Fault structure.
The centralization of faults by Fault report structures for a system-wide consistent handling of faults simplifies software
development.
Fault report captures up to 967 failures such as MPU/SMPU/PPU protection violations, SRAM controller ECC errors,
peripheral-specific errors, and so on. When Fault report captures a fault, it generates a notification signal such as fault
interrupt, trigger output, external pin output, and fault reset request. Each of these output signals can be enabled or
disabled.
The fault interrupt can be mapped to the CPU NMI as a system interrupt. In addition, Fault report provides the fault
source and additional fault-specific information.
For more details, see the Traveo II Architecture Technical Reference Manual (TRM).
Figure 6. Fault Structure
Fault report
Pending Faults
Fault report
Fault report
Fault Report
Structure
Fault Report
Structure
Data0-7
Fault Control
Status
MASK0-2
INT Control
PENDING0-2
・
・
Fault Source
(Up to 96)
Fault Reset
Interrupt
Trigger
Out Signal
Fault source and
additional information
7
For the list of system interrupts supported by the device variants, see the Technical Reference Manual.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 15
2.3.14 Protection
The Protection function of Traveo family consists of the CPU's Memory Protection Unit (MPU), DMA's MPU, and
Peripheral Protection Unit (PPU). Traveo II family consists of MPU, Shared Memory Protection Unit (SMPU), and PPU.
Table 18 lists the main differences in Protection Units.
In Traveo II family, memory protection is provided by MPU and SMPU. MPU is implemented as part of the CPU and
bus infrastructure. P-DMA, M-DMA, and encrypted components do not have MPU. Instead, they inherit the access
control attributes of programmed bus transfer.
SMPU is shared by all masters; PPU is a protection unit for peripheral registers.
Traveo II family supports a new protection attribute (Secure/Non-secure), and protection contexts. Protection contexts
can change the access restriction without changing the setting of the protection unit.
For more details, see the Technical Reference Manual.
Table 18. Differences in Protection Configuration and Access Attribute
Item
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Remarks
MPU implemented in the CPU
Cortex-R5: 16 Regions
Access Attribute:
• Access Range
• Privileged/Unprivileged
• Read/Write
• Execute (Code or Data)
Cortex-M4/M0+: 8 Regions
Cortex-M7: 16 Regions
Access Attribute:
• Access Range
• Privileged/Unprivileged
• Read/Write
• Execute (Code or Data)
MPU implemented in the bus
infrastructure
Not supported
16 Regions
Access Attribute:
• Access Range
• Privileged/Unprivileged
• Read/Write
• Execute (Code or Data)
For external master
such as debugger
SMPU
Not supported
16 Regions
Access Attribute:
• Access Range
• Privileged/Unprivileged
• Read/Write
• Execute (Code or Data)
• Secure/Non-secure
• Protection Contexts
PPU
Access Attribute:
• USER/Privilege
• Read/Write
Access Attribute:
• Access Range
• Privileged/Unprivileged
• Read/Write
• Execute (Code or Data)
• Secure/Non-secure
• Protection Contexts
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 16
Item
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Remarks
MPU16-AHB
Access Attribute:
• Access range
• USER/Privilege
• Read/Write
Not supported.
DMA access protection is
provided by SMPU and PPU.
2.3.15 Boot Process
The boot process of both Traveo and Traveo II families is executed after reset and before the application program
starts. The boot process is executed by the Cortex-R5 processor in Traveo family, and is executed by the secure master
(Cortex-M0+ processor) in Traveo II family.
The boot process in Traveo family mainly executes based on the operation mode and the security setting that the
debugger connection authenticates, secure boot processing, and hardware watchdog timer according to the flash
marker.
In Traveo II family, the boot process consists of ROM boot and flash boot. The ROM boot process determines the
Protection State and validates the flash boot process. The flash boot process configures the protection unit such as
SMPU and PPU, and verify the application program code in the flash memory. In addition, activates the boot loader.
For more details, see the Technical Reference Manual.
2.3.16 Security
Table 19 lists the security features. Traveo II family supports lifecycle stages, device protection states, and Hardware
Security Module (HSM).
Table 19. Differences of Security
Security
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Lifecycle stages
Device protection states
Not supported
Supported
• Lifecycle stages
• Protection states
Flash protection
Supported
Supported
Debugger security
Supported
Supported
Hardware-based
encryption
Supported
Secure Hardware Extension (SHE)
Supported
Enhanced Secure Hardware Extension (eSHE)
and HSM support are enabled by third-party
firmware.
Comparison of Traveo and Traveo II
www.cypress.com Document Number: 002-18629 Rev. *C 17
2.4 Peripherals
2.4.1 Timer
The Timer function of Traveo family consists of a Base timer, Reload timer, Free-run timer, Input Capture, Output
compare, and Quadrature Position/Revolution Counter (QPRC).
Traveo II family implements TCPWM with integrated multiple timer functions. The TCPWM has seven operation modes.
All TCPWM channels can be operated by selecting one of the seven modes. Table 20 lists the corresponding modes
of each function.
Table 20. TCPWM Channel Modes
Function Name
S6J3428/9/A Series
CY2B7/B9, CYT4BF Series
Timer Mode
Base timer: Reload Timer mode
Free-run Timer
Reload Timer
TCPWM: Timer mode
Capture Mode
Input Capture
Base timer: PWC Timer mode
TCPWM: Capture mode
Quadrature
Decoder
QPRC
TCPWM: QUAD mode
PWM Mode
Output compare
Base timer: PWM Timer mode
Base timer: PPG Timer mode
TCPWM: PWM mode
PWM with Dead
Time
Not supported
TCPWM: PWM_DT mode
Pseudo-Random
PWM
Not supported
TCPWM: PWM_PR mode
Shift Register
Not supported
TCPWM: SR mode
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