Cypress AN1196, EZ-USB FX2 PCB User Manual
EZ-USB FX2™ PCB
Design Recommendations
AN1196
Introduction
This application note presents recommendations for designing with the Cypress Semiconductor EZ-USB FX2™ component. Techniques for high-speed design should be applied to
circuits using the EZ-USB FX2. Due to the packaging and
high performance characteristics of the EZ-USB FX2, consideration of the PCB thermal design is required.
CY4611 EZ-USB FX2 USB to ATA Reference
Design
A complete design using the Cypress CY7C68013 EZ-USB
FX2 is available. The design implements the recommendations of this application note. It may be useful for the reader to
download the CY4611 Reference Design Files from the
Cypress Support page for Reference Designs.
Figure 1. FX2 (CY4611) USB to ATA Reference Design
EZ-USB FX2 Package Description
The CY7C68013-56LFC EZ-USB FX2 component is packaged as a 56-pad, 8-mm by 8-mm, 1-mm high, QFN (Quad
Flatpack No leads) package. Please refer to the latest
CY7C68013 EZ-USB FX2 USB Microcontroller High-speed
USB Peripheral Controller data sheet for the detailed package drawing. The data sheet is Cypress specification 38-
08012.
This package is comparable to the Amkor MicroLeadFrame™
package. It is a plastic encapsulated, near-chip scale package using solder lands instead of leads or balls. It uses a copper leadframe substrate that provides for short die to frame
lead length giving good high-frequency performance. It has
an exposed die paddle that enables good thermal transfer out
of the package. For further details about this package and
methods and processes associated with its assembly to a
printed circuit board, please refer to the manufacturer's application note identified in the References section o f this document.
Electrical Design Recommendations
USB 2.0 high-speed signaling is used to transfer data at 480
Mbps. This rate is 40 times higher than the highest speed of
the USB 1.1 specification, full-speed signaling that operates
at a 12-Mbps rate. High-speed signaling requires a greate r
level of attention to electrical design than previously requ ired
for USB designs. Careful attention to component selection,
supply decoupling, signal line impedance, and noise are
required when designing for high-speed USB. These physical
issues are mostly effected by the PCB design and is presented in the PCB Design Recommendation section.
One key measurement of USB data signal quality is the eye
Cypress offers the CY4611 EZ-USB FX2 USB to ATA Reference Design as an evaluation platform for developers wishing
to integrate a USB 2.0 Peripheral Controller into their application. The kit includes the EZ-USB FX2 USB to AT A evaluation
board, USB cable, schematics, bill of material, PCB Gerber
files, and other documentation.
November 21, 2002 Document No. 001-43117 Rev . ** 1
pattern. The eye pattern is a representation of USB signaling
that provides minimum and maximum voltage levels as well
as signal jitter. Section 7.1 in the USB 2.0 Specification provides detailed explanation and requirements for a compliant
eye pattern. Figure 2 is an eye diagram of high-speed signaling as measured on the EZ-USB FX2 component.
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Figure 2. FX2 Eye Diagram of High-speed Signaling
In the diagram, notice how no signal traces overlap the central, six-sided, shaded area. Also, no trace overlaps the
extremes of permissible voltage as shown in the shaded lines
at the very top and very bottom of the figure. Overlap of signal trace over the shaded areas would be a violation of th e
USB 2.0 specification. Overlap can be caused by excessive
data jitter, mismatched impedance, and improper EMI filtering.
The Cypress Semiconductor application note titled “HighSpeed USB PCB Layout Recommendations” treats the electrical design concerns applicable to high-speed USB 2.0 circuits. There are numerous textbooks that treat the subject of
high-speed design in general. One such book is listed in th e
References section of this document.
EZ-USB FX2 Device Supply Decoupling
Decoupling capacitors should be ceramic type of a stable
dielectric. For lower value capacitance, it is appropriate to
use Class 1 dielectric capacitors, C0G (also referred to as
NPO). Class 2 X7R should be used for the larger values. It is
recommended that 0.01-µF and 0.001-µF capacitors be used
to decouple supply pins nearest the pair of USB transceiver
circuits. The 0.001-µF should be C0G dielectric. This will help
decouple the power supply at the frequency range of highspeed USB switching. The other power supply pins should be
decoupled with 0.1-µF X7R capacitors. It is important to have
short trace runs for the power and ground connections from
the EZ-USB FX2 component to solid power and ground
planes.
The specific recommendation for the ceramic capacitor nearest each EZ-USB FX2 power pin is given in Table 1 below.
Table 1. Capacitor Recommendation
QFN
Pin Number
7 0.01 µF 43 0.1 µF
11 0.001 µF 55 0.1 µF
17 0.1 µF 3 0.1 µF
27 0.1 µF 3 2.2 µF
32 0.1 µF
Capacitor
Value
QFN
Pin Number
Capacitor
Value
EMI and ESD Considerations
EMI and ESD need to be considered on a case by case basis
relative to the product enclosure, deployed environment, and
regulatory statutes. This application note does not give specific recommendations regarding EMI, but only gives general
EMI and ESD.
The CY7C68013 requires an external 24-MHz crystal. The
component includes circuitry to step up that frequency to support the 480-MHz bit rate of high-speed USB signaling. Solid
ground planes and short connections help keep emissions
low. Common mode chokes on the USB data pair reduce
emissions at the expense of signal quality. Other forms of
EMI filtering such as insertion of ferrite beads in-line with
USB data lines and addition of capacitance to the data lines
are strongly discouraged as these may cause a significant
corruption of signal quality.
An example of ESD consideration is in the coupling betwe en
signal and safety/shield ground. The two grounds can be
coupled together with the parallel connection of a 4.7-nF,
250VAC capacitor and a 1M-ohm resistor. Review the
CY7C68013 data sheet regarding ESD susceptibility (the
maximum static discharge voltage) for the component pins.
When USB type B connectors are used, they should be USB
2.0 compliant. These shielded connectors are designed with
consideration for both EMI and ESD at the high-speed signalling rates. In this connector the safety/shield ground is kept
separate from the signal ground.
PCB Design Recommendation
Printed circuit board (PCB) design for high-speed signaling
requires careful attention to component placement, signal
routing, layer stack-up, and selection of board material.
These characteristics impact electrical signal quality of the
USB data pair and the efficient dissipation of heat from the
EZ-USB FX2 component.
Some areas of special note concerning design with highspeed devices are addressed in this section.
November 21, 2002 Document No. 001-43117 Rev. ** 2
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AN1196
Zdiff 2 Z010.48– e
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Maintain PCB Trace Impedance
Designing the PCB traces for particular characteristic impedance is very important to signal quality. The USB specification
requires controlled impedance among all elements in the
USB data path. The differential impedance of each USB data
pair should be 90 ohms with a 10% tolerance to match the
differential output impedance of high-speed capable drivers.
A common way to implement a differential pair is to use an
edge-coupled, surface micro-strip line. The pair is placed on
the board’s surface layer, and is directly over a ground plane
layer. This is the scenario used in the design of the CY4611.
The following five parameters set the value for the differential
impedance.
Table 2. Parameters for Differential Impedence
Term Description
h Height of signal traces above ground plane
ε
r
t Trace thickness
wTrace width
s Spacing between each trace of a differential
Parameters h, t, w, and s may be any unit but must be consistent. For example, the CY4611 design referenced in this
application note shows these units in mil, (an English unit,
1/1000th of an inch).
For an edge-coupled, surface micro-strip, these five parameters (h,
ε
, t, w, and s) set the value for the differential imped-
r
ance (“Zdiff”). Zdiff is defined in terms of the impedance of
each line of the pair, (“Z
impedance are:
Material dielectric constant
pair, inside edge-to-edge
ε
is a dimensionless constant.
r
”). The equations approximating
0
Equation 1
The reference section lists a book resource and cites a URL
for downloading a spreadsheet for calculating the impedances mentioned. The following is an example of calculating
the trace impedance that is used in the CY4611 FX2 USB to
ATA/CF Reference Design.
Table 3, which is extracted from the CY4611 FX2 USB to
ATA/CF Reference Design drawings, shows the dimensions
that impact the impedance for the USB data traces. These
dimensions must not only satisfy the required characteristic
impedance but must also be applicable in a practical physical
design. For instance, different fabrication processes may
have limited choices for material dielectric constant and
material thickness between the signal layer and the ground
layer. These two parameters dictate the trace dimensions for
this design. The PCB manufacturer's material for the PCB
was taken from their standard supply. The vendor provided
the tolerance values shown in Table 3. The values are all fin-
ished dimensions.
Table 3. Tolerance Values
Tolerances Min. Nominal Max.
Material Thickness(mils)
Material Dielectric ±0.2 3.8 4.0 4.2
Trace Thickness,
1 oz. (mils)
Width (mils) ±0.5 16.75 17.25 17.75
Spacing (mils) ±1.0 12.75 13.75 14.75
±1.0 9.7 10.7 11.7
±0.1 2.3 2.4 2.5
Using the dimensions from Ta bl e 3, the Zdiff for the USB
data pairs of the CY4611 FX2 USB to ATA/CF Reference
Design is 90 ohms +0%, –4%.
The designer should take advantage of any help available
from the PCB manufacturer. The key dimensions and tolerances should be available from the manufacturer. Some
manufacturers will perform the impedance calculations for the
designer. Some will provide a service to measure the impedance after the PCB is fabricated.
The above equations yield a good estimate of Z
when the following conditions are true:
November 21, 2002 Document No. 001-43117 Rev. ** 3
Equation 2
and Zdiff
0
For best signal characteristics, a USB 2.0 high-speed design
requires at least a four-layer PCB. It is recommended to
place the primary components (CY7C68013 and its crystal)
on the first (or top) layer, followed by the solid signal ground
plane. The third layer should be the voltage plane followed by
the fourth bottom layer. Figure 3 below illustrates these 4 layers which are used in the PCB for the CY4611 FX2 USB to
ATA/CF Reference Design.
Figure 3. Recommended PCB Stack-up
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PCB Layer Stack-Up
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