Cypress 7C185-35, 7C185-20, 7C185-25, 7C185-15 User Manual
185
CY7C185
8K x 8 Static RAM
Features
• High speed
—15 ns
•Fast t
• Low active power
• Low standby power
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inpu ts and outputs
• Automatic power-down when deselected
Functional Description
The CY7C185 is a high -perform ance CMOS st a tic RAM organized as 8192 words by 8 bits. Easy memory expansion is
DOE
—715 mW
—220 mW
, CE2, and OE features
1
[1]
provided by an activ e LOW chip enable (C E
chip enable (CE
three-state drive rs. This dev ice has an au tomatic po wer-down
feature (CE
when deselected. The CY7 C185 i s in a st andard 300-mil-w ide
), and active LOW output enable (OE) and
2
or CE2), reducing the power consum ption by 70%
1
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE
ing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
selecting the device and enabling the outputs, CE
through A12). Reading the devi ce is acc ompli shed b y
0
0
is HIGH, data on the eight data
2
through I/O7) is written into the memory
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these cond itions, the co ntents of t he location addressed by the informati on on address pi ns are present on th e
eight data input/output pins.
The input/output pin s remain in a hig h-impedance st ate unless
the chip is selected, outputs are enabled, and write enable
) is HIGH. A die coat is used to insure alpha immunity.
(WE
), an active HIGH
1
) controls the writ-
Logic Block Diagram Pin Configurations
DIP/SOJ/SOIC
Top View
NC
1
A
4
A
5
A
6
A
A
A
A
I/O
I/O
I/O
GND
7
A
8
A
9
10
11
12
0
1
2
I/O
0
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
256 x 32 x 8
ARRAY
SENSE AMPS
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
V
WE
CE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
2
3
2
1
0
1
7
6
5
4
3
and OE
1
I/O
6
CE
1
CE
2
WE
OE
Selection Guide
COLUMN DECODER
[2]
0
9
10
A
A
A
A11A
POWER
DOWN
12
I/O
7
7C185-15 7C185-20 7C185-25 7C185-35
Maximum Access Time (ns) 15 20 25 35
Maximum Operating Current (mA) 130 110 100 100
Maximum Sta ndb y Current (mA) 40/15 20/15 20/15 20/15
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. For military specifications, see the CY7C185A data sheet.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05043 Rev. *A Revised September 13, 2002
CY7C185
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[3]
............................................–0.5V to +7.0V
[3]
.........................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Ambient
Temperature V
Electrical Characteristics Over the Operating Range
7C185-15 7C185-20
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Notes:
3. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 VCC +
0.3V
Input LOW Voltage
Input Load Current GND ≤ VI ≤ V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic
Power-Down Current
Automatic
Power-Down Current
[3]
CC
GND ≤ VI ≤ VCC,
–0.5 0.8 –0.5 0.8 V
–5 +5 –5 +5 µA
–5 +5 –5 +5 µA
Output Disabled
[4]
VCC = Max.,
V
= GND
OUT
V
= Max.,
CC
= 0 mA
I
OUT
Max. VCC, CE1 ≥ VIH or CE2 ≤ V
Min. Duty Cycle = 100%
IL
Max. VCC, CE1 ≥ VCC – 0.3V,
–300 –300 mA
130 110 mA
40 20
15 15
or CE2 ≤ 0.3V
≥ VCC – 0.3V or VIN ≤ 0.3V
V
IN
2.2 VCC +
0.3V
CC
V
mA
mA
Document #: 38-05043 Rev. *A Page 2 of 11
CY7C185
Electrical Characteristics Over the Operating Range (continued)
7C185-25 7C185-35
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 VCC +
0.3V
[4]
[3]
CC
GND ≤ VI ≤ VCC,
Output Disabled
VCC = Max.,
= GND
V
OUT
V
= Max.,
CC
= 0 mA
I
OUT
Max. VCC, CE1 ≥ VIH or CE2 ≤ V
Min. Duty Cycle = 100%
Max. VCC, CE1 ≥ VCC – 0.3V
or CE2 ≤ 0.3V
≥ VCC – 0.3V or VIN ≤ 0.3V
V
IN
–0.5 0.8 –0.5 0.8 V
–5 +5 –5 +5 µA
–5 +5 –5 +5 µA
–300 –300 mA
100 100 mA
IL
20 20 mA
15 15 mA
Input LOW Voltage
Input Load Current GND ≤ VI ≤ V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic
Power-Down Current
Automatic
Power-Down Current
2.2 VCC +
0.3V
V
Capacitance
[5]
Parameter Description Te st Conditions Max. Unit
C
IN
C
OUT
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF
VCC = 5.0V
AC Test Loads and Waveforms
R1 481
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
(a) (b)
OUTPUT 1.73V
Ω
R2
255Ω
OUTPUT
INCLUDING
167Ω
5V
5
JIGAND
SCOPE
pF
R1 481Ω
R2
255Ω
3.0V
GND
≤ 5ns
10%
7 pF
ALL INPUT PULSES
90%
90%
10%
≤ 5
ns
Document #: 38-05043 Rev. *A Page 3 of 11
CY7C185
Switching Characteristics Over the Operating Range
[6]
7C185-15 7C185-20 7C185-25 7C185-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
6. T est conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
7. t
HZOE, tHZCE
8. At any given temperature and voltage condition, t
9. The internal write time of the memory is defined by the overlap of CE
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminat es the write .
Read Cycle Time 15 20 25 35 ns
Address to Data Valid 15 20 25 35 ns
Data Hold from Address Change 3 5 5 5 ns
CE1 LOW to Data Valid 15 20 25 35 ns
CE2 HIGH to Data Valid 15 20 25 35 ns
OE LOW to Data Valid 8 9 12 15 ns
OE LOW to Low Z 3 3 3 3 ns
OE HIGH to High Z
CE1 LOW to Low Z
[7]
[8]
7 8 10 10 ns
3 5 5 5 ns
CE2 HIGH to Low Z 3 3 3 3 ns
CE1 HIGH to High Z
[7, 8]
7 8 10 10 ns
CE2 LOW to High Z
CE1 LOW to Power-Up
to HIGH to Power-Up
CE
2
CE1 HIGH to Power-Down
LOW to Power-Down
CE
2
[9]
0 0 0 0 ns
15 20 20 20 ns
Write Cycle Time 15 20 25 35 ns
CE1 LOW to Write End 12 15 20 20 ns
CE2 HIGH to Write End 12 15 20 20 ns
Address Set-up to Write End 12 15 20 25 ns
Address Hold from Write End 0 0 0 0 ns
Address Set-up to Write Start 0 0 0 0 ns
WE Pulse Width 12 15 15 20 ns
Data Set-up to Write End 8 10 10 12 ns
Data Hold from Write End 0 0 0 0 ns
WE LOW to High Z
[7]
7 7 7 8 ns
WE HIGH to Low Z 3 5 5 5 ns
and 30-pF load capacitance.
, and t
are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZWE
is less than t
HZCE
and t
LZCE1
LOW, C E2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
1
for any given device.
LZCE2
Document #: 38-05043 Rev. *A Page 4 of 11
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