CYPRESS CY62148ELL-45ZSX, 628512-70 M Datasheet
CY62148E MoBL
®
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Logic Block Diagram
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
Note
1. SOIC package is available only in 55 ns speed bin.
Features
■ Very high speed: 45 ns
■ Voltage range: 4.5 V to 5.5 V
■ Pin compatible with CY62148B
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 7 µA (Industrial)
■ Ultra low active power
❐ Typical active current: 2.0 mA at f = 1 MHz
■ Easy memory expansion with CE, and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)
[1]
packages
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512 K words by 8-bits. This device features
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE
HIGH). The eight input and output pins (I/O
through I/O7) are placed in a high impedance state when the
device is deselected (CE
HIGH), Outputs are disabled (OE
HIGH), or during an active Write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE
(WE
) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
) and Write Enable
is then written into the location specified on the address pins (A
through A18).
To read from the device, take Chip Enable (CE
Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under
) and Output
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The CY62148E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
0
0
CE
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05442 Rev. *M Revised August 19, 2013
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
A
A
A
9
10
11
12
ROW DECODER
INPUT BUFFER
512K x 8
ARRAY
COLUMN DECODER
15
14
13
A
A
A16A
A
SENSE AMPS
POWER
DOWN
17
18
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
CY62148E MoBL
®
Contents
Pin Configurations ........................................................... 3
Product Portfolio ..............................................................3
Maximum Ratings ............................................................. 4
Operating Range ...............................................................4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ...................................................................... 10
Ordering Information ......................................................11
Ordering Code Definitions ......................................... 11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support ....................... 18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support ..................................................... 18
Document Number: 38-05442 Rev. *M Page 2 of 18
CY62148E MoBL
®
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
Top Vi ew
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
SS
V
CC
A
18
WE
OE
CE
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25 °C.
Figure 1. 32-pin SOIC/TSOP II pinout
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V)
Min Ty p
[2]
Max Typ
Speed
(ns)
CY62148ELL TSOP II Industrial 4.5 5.0 5.5 45 2 2.5 15 20 1 7
Operating ICC (mA)
f = 1 MHz f = f
[2]
Max Typ
[2]
max
Max Typ
Standby I
[2]
SB2
(µA)
Max
CY62148ELL SOIC Industrial /
4.5 5.0 5.5 55 2 2.5 15 20 1 7
Automotive-A
Document Number: 38-05442 Rev. *M Page 3 of 18
CY62148E MoBL
®
Maximum Ratings
Notes
3. V
IL(min)
= –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC(min)
and 200 µs wait time after V
CC
stabilization.
6. SOIC package is available only in 55 ns speed bin.
7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25 °C.
8. Please note that the maximum V
OH
limit for this device does not exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5 V legacy processors
that require a minimum V
IH
of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
9. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This
is applicable to SOIC package only.
10. Chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to
ground potential ................. –0.5 V to 6.0 V (V
DC voltage applied to outputs
in high Z state
[3, 4]
............. –0.5 V to 6.0 V (V
CCmax
CCmax
+ 0.5 V)
+ 0.5 V)
Electrical Characteristics
Over the operating range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[8]
[10]
Output HIGH voltage VCC = 4.5 V, IOH = –1 mA 2.4 – – 2.4 – – V
= 5.5 V, IOH = –0.1 mA – – 3.4
V
CC
Output LOW voltage IOL = 2.1 mA – – 0.4 – – 0.4 V
Input HIGH voltage V
Input LOW voltage V
= 4.5 V to 5.5 V 2.2 – V
CC
= 4.5 V to 5.5 V For TSOPII
CC
package
For SOIC
package
Input leakage current GND < VI < V
CC
Output leakage current GND < VO < VCC, output disabled –1 – +1 –1 – +1 µA
VCC operating supply
current
Automatic CE
power-down current –
CMOS inputs
f = f
= 1/t
max
RC
f = 1 MHz – 2 2.5 – 2 2.5
VCC = V
I
OUT
CMOS levels
CE > VCC – 0.2 V,
V
> VCC – 0.2 V or V
IN
f = 0, V
CC
= V
CC(max)
DC input voltage
[3, 4]
......... –0.5 V to 6.0 V (V
CCmax
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current ....................................................> 200 mA
Operating Range
Device Range
CY62148E Industrial /
Min Typ
–0.5 – 0.8 – – – V
– – – –0.5 – 0.6
–1 – +1 –1 – +1 µA
–1520–1520mA
,
CC(max)
= 0 mA
–1 7 –1 7 µA
< 0.2 V,
IN
Automotive-A
45 ns 55 ns
[7]
Max Min Typ
CC
Ambient
Temperature
–40 °C to +85 °C 4.5 V to 5.5 V
[7]
[8]
– – 3.4
+ 0.5 2.2 – V
[6]
Max
CC
+ 0.5 V)
[5]
V
CC
Unit
[8]
+ 0.5 V
[9]
V
Document Number: 38-05442 Rev. *M Page 4 of 18
CY62148E MoBL
®
Capacitance
3.0 V
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
[11]
Description Test Conditions Max Unit
Input capacitance TA = 25 °C, f = 1 MHz, VCC = V
Output capacitance 10 pF
Thermal Resistance
Parameter
JA
JC
[11]
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Description Test Conditions
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
CC(Typ)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
10 pF
32-pin SOIC
Package
32-pin TSOP II
Package
75 77 C/W
10 13 C/W
Unit
Parameter
[11]
R1 1800
R2 990
R
TH
V
TH
Document Number: 38-05442 Rev. *M Page 5 of 18
5.0 V Unit
639
1.77 V
CY62148E MoBL
®
Data Retention Characteristics
V
CC(min)
V
CC(min)
t
CDR
VDR> 2.0 V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
12. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25 °C.
13. Chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
14. Full device operation requires linear V
CC
ramp from VDR to V
CC(min)
> 100 µs or stable at V
CC(min)
> 100 µs.
Over the operating range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[13]
VCC for data retention 2 – – V
Data retention current VCC = VDR,
Industrial /
–17µA
Automotive-A
CE > VCC – 0.2 V,
V
> VCC – 0.2 V or
IN
< 0.2 V
V
IN
t
CDR
t
R
[14]
Chip deselect to data retention
0––ns
time
Operation recovery time TSOP II 45 – – ns
SOIC 55 – – ns
Data Retention Waveform
Figure 3. Data Retention Waveform
[12]
Max Unit
Document Number: 38-05442 Rev. *M Page 6 of 18
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