Page 1
CY62148E MoBL
®
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Logic Block Diagram
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
Note
1. SOIC package is available only in 55 ns speed bin.
Features
■ Very high speed: 45 ns
■ Voltage range: 4.5 V to 5.5 V
■ Pin compatible with CY62148B
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 7 µA (Industrial)
■ Ultra low active power
❐ Typical active current: 2.0 mA at f = 1 MHz
■ Easy memory expansion with CE, and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)
[1]
packages
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512 K words by 8-bits. This device features
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE
HIGH). The eight input and output pins (I/O
through I/O7) are placed in a high impedance state when the
device is deselected (CE
HIGH), Outputs are disabled (OE
HIGH), or during an active Write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE
(WE
) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
) and Write Enable
is then written into the location specified on the address pins (A
through A18).
To read from the device, take Chip Enable (CE
Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under
) and Output
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The CY62148E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
0
0
CE
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05442 Rev. *M Revised August 19, 2013
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
A
A
A
9
10
11
12
ROW DECODER
INPUT BUFFER
512K x 8
ARRAY
COLUMN DECODER
15
14
13
A
A
A16A
A
SENSE AMPS
POWER
DOWN
17
18
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
Page 2
CY62148E MoBL
®
Contents
Pin Configurations ........................................................... 3
Product Portfolio ..............................................................3
Maximum Ratings ............................................................. 4
Operating Range ...............................................................4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ...................................................................... 10
Ordering Information ......................................................11
Ordering Code Definitions ......................................... 11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support ....................... 18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support ..................................................... 18
Document Number: 38-05442 Rev. *M Page 2 of 18
Page 3
CY62148E MoBL
®
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
Top Vi ew
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
SS
V
CC
A
18
WE
OE
CE
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25 °C.
Figure 1. 32-pin SOIC/TSOP II pinout
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V)
Min Ty p
[2]
Max Typ
Speed
(ns)
CY62148ELL TSOP II Industrial 4.5 5.0 5.5 45 2 2.5 15 20 1 7
Operating ICC (mA)
f = 1 MHz f = f
[2]
Max Typ
[2]
max
Max Typ
Standby I
[2]
SB2
(µA)
Max
CY62148ELL SOIC Industrial /
4.5 5.0 5.5 55 2 2.5 15 20 1 7
Automotive-A
Document Number: 38-05442 Rev. *M Page 3 of 18
Page 4
CY62148E MoBL
®
Maximum Ratings
Notes
3. V
IL(min)
= –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC(min)
and 200 µs wait time after V
CC
stabilization.
6. SOIC package is available only in 55 ns speed bin.
7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25 °C.
8. Please note that the maximum V
OH
limit for this device does not exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5 V legacy processors
that require a minimum V
IH
of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
9. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This
is applicable to SOIC package only.
10. Chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to
ground potential ................. –0.5 V to 6.0 V (V
DC voltage applied to outputs
in high Z state
[3, 4]
............. –0.5 V to 6.0 V (V
CCmax
CCmax
+ 0.5 V)
+ 0.5 V)
Electrical Characteristics
Over the operating range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[8]
[10]
Output HIGH voltage VCC = 4.5 V, IOH = –1 mA 2.4 – – 2.4 – – V
= 5.5 V, IOH = –0.1 mA – – 3.4
V
CC
Output LOW voltage IOL = 2.1 mA – – 0.4 – – 0.4 V
Input HIGH voltage V
Input LOW voltage V
= 4.5 V to 5.5 V 2.2 – V
CC
= 4.5 V to 5.5 V For TSOPII
CC
package
For SOIC
package
Input leakage current GND < VI < V
CC
Output leakage current GND < VO < VCC, output disabled –1 – +1 –1 – +1 µA
VCC operating supply
current
Automatic CE
power-down current –
CMOS inputs
f = f
= 1/t
max
RC
f = 1 MHz – 2 2.5 – 2 2.5
VCC = V
I
OUT
CMOS levels
CE > VCC – 0.2 V,
V
> VCC – 0.2 V or V
IN
f = 0, V
CC
= V
CC(max)
DC input voltage
[3, 4]
......... –0.5 V to 6.0 V (V
CCmax
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current ....................................................> 200 mA
Operating Range
Device Range
CY62148E Industrial /
Min Typ
–0.5 – 0.8 – – – V
– – – –0.5 – 0.6
–1 – +1 –1 – +1 µA
–1520–1520mA
,
CC(max)
= 0 mA
–1 7 –1 7 µA
< 0.2 V,
IN
Automotive-A
45 ns 55 ns
[7]
Max Min Typ
CC
Ambient
Temperature
–40 °C to +85 °C 4.5 V to 5.5 V
[7]
[8]
– – 3.4
+ 0.5 2.2 – V
[6]
Max
CC
+ 0.5 V)
[5]
V
CC
Unit
[8]
+ 0.5 V
[9]
V
Document Number: 38-05442 Rev. *M Page 4 of 18
Page 5
CY62148E MoBL
®
Capacitance
3.0 V
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
[11]
Description Test Conditions Max Unit
Input capacitance TA = 25 °C, f = 1 MHz, VCC = V
Output capacitance 10 pF
Thermal Resistance
Parameter
JA
JC
[11]
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Description Test Conditions
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
CC(Typ)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
10 pF
32-pin SOIC
Package
32-pin TSOP II
Package
75 77 C/W
10 13 C/W
Unit
Parameter
[11]
R1 1800
R2 990
R
TH
V
TH
Document Number: 38-05442 Rev. *M Page 5 of 18
5.0 V Unit
639
1.77 V
Page 6
CY62148E MoBL
®
Data Retention Characteristics
V
CC(min)
V
CC(min)
t
CDR
VDR> 2.0 V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
12. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25 °C.
13. Chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
14. Full device operation requires linear V
CC
ramp from VDR to V
CC(min)
> 100 µs or stable at V
CC(min)
> 100 µs.
Over the operating range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[13]
VCC for data retention 2 – – V
Data retention current VCC = VDR,
Industrial /
–17µA
Automotive-A
CE > VCC – 0.2 V,
V
> VCC – 0.2 V or
IN
< 0.2 V
V
IN
t
CDR
t
R
[14]
Chip deselect to data retention
0––ns
time
Operation recovery time TSOP II 45 – – ns
SOIC 55 – – ns
Data Retention Waveform
Figure 3. Data Retention Waveform
[12]
Max Unit
Document Number: 38-05442 Rev. *M Page 6 of 18
Page 7
CY62148E MoBL
®
Switching Characteristics
Notes
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Notes is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified I
OL/IOH
as shown in the Figure 2 on page 5.
17. SOIC package is available only in 55 ns speed bin.
18. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
19. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
20. The internal wre.ite time of the memory is defined by the overlap of WE
, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Over the operating range
Parameter
Read Cycle
[15, 16]
Description
45 ns 55 ns
[17]
Min Max Min Max
Unit
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read cycle time 45 – 55 – ns
Address to data valid – 45 – 55 ns
Data hold from address change 10 – 10 – ns
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
[20]
[18]
[18, 19]
[18]
[18, 19]
–45–55ns
–22–25ns
5–5–ns
–18–20ns
10–10–ns
–18–20ns
0–0–ns
–45–55ns
Write cycle time 45 – 55 – ns
CE LOW to write end
35–40–ns
Address setup to write end 35 – 40 – ns
Address hold from write end 0 – 0 – ns
Address setup to write start 0 – 0 – ns
WE pulse width
35–40–ns
Data setup to write end 25 – 25 – ns
Data hold from write end 0 – 0 – ns
WE LOW to high Z
WE HIGH to low Z
[18, 19]
[18]
–18–20ns
10–10–ns
Document Number: 38-05442 Rev. *M Page 7 of 18
Page 8
CY62148E MoBL
®
Switching Waveforms
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
IMPEDANCE
I
CC
I
SB
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
DATA VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA I/O
OE
NOTE
26
Notes
21. Device is continuously selected. OE
, CE = VIL.
22. WE
is HIGH for read cycles.
23. Address valid before or similar to CE
transition LOW.
24. Data I/O is high impedance if OE
= VIH.
25. If CE
goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
26. During this period, the I/Os are in output state and input signals must not be applied.
Figure 4. Read Cycle No. 1 (Address Transition Controlled)
[21, 22]
Figure 5. Read Cycle No. 2 (OE Controlled)
[22, 23]
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
[24, 25]
Document Number: 38-05442 Rev. *M Page 8 of 18
Page 9
CY62148E MoBL
®
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA I/O
NOTE
29
Notes
27. Data I/O is high impedance if OE
= VIH.
28. If CE
goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
29. During this period, the I/Os are in output state and input signals must not be applied.
Figure 7. Write Cycle No. 2 (CE Controlled)
[27, 28]
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
[28]
Document Number: 38-05442 Rev. *M Page 9 of 18
Page 10
CY62148E MoBL
®
Truth Table
Note
30. Chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
CE WE OE I/O Mode Power
[30]
H
L H L Data out Read Active (I
L L X Data in Write Active (I
L H H High Z Selected, outputs disabled Active (I
X X High Z Deselect/power-down Standby (ISB)
CC
CC
CC
)
)
)
Document Number: 38-05442 Rev. *M Page 10 of 18
Page 11
CY62148E MoBL
®
Ordering Information
Temperature Grade: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = ZS or S
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
Process Technology: E = 90 nm
Bus width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
CY
XX XX
621
4
8
E
X
LL
X
-
Ta bl e 1 lists the CY62148E MoBL® key package features and ordering codes. The table contains only the parts that are currently
available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress
website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 1. Key features and Ordering Information
Speed
(ns)
45 CY62148ELL-45ZSXI 51-85095 32-pin TSOP II (Pb-free) Industrial
CY62148ELL-45ZSXA 51-85095 32-pin TSOP II (Pb-free) Automotive-A
55 CY62148ELL-55SXI 51-85081 32-pin SOIC (Pb-free) Industrial
CY62148ELL-55SXA 51-85081 32-pin SOIC (Pb-free) Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Ordering Code
Ordering Code Definitions
Package
Diagram
Package Type
Operating
Range
Document Number: 38-05442 Rev. *M Page 11 of 18
Page 12
CY62148E MoBL
®
Package Diagrams
51-85095 *B
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
Document Number: 38-05442 Rev. *M Page 12 of 18
Page 13
CY62148E MoBL
®
Package Diagrams (continued)
51-85081 *E
Figure 10. 32-pin SOIC (450 Mil) S32.45/SZ32.45 Package Outline, 51-85081
Document Number: 38-05442 Rev. *M Page 13 of 18
Page 14
CY62148E MoBL
®
Acronyms Document Conventions
Acronym Description
CE
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE
MoBL More Battery Life
SOIC Small Outline Integrated Circuit
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
WE
Chip Enable
Output Enable
Write Enable
Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
Document Number: 38-05442 Rev. *M Page 14 of 18
Page 15
CY62148E MoBL
®
Document History Page
Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05442
Revision ECN
Orig. of
Change
** 201580 AJU 01/08/04 New data sheet.
*A 249276 SYT See ECN Changed status from Advance Information to Preliminary.
*B 414820 ZSD See ECN Changed status from Preliminary to Final
Submission
Date
Description of Change
Updated Features (Added RTSOP II and removed FBGA Package).
Updated Functional Description (Added RTSOP II and removed FBGA Package).
UpdatedPin Configurations (Added RTSOP II and removed FBGA Package).
Updated Operating Range (Updated Note 5 (Changed V
100 s to 200 s)).
Updated Data Retention Characteristics (Changed maximum value of I
parameter from 2.0 A to 2.5 A, changed minimum value of tR parameter from
100 s to t
Updated Switching Characteristics (Changed minimum value of t
RC
ns).
from 6 ns to 10 ns for both 35 ns and 45 ns speed bin, changed maximum value
of t
parameter from 15 ns to 18 ns for 35 ns speed bin, changed maximum
DOE
value of t
15 ns to 18 ns for 45 ns speed bin, changed minimum value of t
HZOE
, t
parameters from 12 ns to 15 ns for 35 ns speed bin and
HZWE
from 25 ns to 30 ns for 35 ns speed bin and 40 ns to 35 ns for 45 ns speed bin,
changed maximum value of t
bin and 15 ns to 22 ns for 45 ns speed bin, changed minimum value of t
parameter from 12 ns to18 ns for 35 ns speed
HZCE
parameter from 15 ns to 18 ns for 35 ns speed bin and 20 ns to 22 ns for 45 ns
speed bin).
Updated Ordering Information (Corrected typo in Package Name column, also
updated Ordering Codes (to include Pb-free packages)).
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Updated Features (Removed 35 ns speed bin).
Updated Pin Configurations (Removed the Note “DNU pins have to be left floating
or tied to V
Updated Product Portfolio (Removed 35 ns speed bin).
to ensure proper application.” and its reference).
SS
Updated Maximum Ratings (Updated Note 3 to include current limit).
Updated Electrical Characteristics (Removed “L” version of CY62148E, changed
typical value of I
value of I
of I
details, changed typical value of I
value of I
Updated AC Test Loads and Waveforms (Changed the AC test load capacitance
CC
parameter from 12 mA to 15 mA at f = f
CC
SB2
parameter from 1.5 mA to 2 mA at f = 1 MHz, changed maximum
CC
parameter from 2 mA to 2.5 mA at f = 1 MHz, changed typical value
parameter from 0.7 A to 1 A and maximum
parameter from 2.5 A to 7 A).
SB2
max,
from 100 pF to 30 pF in Figure 2, changed test load parameters R1, R2, RTH and
V
from 1838 , 994 , 645 and 1.75 V to 1800 , 990 , 639 and 1.77 V).
TH
Updated Data Retention Characteristics (Changed maximum value of I
parameter from 2.5 A to 7 A, Added typical value for I
Updated Switching Characteristics (Removed 35 ns speed bin, changed minimum
value of t
parameters from 6 ns to 10 ns, changed maximum value of t
t
LZWE
from 22 ns to 18 ns, changed minimum value of t
35 ns, changed minimum value of t
Updated Ordering Information (Updated ordering codes and replaced Package
parameter from 3 ns to 5 ns, changed minimum value of t
LZOE
parameter from 22 ns to 25 ns).
SD
Name column with Package Diagram).
stabilization time from
CC
OHA
SCE
removed I
parameter from 30 ns to
PWE
parameter and its
SB1
parameter).
CCDR
HZCE
CCDR
parameter
parameter
SD
CCDR
and
LZCE
parameter
Document Number: 38-05442 Rev. *M Page 15 of 18
Page 16
CY62148E MoBL
®
Document History Page (continued)
Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05442
Revision ECN
Orig. of
Change
*C 464503 NXR See ECN Updated Product Portfolio (Included Automotive Range).
*D 485639 VKN See ECN Updated Operating Range (Updated V
*E 833080 VKN See ECN Updated Electrical Characteristics (Added V
*F 890962 VKN See ECN Updated Pin Configurations (Added Note 1 related to SOIC package).
*G 2947039 VKN 06/10/2010 Updated Truth Table (Added Note 30 and referred the same note in CE
*H 3006318 AJU 08/23/10 Updated Data Retention Characteristics (Added note 13 and referred the same
*I 3235744 RAME 04/20/2011 Updated Functional Description (Removed the line “For best practice
*J 3302815 RAME 07/14/2011 Updated in new template.
*K 3539544 TAVA 03/01/2012 Updated Electrical Characteristics (Updated Note 9).
*L 3992135 MEMJ 05/06/2013 Updated Functional Description.
Submission
Date
Description of Change
Updated Operating Range (Included Automotive Range).
Updated Electrical Characteristics (Included Automotive Range).
Updated Data Retention Characteristics (Included Automotive Range).
Updated Switching Characteristics (Included Automotive Range).
Updated Ordering Information (Updated ordering codes (Included Automotive
parts and their related information)).
to 4.5 V to 5.5 V).
CC
parameter for SOIC package, added
Note 9 and referred the same note in V
IL
parameter for SOIC package).
IL
Updated Product Portfolio (Included Automotive-A range and removed
Automotive-E range).
Updated Operating Range (Included Automotive-A range and removed
Automotive-E range).
Updated Electrical Characteristics (Included Automotive-A range and removed
Automotive-E range, added Note 10 related to I
I
parameter).
SB2
Updated Data Retention Characteristics (Included Automotive-A range and
and referred the same note in
SB2
removed Automotive-E range).
Updated Switching Characteristics (Included Automotive-A range and removed
Automotive-E range).
Updated Ordering Information (Updated ordering codes (Added Automotive-A part
and its related information, removed Automotive-E part and its related information).
Updated Ordering Information (Added “CY62148ELL-45ZSXA” part number).
Updated Package Diagrams.
Added Sales, Solutions, and Legal Information.
note in I
Added Ordering Code Definitions.
parameter).
CCDR
Added Acronyms and Units of Measure.
Updated in new template.
recommendations, refer to the Cypress application note AN1064, SRAM System
Guidelines”).
Updated Package Diagrams.
Updated Package Diagrams.
column).
Updated Electrical Characteristics (Added one more Test Condition
“V
= 5.5 V, IOH = –0.1 mA” for VOH parameter and its corresponding values).
CC
Updated Package Diagrams:
spec 51-85081 – Changed revision from *D to *E.
Completing Sunset Review.
Document Number: 38-05442 Rev. *M Page 16 of 18
Page 17
CY62148E MoBL
®
Document History Page (continued)
Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05442
Revision ECN
*M 4099045 VINI 08/19/2013 Updated Switching Characteristics:
Orig. of
Change
Submission
Date
Added Note 15 and referred the same note in “Parameter” column.
Updated in new template.
Description of Change
Document Number: 38-05442 Rev. *M Page 17 of 18
Page 18
CY62148E MoBL
®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC® Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05442 Rev. *M Revised August 19, 2013 Page 18 of 18
More Battery Life is a trademark and MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of
their respective holders.
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