CYPRESS 39K30, 39K50, 39K100, 39K165, 39K200 User Manual

Features

• High density —30K to 200K usable gates

—512 to 3072 macrocells —136 to 428 maximum I/O pins

—Twelve dedicated inputs including four clock pins,

four global I/O control signal pins and four JTAG interface pins for boundary scan and reconfigurability

• Embedded memory —80K to 480K bits embedded SRAM

• 16K to 96K bits of (dual-port) channel memory

• High speed – 233-MHz in-system operation

•AnyVolt™ —3.3V, 2.5V,1.8V, and 1.5V I/O capability

• Low-power operation —0.18-mm six-layer metal SRAM-based logic p roces s —Full-CMOS implementation of product term array —Standby current as low as 5mA

• Simple timing model —No penalty for using full 16 product terms/macroce ll

—No delay for single product term steering or sharing

• Flexible clocking —Spread Aware™ PLL drives all four clock networks

—Four synchronous clock networks per device —Locally generated product term clock —Clock polarity control at each register

interface

• Allows 0.6% spread spectrum input clocks

• Several multiply, divide and phase shift options

Delta39K™ ISR™

CPLD Fami

CPLDs at FPGA Densities™

• Carry-chain logic for fast and efficient arithme tic operations

• Multiple I/O standards supported

—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-programmable Bus Hold capability on each I/O pin

• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec, rev. 2.2)

• CompactPCI hot swap ready

• Multiple package/pinout offering across all densities

—208 to 676 pins in PQFP, BGA, and FBGA packages —Simplifies design migration across density —Self-Boot™ solution in BGA and FBGA packages

• In-System Reprogrammable™ (ISR™)

—JTAG-compliant on-board programming —Design changes do not cause pinout changes

• IEEE114 9.1 JTAG boundary scan

Development Software

• Warp

—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing —Active-HDL FSM graphical finite state machine editor —Active-HDL SIM post-synthesis timing simulator —Architecture Explorer for detailed design analysis —Static Timing Analyzer for critical path analysis —Available on Windows

Windows NT™ for $99 —Supports all Cypress programmable logic products



95/98/2000/XP™ and

Delta39K™ ISR CPLD Family Members

Typical

[1]

Device

39K30 16K – 48K 512 64 16 174 233 7.2 5 mA

39K50 39K100 46K – 144K 1536 192 48 302 222 7.5 10 mA 39K165 77K – 241K 2560 320 80 386 181 8.5 20 mA 39K200 92K – 288K 3072 384 96 428 181 8.5 20 mA

Notes:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-03039 Rev. *H Revised August 1, 2003

Gates

23K – 72K 768 96 24 218 233 7.2 5 mA

values are with PLL not utilized, no output load and stable inputs.

Macrocells

Cluster

memory

(Kbits)

Channel memory

(Kbits)

Maximum

I/O Pins

MAX2

(MHz)

Speed-tPD Pin-to-Pin

(ns)

Standby I

TA = 25°C

3.3/2.5V

[2]

Delta39K™ ISR

™

[3]

233 200 181 125 83

Delta39K Speed Bins

Device V

39K30 3.3/2.5V X X X

39K50 3.3/2.5V X X X 39K100 3.3/2.5V X X X 39K165 3.3/2.5V X X X 39K200 3.3/2.5V X X X

CPLD Fami

Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs

Self-Boot Solution

208 EQFP

Device

39K30 136 174 174

39K50 136 180 218 218 39K100 136 180 302 294 302 39K165 136 356 294 386 39K200 136 368 294 428

Notes:

3. Speed bins shown here are for commercial operating range. Please refer to Delta39K ordering information on industrial-range speed bins on page 38.

4. Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000 programming/erase cycles and can retain data for at least 100 years.

28 × 28 mm

0.5-mm pitch

256 FBGA

17 × 17 mm

1.0-mm pitch

484-FBGA

23 × 23 mm

1.0-mm pitch

256-FBGA

17 × 17 mm

1.0-mm pitch

388-BGA

35 × 35 mm

1.27-mm pitch

[4]

484-FBGA

23 × 23 mm

1.0-mm pitch

676-FBGA

27 × 27 mm

1.0-mm pitch

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Delta39K™ ISR

™

GCLK[3:0]

PLL and Clock MUX

GCLK[3:0]

LB 0 LB 1 LB 2

Cluster

RAM

GCLK[3:0]

LB 0 LB 1 LB 2

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

GCTL[3:0]

Channel

RAM

Channel

RAM

LB 0 LB 1 LB 2

Cluster

RAM

LB 0 LB 1 LB 2

Cluster

RAM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

PIM

4 4

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

PIM

LB 0 LB 1 LB 2

Cluster

RAM

LB 0 LB 1 LB 2

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

LB 7

LB 6 LB 5 LB 4LB 3

Cluster

RAM

CPLD Fami

I/O Bank 6I/O Bank 7

LB 0 LB 1

Channel

RAM

Channel

RAM

LB 2

Cluster

RAM

LB 0 LB 1 LB 2

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

Channel

RAM

I/O Bank 5

GCLK[3:0]

LB 0 LB 1

I/O Bank 1 I/O Bank 0

LB 2

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

LB 0 LB 1 LB 2

Cluster

RAM

4 4

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

PIM

Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure

General Description

The Delta39K family, based on a 0.18-mm, six-layer metal CMOS logic process, offers a wide range of high-density solutions at unparalleled system performance. The Delta39K family is designed to combine the high speed, predictable timing, and ease of use of CPLDs with the high densities and low power of FPGAs. With devices ranging from 30,000 to 200,000 usable gates, the family features devices ten times the size of previously available CPLDs. Even at these large densities, the Delta39K family is fast enough to implement a fully synth esizable 64-bit, 66-MHz PCI core.

LB 0 LB 1 LB 2

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

LB 0 LB 1 LB 2

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4LB 3

Cluster

RAM

Channel

RAM

I/O Bank 4

I/O Bank 3I/O Bank 2

The architecture is based on Logic Block Clusters (LBC) that are connected by Horizontal and Vertical (H and V) routing channels. Each LBC features eight individual Logic Blocks (LB) and two cluster memo ry b loc ks . Adj ac ent to eac h LBC i s a channel memory block, w hich can be acces sed directly from the I/O pins. Both types of memory blocks are highly configurable and can be c as ca ded i n w id t h and depth. See Figure 1 for a block diagram of the Delta39K architecture.

All the members of th e Delt a39K fa mi ly have C ypres s’ s hig hly regarded In-System Reprogrammability (ISR) feature, which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to recon-

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Delta39K™ ISR

™

figure the devices without having design changes cause pinout or timing changes in most cases. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins respectively. Superior routability, simple timing, and the ISR allows users to chan ge exist ing logic de signs whil e simultaneously fixing pinout assignments and maintaining system performance.

The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and tim ing requirements. The Delt a3 9K family also features user programmable bus-hold and slew rate control capabilities on each I/O pi n.

AnyVolt Interface

All Delta39KV devices feature an on-chip regulator, which accepts 3.3 V or 2.5V on the V to 1.8V internally , the voltage level at which the core operate s.

supply pins and step s it down

With Delta39K’s AnyVolt technology, the I/O pins can be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devices are 3.3V-tolerant regardless of V

or VCC settings.

CCIO

Table 1.

Device V

39KV 3.3V or 2.5V 3.3V or 2.5V or 1.8V or 1.5V

CCIO

[5]

CPLD Fami

Global Routing Description

The routing architecture of the Delta39K is made up of horizontal and vertical (H and V) routing channels. These routing channels allow signals from each of the Delta39K architectural com ponents to c ommunicate with on e another . In addition to the horizontal and vertical routing channels that interconnect the I/O ban ks, chann el memory bl ocks, and logi c block clusters, each LBC contains a Programmable Interconnect Matrix (PIM™), which is used to route signals among the logic blocks and the cluster memory blocks.

Figure 2 is a block diagram of the routing channels that interface within the Del t a39 K arc hit ecture. The LBC is exactly the same for every member of the Delta39K CPLD family.

Logic Block Cluster (LBC)

The Delta39K architecture consists of several logic block clusters, each of which have eight Logic Blocks (LB) and two cluster memory blocks connected via a Programmable Interconnect Matrix (PIM) as shown in Figure 3. Each cluster memory block consists of 8-Kbit single-port RAM, which is configurable as synchronous or asynchronous. The cluster memory blocks can be cascaded with other cluster memory blocks within the same LBC as well as other LBCs to implement larger m emory func tions. If a clus ter me mory bloc k is not specifically utilized by the designer, Cypress’s Warp software can au tom ati ca lly us e it to implement large blo ck s of logic.

All LBCs interface with each other via horizontal and vertical routing channels.

Note:

5. For HSTL only.

I/O Block

Cluster

PIM

Channel Memory

Cluster

Block

Memory

Block

Cluster

Memory

Block

I/O Block

Pin inputs from the I/O cells drive dedicated tracks in the horizontal and vertical routing channels

Figure 2. Delta39K Routing Interface

Channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels

H-to-V

PIM

V-to-H

PIM

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Delta39K™ ISR

™

Clock Inputs

Logic Block

CC CC CC

Logic Block

Cluster

Memory

Horizontal Routing

25 8

64 Inputs From

Channel

GCLK[3:0]

PIM

144 Outputs to

Horizontal and Vertical

cluster-to-channel PIMs

Logic

Block

Logic

Block

Logic

Block

Logic

Block

Cluster

Memory

CC = Carry Chai

64 Inputs From Vertical Routing Channel

CPLD Fami

CC CC CC

Figure 3. Delta39K Logic Block Cluster Diagram

Logic Block

The LB is the basic buildin g block of the Delta 39K architecture. It consists of a product term array, an intelligent product-term allocator, and 16 macrocells.

Product Term Array

Each logic block features a 72 x 83 programmable product term array. This array accepts 36 inputs from the PIM. These inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. Active LOW and active HIGH ver sions of each of thes e input s are generated to create the full 72-input field. The 83 product terms in the array can be created from any of the 72 inputs.

Of the 83 product terms, 80 are for general-purpose use for the 16 macrocell s in the logic block. T wo of the remaining three product terms in the logic bloc k are used as asynchro nous set and asynchronous reset product te rms. The fi nal produc t term is the Product Term clock (PTCLK) and is shared by all 16 macrocells within a logic block.

Product Term Allocator

Through the product term allocator, Warp software automatically distributes the 80 pro duct terms as needed amo ng the 16 macrocells in the logic block. The product term allocator

provides two important capabilities without affecting performance: product term steering and product term sharing.

Product Term Steering

Product term steering is the process of assigning product terms to macroce lls as n eeded . For ex ampl e, if o ne macr ocell requires ten product te rms whil e anoth er needs just thre e, the product term allocator will “steer” ten product terms to one macrocell and three to the other. On Delta39K devices, product terms are stee red on an indivi dual ba sis. An y nu mber between 1 and 16 product terms can be steered to any macrocell.

Product Term Sharing

Product term sharing is the pr ocess of usin g the same product term among multiple macrocell s. For example, i f more than one function has one or more produ ct terms in it s equation th at are common to other functions, those product terms are only programmed once. The Delta39K product term allocator allows sharing across groups of four macrocells in a variable fashion. The software automatically takes advantage of this capability so that the user does not have to intervene.

Note that neither product term sharing nor product term steering have any effect on the speed of the product. All steering and sharing c onfiguration s have been incorporated i n the timing specifications for the Delta39K devices.

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Delta39K™ ISR

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Macrocell

Within each logic block there are 16 macrocells. Each macrocell accepts a sum of up to 16 product terms from the product term array. The sum of these 16 product terms can be output in either registered or combinatorial mode. Figure 4 displays th e b l oc k dia g r am of th e m ac r oc el l. T h e re g is t er c an be asynchronously preset or asynchronously reset at the macrocell level with the separate preset and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be preset or reset based on an AND expression or an OR expression.

An XOR gate in the Delta39K macrocell allows for many different types of equations to be realized. It can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a to ggl e to tu rn the D flip-flop into a T flip-flop. The carry-chain input mux allows additional flexibil ity fo r the i mplem ent ation of dif fere nt type s of logic. The macrocell can utilize the carry chain logic to implement adders, subtractors, magnitude comparators, parity tree, or even generic XOR logic. The output of the macrocell is either registered or combinatorial.

Carry Chain Logic

The Delta39 K macrocell featu res carry chain l ogic which is used for fast and eff ici en t imp lementation of arithmetic ope rations. The carry logic connects macrocells in up to four logic blocks for a total of 64 macrocells. Effective data path opera-

CPLD Fami

tions are implemented through the use of carry-in arithmetic, which drives through the circuit quickly. Figure 4 shows that the carry chain logic within the macrocell consists of two product terms (CPT0 and CPT1) from the PTA and an input carry-in for carry logic. The inputs to the carry chain mux are connected directly t o the produc t terms in the PTA. The output of the carry chain mux generates the carry-out for the next macrocell in the logic bl ock as wel l as the l ocal car ry inpu t that is connected to an inp ut of the XOR input m ux. Carry-i n and a configuration bit are inputs to an AND gate. This AND gate provides a method of segmenting the carry chain in any macrocell in the logic block.

Macrocell Clocks

Clocking of the register is highly flexible. Four global synchronous clocks (GCLK[3:0]) and a PTCLK are available at each macrocell register. Furthermore, a clock polarity mux within each macrocell allows the register to b e clocked on the rising or the falling edge (see macrocell diagram in Figure 4).

PRESET/RESET Configurations

The macrocell register can be asynchronously preset and reset using the PRESET and RESET mux. Both signals are active high and c an be controll ed by either o f two Preset/Res et product terms (PRC[1:0] in Figure4) or GND. In situations where the PRESET and RESET are active at the same time, RESET takes priority over PRESET.

(from macrocell n-1)

CPT0 CPT1

FROM PTM

Up To 16 PTs

GCLK[3:0]

PTCLK

Carry In

Clock Mux

Carry Chain

Mux

Carry Out

(to macrocell n+1)

PRESET

0 1

XOR Input

Mux

PRC[1:0]

0 1

Mux

Clock

Polarity

Mux

RESET Mux

Output

Mux

To PIM

PSET

RES

Figure 4. Delta39K Macrocell

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Delta39K™ ISR

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Embedded Memory

Each member of the Delta39K family contains two types of embedded memory blocks. The channel memory block is placed at the intersection of horizontal and vertical routing channels. Each chan nel memor y block is 4096 bit s in size an d can be configured as asynchrono us or synchro nous Dual- Port RAM, Single-Port RAM, Read-Only memory (ROM), or synchronous FIFO memory. The memory organization is configurable as 4K × 1, 2K × 2, 1K × 4 and 512K × 8. The second type of memory block is located within each LBC and is referred to as a cluster memory block. Each LBC contains two cluster memory blocks that are 8192 bits in size. Similar to the channel memor y blocks, the c luster memory blocks ca n be configured as 8K × 1, 4K × 2, 2K × 4 and 1K × 8 asynchronous or synchronous Single-Port RAM or ROM.

Cluster Memory

Each logic blo ck clu ster o f the Delt a39 K cont ain s two 8192-b it cluster memory blocks. Figure 5 is a block diagram of the cluster memory block and the interface of the cluster memory block to the cluster PIM.

The output of the c luster memory block c an be optionally re gistered to perform synchronous pipelining or to register asynchronous Read and Write operations. The output registers contain an as ynchronous RESET which can be use d in any type of sequential logic circuits (e.g., state machines).

There are four global clocks (GCLK[3:0]) and one local clock available for the i nput and t he out put regis ters. The l ocal cloc k for the input registers is independent of the one used for the output registers. The local clock is generated in the user design in a macrocell or comes from an I/O pin.

CPLD Fami

Cluster Memory Initialization

The cluster memory po wers up in an undefined st ate, but is set to a user-defined k nown state durin g configuration. T o facilit ate the use of look-up-t able (LUT) logic and ROM applications, th e cluster memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks.

Channel Memory

The Delta39K architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. The channel memory is a 4096-bit embedded memory block that can be configured as asynchronous or synchronous single-port RAM, dual-port RAM, ROM, or synchronous FIFO memory.

Data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. All data and FIFO logic output s drive dedicated trac ks in the horizont al and vertical routing channels. The clocks for the channel memory bloc k are selected from f our global clocks a nd pin inputs from the horizontal and vertical channels. The clock muxes also inc lude a p olarity mux for e ach clock s o that t he user can choose an inverted clock.

Dual-Port (Channel Memory) Configuration

Each port has distinct addre ss inputs, as wel l as separate dat a and control inputs that can be accessed simultaneously. The inputs to the Dual-Port mem ory are driv en from the hori zont al and vertical routing channels. The data outputs drive dedicated tracks in the routing channels. The interface to the routing is such that Port A of the Dual-Po rt interface s primarily with the horizontal routing channel and Port B interfaces primarily with the vertical routing channel.

Write

Control

Logic

1024x8

Asynchronous

SRAM

Cluster PIM

GCLK[3:0]

Local CLK

DOUT[7:0]

RESET

GCLK[3:0]

Local CLK

DIN[7:0]

ADDR[12:0]

Read

Control

Logic

Row Decode (1024 Rows)

Pulse

Write

5:1

Figure 5. Block Diagram of Cluster Memory Block

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Delta39K™ ISR

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The clocks for each port of the Dual-Port configuration are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs of the dualport memory can also be registered. Clocks for the output registers are also selected from four global clocks and two local clocks. O ne c lo ck p ola rity m ux p er port al low s t he us e of true or complement polarity for input and output clocking purposes.

Arbitration

The Dual-Port configuration of the Channel Memory Block provides arbitrat ion when bot h ports a ccess the sam e address at the same time. Depending on the memory operation being attempted, one port always gets priority. See Table 2 for details on which port gets priority for Read and Write operations. An active-LOW “Address Match” signal is generated when an address collision occurs.

Table 2. Arbitration Result: Address Match Signal Becomes Active

Port A Port B

Read Read No arbitration

Write Read Port A gets

Read Write Port B gets

Write Write Port A gets

FIFO (Channel Memory) Configuration

The channel memory blocks are also configurable as synchronous FIFO RAM. In the FIFO mode of operation, the channel memory block supports all normal FIFO operations without the use of any general-purpose logic resources in the device.

Result of

Arbitration Comment

Both ports read at the

required

priority

same time If Port B requests first then

it will read the current data. The output will then change to the newly written data by Port A

If Port A requests first then it will read the current data. The output will then change to the newly written data by Port B

Port B is blocked until Port A is finished writing

The FIFO block contains all of the necessary FIFO flag logic, including the Read an d Write address poi nters. The FIFO flags include an empty/ful l flag (EF mable almost-empty /ful l (PAEF uration has the ab ility to perform simultaneo us Read and W rite operations using two separate clocks. These clocks may be tied together for a single operation or may run independently for asynchronous Re ad/Write (with re gard to each other) appl ications. The data and control inputs to the FIFO block are driven from the horizontal or vertical routing channels. The data and flag o utpu t s are driv en onto dedicated routing trac k s in both the horizont al and vertical routing channels . This allows the FIFO blocks to be exp anded by using multipl e FIFO bloc ks on the same horizon tal or vertical rout ing ch annel without any speed penalty.

In FIFO mode, the Write and Read ports are controlled by separate clock and enable signals. The clocks for each port are selected from four global clocks and two local clocks.

One local clock is sourced from the horizont al channel an d the other from the vertical channel. The data outputs from the Read port of the FIFO can also be registered. One clock polarity mux per port allo ws using true or com plem ent pol arity for Read and Write operations. The Write operation is controlled by the clock and the Write enable pin. The Read operation is controlled by the clock and the Read enable pin. The enable pins can be sourced from horizontal or vertical channels.

Channel Memory Initialization

The channel memory powers up in an undefined state, but is set to a user-defined known state du ring configuration. T o faci litate the use of look-up-table (LUT) logic and ROM applications, the channel memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks.

Channel Memory Routing Interface

Similar to LBC outputs, the channel memory blocks feature dedicated tracks in the hori zontal and vertical routing channels for the data outputs and the flag outputs, as shown in Figure 6. This allows the channel memory blocks to be expanded easi ly. These dedic ated li nes can b e route d to I/O pins as chip outputs or to other logic block clusters to be used in logic equations.

), half-full flag (HF), an d program-

CPLD Fami

) flag output. The FIFO confi g-

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Delta39K™ ISR

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All channel memory

inputs are driven from

the routing channels

4096-bit Dual-Port

Array

Configurable as

Async/Sync Dual-Port

or Sync FIFO

Configurable as

4K x 1, 2K x 2, 1K x 4,

and 512 x 8 block sizes

All channel memory outputs

drive dedicated tracks in the

routing channels

Horizontal Channel

Figure 6. Block Diagram of Channel Memory Block

Vertical Channel

CPLD Fami

Global Cloc

Signals

GCLK[3:0]

I/O Banks

The Delta39K interfaces the horizontal and vertical routing channels to the pins through I/O banks. There are eight I/O banks per device as shown in Figure 7, and all I/Os from an I/O bank are loca ted in the sam e section o f a packa ge for PCB layout convenience.

Delta39K devices support True Vertical Migration™ (i.e., for each package type, Delta39K devices of different densities keep given pins in the same I/O banks). This allows for easy and simple im plementation o f multiple I/O s tandards during the design and proto typ ing ph ase, before a final dens ity h as bee n determined. Please refer to the application n ote titl ed “Family,

Package and Densi ty Migration in Delt a 39K and Quantum3 8K CPLDs.”

Each I/O bank contain s several I/O cells, and each I/O ce ll contains an input/output register, an output enable register, programmabl e slew rate contr ol and progr ammabl e bus h old control logic. Each I/O cell drives a pin output of the device; the cell also suppli es an i npu t to the d ev ic e tha t c onn ec ts to a dedicated track in the assoc ia ted rout ing channel.

Each I/O bank can use any supported I/O standard by supplying appropriate V uring the I/O through the Warp software. All the V V and V number of I/O standards sup ported by an I/O bank at any given time.

The number of I/Os which can be used in each I/O bank depend on the type of I/O s tand ards an d the num ber of V and GND pins being used. This restriction is derived from the electromigration limit of the V chip. Please refer to the note on page 17 and the application note titled “Delta39K Fam ily Device I/ O St andards and Config- urations” for details.

and V

REF

pins in an I/O bank must be connected to the same V

CCIO

voltage respectively. This requirement restricts the

CCIO

voltages and con fig-

CCIO

and GND bussing on the

REF

and

REF

CCIO

I/O Cell

Figure 8 is a block diagram of the Delta39K I/O cell. The I/O cell contains a thre e-s t ate inp ut bu ffer, an outp ut bu ffer, an d a register that can be configured as an input or output register. The output b uffer has a sl ew rate cont rol option that can be used to configure the output for a slower slew rate. The input of the device and the pin output can each be configured as registered or combinatorial; however, only one path can be configured as registered in a given design.

The output enable in an I/O cell can be selected from one of the four global control signals or from one of two Output Control Channel (OCC) signals. The output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. The selection is done via a mux that includes V inputs.

and GND as

bank 6bank 7

bank 0bank 1

Delta39K

bank 4 bank 5

bank 2 bank 3

Figure 7. Delta39K I/O Bank Block Diagram

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Delta39K™ ISR

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From

Output PIM

To Routing

Channel

Registered OE

OE Mux

Clock

Polarity

Mux

DQ E

RES

Output Mux

Input

Mux

Global Clock Signals

Global I/O Control Signals

Output Control Channel OCC

Clock Mux

Mux

RES

Bus

Hold

Slew Rate

Control

CPLD Fami

I/O

Figure 8. Block Diagram of I/O Cell

I/O Signals

There are four dedicated inputs (GCTL[3:0]) that are used as Global I/O Control Signals available to every I/O cell. These global I/O control signals may be used as output enables, register resets and register clock enables as shown in Figure 8. These global control signals, driven from four dedicated pins, can only be used as active-high signals and are available only to the I/O cells thereby implementing fast resets, register and output enables.

In addition, there are six OCC signals available to each I/O cell. These control signals may be used as output enables, register resets and register clock enables as shown in Figure 8. Unlike global control signals, these OCC signal can be driven from internal logic or and I/O pin.

One of the four global clocks can be selected as the clock for the I/O cell regi ster . The c lock mux out put is an input to a cl ock polarity mux that all ows the input /output register to be c locked on either edge of the clock

Slew Rate Control

The output buffer has a slew rate control option. This allows the output buffer to slew at a fast rate (3 V/ns) or a slow rate (1 V/ns). All I/Os default to fast slew rate. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance.

Table 3.

I/O Standards

I/O

Standard V

(V) V

REF

CCIO

Termination

Voltage (VTT)

Min. Max.

LVTTL N/A 3.3V N/A

LVCMOS 3.3V N/A LVCMOS3 3.0V N/A LVCMOS2 2.5V N/A

LVCMOS18 1.8V N/A

3.3V PCI 3.3V N/A GTL+ 0.9 1.1 N/A 1.5

SSTL3 I 1.3 1.7 3.3V 1.5

SSTL3 II 1.3 1.7 3.3V 1.5

SSTL2 I 1.15 1.35 2.5V 1.25

SSTL2 II 1.15 1.35 2.5V 1.25

HSTL I 0.68 0.9 1.5V 0.75

HSTL II 0.68 0.9 1.5V 0.75

HSTL III 0.68 0.9 1.5V 1.5

HSTL IV 0.68 0.9 1.5V 1.5

Document #: 38-03039 Rev. *H Page 10 of 86

Delta39K™ ISR

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Programmable Bus Hold

On each I/O pin, user-programmable-bus-hold is included. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in businterface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device with out cutti ng trac e co nne ctions to

or GND. For more information, see the application note

titled “Understanding Bus-Hold–A Feature of Cypress CPLDs.”

Clocks

Delta39K has four dedicated clock input pins (GCLK[3:0]) to accept system clocks. One of these clocks (GCLK[0]) may be selected to drive an on-chip phase-locked loop (PLL) for frequency modulation (see Figure 9 for details).

The global clock tree for a Delta39K device can be driven by a combination of the dedicated clock pins and/or the PLLderived clocks. The global clock tree consists of four global clocks that go to e ve ry m ac roc el l, m em ory b loc k, and I/O cell.

Clock Tree Distribution

The global clock tree performs two prima ry functions. Firs t, the clock tree generates the fou r global clocks by mult iplexing four dedicated clocks from the package pins and four PLL driven clocks. Second, the clo ck tree distributes the fo ur global clocks to every cluster, channel memory, and I/O block on the die. The global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay.

Spread Aware PLL

Each device in the Delta39K family features an on-chip PLL designed using S pre ad Aware t echnology for lo w EMI applications. In general, PLLs are used to implement time-divisionmultiplex circuits to achieve higher performance with fewer device resources.

off-chip signal (external feedback)

INTCLK0, INTCLK1, INTCLK2, INTCLK3

GCLK1

Clock Tree

Delay

GCLK0

Source

Clock

PLL

X1, X2, X3, X4, 5X,

X6, X8, X16

CLK[3:0]

Lock

Clk

Clk 45

Clk

Clk 135

Clk 180

Clk

225

Clk

270

Clk

315

Figure 9. Block Diagram of Spread Aware PLL

Phase selection

CPLD Fami

For example, a system th at operates on a 32-bit dat a path th at runs at 40 MHz can be implemented with 16-bit circuitry that runs internally at 80 MHz. PLLs can also be used to take advantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times.

There are several freq uen cy multi pl y (X1 , X2 , X3, X4, X5, X6, X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options available to create a wide range of clock frequencies from a single clock input (GCLK[0 ]). For increased flexibility , there are seven phase shifting options which allow clock skew/deskew by 45°, 90°, 135°, 180°, 225°, 270°, or 315°.

The Spread Aware feature refers to the ability of the PLL to track a spread-spectrum input clock such that its spread is seen on the outp ut clock wi th the PLL s taying l ocked. The total amount of spread on th e inpu t clock shou ld be li mited to 0.6 % of the fundamental frequency. Spread Aware feature is supported only with X1, X2, and X4 multiply options.

The Voltage Controlled Oscillator (VCO), the core of the Delta39K PLL is designed to operate within the frequency range of 100 MHz to 266 MHz. Hence, the multiply option combined with input (GCLK[0]) frequency should be selected such that this VCO operating frequency requirement is met. This is demonstrated in Table 4 (columns 1, 2, and 3).

Another feature of this PLL is the ability to drive the output clock (INTCLK) of f the Delt a39K chip to clock o ther devi ces on the board, as shown in Figure 9 above. This off-chip clock is half the frequency o f the out put clo ck as it h as to go through a register (I/O register or a macrocell register).

This PLL can also be used for board de-skewing purpose by driving a PLL output clock off-chip, routing it to the other devices on the board and feed ing it ba ck to the PLL’s external feedback input (GCLK[1]). When this feature is used, only limited multiply, divide and phase shift options can be used. Table 4 describes the valid multiply and d ivide option s that can be used without extern al feedback. Table 5 describes the valid multiply and divide options that can be used with an external feedback.

Normal I/O signal path

Any Register (TFF)

Divide

¸ 1-6,8,16

Divide

¸ 1-6,8,16

Divide

¸ 1-6,8,16

Divide

¸ 1-6,8,16

Send a global clock off

chip

Lock Detect/IO pin

GCLK0

GCLK1

GCLK2

GCLK3

INTCLK

INTCLK1

INTCLK2

INTCLK3

Document #: 38-03039 Rev. *H Page 11 of 86

Delta39K™ ISR

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Table 6 describes the valid phase shift options that can be used with or without an external feedback.

Table 7 is an example of the effect of all the available divide and phase shift options on a VCO output of 250 MHz. It also shows the effect of division on the duty cycle of the resultant clock. Note that the duty cycle is 50-50 when a VCO output is divided by an even number. Also note that the phase shift applies to the VCO output and not to the divided output.

Table 4. Valid PLL Multiply and Divide Options—without External Feedback

Input Frequency

(GCLK[0])

(MHz)

PLLI

DC–12.5 N/A N/A N/A DC–12.5 DC–6.25 100–133 1 100–133 1–6, 8, 16 6.25–133 3.125–66 50–133 2 100–266 1–6, 8, 16 6.25–266 3.125–133

33.3–88.7 3 100–266 1–6, 8, 16 6.25–266 3.1–266 25–66 4 100–266 1–6, 8, 16 6.25–266 3.125–133 20–53.2 5 100–266 1–6, 8, 16 6.25–266 3.1–133

16.6–44.3 6 100–266 1–6, 8, 16 6.25–266 3.1–133

12.5–33 8 100–266 1–6, 8, 16 6.25–266 3.125–133

12.5–16.625 16 200–266 1–6, 8, 16 6.25–266 3.125–133

Valid Multiply Options Valid Divide Options

Value

VCO Output

Frequency (MHz) Value

For more details o n th e arc hi tec ture an d o pera tio n of thi s PL L please refer to the applicat ion note entitled “Delta3 9K PLL and Clock Tree”.

Output Frequency (INTCLK[3:0])

PLLO

(MHz)

CPLD Fami

Off-chip Clock

Frequency

Table 5. Valid PLL Multiply and Divide Options—With External Feedback

Valid Multiply Options Valid Divide Options

Input (GCLK) Frequency

50–133 1 100–266 1 100–266 50–133 25–66.5 1 100–266 2 50–133 25–66.5

16.67–44.33 1 100–266 3 33.33–88.66 16.67–44.33

12.5–33.25 1 100–266 4 25–66.5 12.5–33.25

12.5–26.6 1 125–266 5 25–53.2 12.5–26.6

12.5–22.17 1 150–266 6 25–44.34 12.5–22.17

12.5–16.63 1 200–266 8 25–33.25 12.5–16.63

Table 6. Recommended PLL Phase Shift Options

0°,45°, 90°, 135°, 180°, 225°, 270°, 315° 0°

Table 7. Timing of Clock Phases for all Divide Options for a V

Divide Factor

1 4 40–60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2 8 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3 12 33–67 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 16 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5 20 40–60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6 24 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 8 32 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

16 64 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

(MHz)

PLLI

Period

(ns) Duty Cycle%0°(ns)

Value

Without External Feedback With External Feedback

VCO Output

Frequency (MHz) Value

45°

(ns)

90°

(ns)

Output (INTCLK) Frequency

Output Frequency of 250 MHz

135°

(ns)

180°

(ns)

PLLO

(MHz)

225°

(ns)

Off-chip Clock

Frequency

270°

(ns)

315°

(ns)

Document #: 38-03039 Rev. *H Page 12 of 86

Delta39K™ ISR

™

CompactPCI Hot Swap

The CompactPCI Hot Swap specification allows the removal and insertion of cards into CompactPCI sockets without switching-off the bus. Delta39K CPLDs can be used as a CompactPCI host or target on these cards.

This feature is useful in telecommunication and networking applications as it allows implementation of high availability systems, where repairs and upgrades can be done without downtime.

Delta39K CPLDs are CompactPCI Hot Swap Ready per CompactPCI Hot Swap specification R2.0, with the following exception:

• The I/O cells do not provide bias voltage support. External resistors can be used to achieve this, per sectio n 3.1.3.1 of the CompactPCI Hot Swap specification R2.0. A simple board level sol ution is prov ided in the ap plication note titled

“Hot-Swapping Delta39K and Quantum38K CPLDs.”

Timing Model

One important feature of the Delta39K family is the simplicity of its timing. All combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the AC specs section) as long as data is routed through the same horizontal and vertical channels. Figure 10 illustrates the true timing model for the 200-MHz devices. For synchronous cloc king of macroc ells, a del ay is i ncurr ed from macrocell cloc k to macrocell clock o f separate Logic Blocks within the same cluster, as well as separate Logic Blocks within differe nt clusters. This is respectively shown as t t

in Figure 10. For combinatorial paths, any input to any

SCS2

SCS

and

output (from corner to corner on the device), incurs a worstcase delay in the 3 9K100 regardless of the amo unt of l ogic or which horizontal and vertical channels are u sed. This is the t shown in Figure 10. For synchronous systems, the input setup time to the outp ut macrocel l register and the clock to o utput time are shown as the parameters t the Figure 10. These measurements are for any output and synchronous clock, regardless of the logic placement.

The Delta39K features:

• no dedicated vs. I/O pin delays

• no penalty for using 0 – 16 product terms

• no added delay for steering product terms

• no added delay for sharing product terms

• no output bypass delays.

The simple timing model of the Delta39K family eliminates unexpected performance penalties.

Family, Package, and Density Migration in Delta39K CPLDs

The Delta39K CPLDs combine dense logic, embedded memory and configurable I/O standards. Further de sign flexibil ity is added by the easy m igra tio n options available be tw een d if f erent packages and densities of Delta39K CPLD offerings.

This migration flexibility makes changes or additions to designs simple even after PCB layout. It also provides the ability for experimental designs to be used on production PCBs. Please refer to the application note titled “Family,

Package, and Density Migration in Delta39K CPLDs.”

CPLD Fami

MCS

and t

MCCO

shown in

Document #: 38-03039 Rev. *H Page 13 of 86

Delta39K™ ISR

™

MCS

GCLK[3:0]

PIM

LB 7 LB 6 LB 5 LB 4

RAM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

LB 0 LB 1 LB 2 LB 3

Cluster Cluster

RAM

GCLK[3:0]

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

Channel

RAM

Channel

RAM

SCS

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

Channel

RAM

CPLD Fami

LB 0 LB 1 LB 2 LB 3

SRAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

8 Kb

PIM

LB 7 LB 6 LB 5 LB 4

8 Kb

SRAM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

Channel

RAM

SCS2

GCLK[3:0]

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

MCCO

PIM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

PIM

Figure 10. Timing Model for 39K100 Device

IEEE 1149.1-compliant JTAG Operation

The Delta39K family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR operations.

Four dedicated pins are reserved on each device for use by the Test Access Port (TAP).

Boundary Scan

The Delta39K family supports Bypass, Sample/Preload, Extest, Intest, Idcode and Usercode boundary scan instructions. The JTAG interface is shown in Figure 11.

In-System Reprogramming (ISR)

In-System Reprogram ming is the combi nation of the cap ability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins.

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

LB 0 LB 1 LB 2 LB 3

Cluster

RAM

PIM

LB 7 LB 6 LB 5 LB 4

Cluster

RAM

Channel

RAM

The Delta39K family implements ISR by providing a JTAG compliant int e rf ac e f or on -bo a rd p r ogr a mmi ng, r obu st ro ut i ng resources for pinout flexibility, and a simple timing model for consistent system performance.

Configuration

Each device of the Delta39K fa mily is available in a volatile an d a Self-Boot package . Cypres s’s CPLD boot EEPROM is used to store configuration data for the volatile solution and an embedded on-chip FLASH m emory device is used for th e SelfBoot solution.

For volatile Delta39K packages, programming is defined as the loading of a user’s design into the external CPLD boot EEPROM. For Self-Boot Delta39K packa ges, program ming is defined as the loading of a user’s design into the on-chip FLASH internal to the Delta39K package. Configuration is defined as the load ing of a user’s design int o the Delta39 K die.

Document #: 38-03039 Rev. *H Page 14 of 86

Delta39K™ ISR

™

Instruction Register

TDI

TMS

TCLK

Configuration can begin in two ways. It can be initiated by toggling the Reconfig pin from LOW to HI GH, or by issuing th e appropriate IEEE STD 1149.1 JTAG instruction to the Delta39K device via the JTAG interface. There are two IEEE STD 1149.1 JTAG instructions that initiate configu rati on of th e Delta39K. The Self Config instruction causes the Delta39K to (re)configure with data stored in the serial boot PROM or the embedded FLASH memory. The Load Config instruction causes the Delta39K to (re)configure according to data provided by other sources such as a PC, automatic test equipment (ATE), or an embedded micro-controller/pro cess or via the JTAG interface. For more informatio n on configuring Delta39K devices, refer to the application note titled “Config- uring Delta39K/Quantum38K” at http://www.cypress.com.

There are two configuration options available for issuing the IEEE STD 1 149. 1 JTAG instructions to the Delta39K. Th e first method is to use a PC with the C3ISR programming cable and software. With this method, the ISR pins of the Delta39K devices in th e sys tem are rou ted to a co nnecto r a t the edg e of the printed circuit board. The C3ISR programming cable is then connected between the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on the Delta39K devices in the system. The ISR software then automatically completes all of the necessary data manipulations req uir ed to accomplish configuration, reading, verifying, and other ISR functions. For more i nform at ion on the Cypress ISR i nterface, see the ISR Programming Kit data sheet (CY3900i).

The second configuration option for the Delta39K is to utilize the embedded contr oller or proc essor that alrea dy exists i n the system. The Delta3 9K ISR soft war e as si sts in th i s me tho d by converting the device HEX file into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be configured. The embedded controller then simply directs this ISR stream to the chain of

JTAG

TAP

CONTROLLER

Figure 11. JTAG Interface

Bypass Reg.

Boundary Scan

idcode

Usercode

ISR Prog.

Data Registers

Delta39K devices to complete the desired reconfiguration or diagnostic operat ions. Cont act y our loc al sa les o f fice for inf ormation on the availability of this option.

Programming

The on-chip FLASH device o f the Delta39K Se lf-Boot package is programmed by issuing the appropriate IEEE STD 1149.1 JTAG instruction to the internal FLASH memory via the JTAG interface. This can be done automatically using ISR/STAPL software. The configuration bits are sent from a PC through the JTAG port into the Delta39K via the C3ISR programming cable. The dat a is th en int ernally p assed from De lt a39K t o the on-chip FLASH. For more information on how to program the Delta39K through ISR/STAPL, please refer to the ISR/STAPL User Guide.

The external CPLD boot EEPROM used to store confi guration data for the Delt a39K vo latile pa ckage is progr ammed throug h Cypress’s CYDH2200E CPLD Boot PROM Programming Kit via a two-wire interface. For more information on how to program the CPLD boot EEPROM, please refer to the data sheet titled “CYDH2200E CPLD Boot PROM Programming Kit.” For more information o n the architecture and tim ing specification of the boot EEPROM, refer to the data sheet titled “512K/1Mb CPLD Boot EEPROM” or “2-Mbit CPLD Boot EEPROM.”

Third-Party Programmers

Cypress support is available on a wide variety of third-party programmers. All major programmers (including BP Micro, System General, Hi-Lo) support the Delta39K family.

CPLD Fami

Development Software Support

Warp

Warp is a state-of-the-art desig n environment for design ing with Cypress programmable logic. Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware Description Language (HDL) for design entry. Warp accepts VHDL or Veri log inpu t, synth esize s and opti mize s the entere d design, and outputs a configuration bitstream for the desired Delta39K device. For simulation, Warp provides a graphical waveform simulator as well as VHDL and Verilog Timing Models.

VHDL and Verilog are open, powerful, non-proprietary Hardware Description Languages (HDLs) that are standards for behavioral design entry and simulation. HDL allows designers to learn a single lan guage that is useful for all fac ets of the design process.

Third-Party Software

Cypress products are supported in a number of third-party design entry and simulation tools. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third party vendors.

Document #: 38-03039 Rev. *H Page 15 of 86

Delta39K™ ISR

™

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature

(39K200, 208 EQFP) .................................–45°C to +125°C

Storage Temperature

(all other densities and packages)..............–65°C to +150°C

Soldering Temperature.................................................220°C

Ambient Temperature with

Power Applied...............................................–40°C to +85°C

Operating Range

Range

Temperature

Commercial 0°C to +70°C 0°C to +85°C 3.3V 3.3V ± 0.3V 3.3V ± 0.3V or

Industrial –40°C to +85°C –40°C to +100°C 3.3V 3.3V ± 0.3V

Ambient

Junction

Temperature

Output

Condition V

2.5V 2.5V ± 0.2V

1.8V 1.8V ± 0.15V

1.5V 1.5V ± 0.1V

2.5V 2.5V ± 0.2V

1.8V 1.8V ± 0.15V

1.5V 1.5V ± 0.1V

DC Characteristics

Parameter Description

DRINT

DRIO

[7]

BHL

BHH

BHLO

BHHO

CC0

[8]

Data Retention VCC Voltage (config data may be lost below this)

Data Retention V (config data may be lost below this)

CCIO

Voltage

Input Leakage Current GND ≤ VI ≤ 3.6V –10 10 –10 10 –10 10 µA Output Leakage Current GND ≤ VO ≤

Output Short Circuit Current V

Input Bus Hold LOW Sust aining Cu rrent VCC = Min.

Input Bus Hold H IGH Sustaining Current VCC = Min.

Input Bus Hold LOW Overdrive Current VCC = Max. +250 +200 +150 µA Input Bus Hold H IGH O verdr ive Cu rrent VCC = Max. –250 –200 –150 µA Standby Current

Conditions

CCIO CCIO

OUT

= V

39K30 39K50 39K100 39K165 39K200

Junction Temperature...................................................135°C

to Ground Potential...................................–0.5V to 4.6V

to Ground Potential................................–0.5V to 4.6V

CCIO

DC Voltage Applied to Outputs

in High-Z state..................................................–0.5V to 4.5V

DC Input voltage...............................................–0.5V to 4.5V

DC Current into Outputs........................................± 20 mA

Static Discharge Voltage

(per JEDEC EIA./JESD22–A114A)............................>2001V

Latch-up Current.....................................................>200 mA

CCIO

2.5V ± 0.2V (39KV)

[5]

= 3.3V V

Test

CCIO

1.5 1.5 1.5 V

1.2 1.2 1.2 V

–10 10 –10 10 –10 10 µA

= Max.

–160 –160 –160 µA

= 0.5V

+40 +30 +25 µA

–40 –30 –25 µA

All bins

20 20 30 60 60

CPLD Fami

Same as

= 2.5V V

All bins

20 20 30 60 60

CCJTAG CCCNFGVCCPLLVCCPRG

Same as

CCIO

–125 bin

= 1.8V

3 3

5 10 10

–83 bin

12 12 20 40 40

[6]

3.3V ±

0.3V

UnitMin. Max. Min. Max. Min. Max.

µA

Note:

6. DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and V

7. Input Le akag e cu rren t is ± 10µA for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec for these pins in ±200µA

Package Pins

388-BGA B4, C2 484-FBGA B8, G9 676-FBGA F11, J11

8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters.

Delta39K100

= 0.5V has been chosen to avoid test

OUT

Document #: 38-03039 Rev. *H Page 16 of 86

= 1.5).

Delta39K™ ISR

™

CPLD Fami

Capacitance

Parameter Description Test Conditions Min. Max. Unit

I/O

CLK

PCI

DC Characteristics (I/ O)

I/O Standards

LVTTL –2 mA N/A 3.3 –2 mA 2.4 2 mA 0.4 2.0V V LVTTL –4 mA 3.3 –4 mA 2.4 4 mA 0.4 2.0V V LVTTL –6 mA 3.3 –6 mA 2.4 6 mA 0.4 2.0V V

LVTTL –8 mA 3.3 –8 mA 2.4 8 mA 0.4 2.0V V LVTTL –12 mA 3.3 –12 mA 2.4 12 mA 0.4 2.0V V LVTTL –16 mA 3.3 –16 mA 2.4 16 mA 0.4 2.0V V LVTTL –24 mA 3.3 –24 mA 2.4 24 mA 0.4 2.0V V

LVCMOS 3.3 –0.1 mA V

LVCMOS3 3.0 –0.1 mA V

LVCMOS2

LVCMOS18 1.8 –2 mA V

3.3V PCI 3.3 –0.5 mA 0.9V GTL+ 1.0

SSTL3 I 1.5 3.3 –8 mA V

SSTL3 II 1.5 3.3 –16 mA V

SSTL2 I 1.25 2.5 –7.6 mA V

SSTL2 II 1.25 2.5 –15.2 mA V

HSTL I 0.75 1.5 –8 mA V

HSTL II 0.75 1.5 –16 mA V

HSTL III 0.9 1.5 –8 mA V

HSTL IV 0.9 1.5 –8 mA V

Configuration Parameters

Parameter Description Min. Unit

RECONFIG

Power-up Sequence Requirements

• Upon power-up, al l the output s rema in three-st ated unt il all the V the part has completed configuration.

• The part will not start configuration until V V nominal voltage.

Notes:

9. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in

10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of V

11. See “Power-up Sequence Requirements” below for V

12. 25W resistor terminated to termination voltage of 1.5V.

pins have powered-up to the nom in al voltage and

, V

CCJTAG

a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf. to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.

• The source current limit per I/O bank per Vccio pin is 165 mA.

• The sink current limit per I/O bank per GND pin is 230 mA.

CCCNFG

Input/Output Capacitance V Clock Signal Capacitance V PCI-compliant

REF

(V)

[10]

CCIO

(V)

[9]

Capacitance V

(V) V

@ I

=VOH (min.) @ I

CCIO CCIO

2.5 –0.1 mA 2.1 0.1 mA 0.2 1.7V V –1.0 mA 2.0 1.0 mA 0.4 –2.0 mA 1.7 2.0 mA 0.7

CCIO

[11]

CCIO

CCIO CCIO CCIO

CCIO

Reconfig pin LOW time before it goes HIGH 200 ns

, V

CCPLL

and V

CCPRG

have reached

CCIO

= V

@ f = 1 MHz 25°C 10 pF

CCIO

@ f = 1 MHz 25°C 5 12 pF

CCIO

@ f = 1 MHz 25°C 8 pF

CCIO

(V) V

VOL

(max.) Min. Max. Min. Max.

– 0.2V 0.1 mA 0.2 2.0V V – 0.2V 0.1 mA 0.2 2.0V V

– 0.45V 2.0 mA 0.45 0.65V

CCIO

1.5 mA 0.1V

[12]

36 mA

CCIO

0.6 V

– 1.1V 8 mA 0.7 V – 0.9V 16 mA 0.5 V – 0.62V 7.6 mA 0.54 V – 0.43V 15.2 mA 0.35 V

– 0.4V 8 mA 0.4 V

– 0.4V 16 mA 0.4 V

– 0.4V 24 mA 0.4 V

– 0.4V 48 mA 0.4 V

•V

pins can be powered up in any order. This includes

VCC, V

CCIO

s on a bank should be tied to the same potential

CCIO

and powered up together.

s (even the unused banks) need to be pow ered up

CCIO

to at least 1.5V before configuration has compl eted.

, V

CCIO

•All V

CCIOVCCIO

0.5V

CCIOVCCIO

+ 0.2 V

REF

+ 0.2 V

REF

+ 0.2 V

REF

+ 0.18 V

REF

+ 0.18 V

REF

+ 0.1 V

REF

+ 0.1 V

REF

+ 0.1 V

REF

+ 0.1 V

REF

, V

CCJTAG

• Maximum ramp time for all V voltage in 100 ms.

requirement.

(V) V

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.8V

CCIO

+ 0.3 –0.3V 0.7V

CCIO

+ 0.3 –0.3V 0.35V + 0.5 –0.5V 0.3V

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

+ 0.3 –0.3V V

CCIO

, V

CCIO

, V

CCCNFG

s should be 0V to nominal

and GND pins being used. Please refer

CCPLL

and V

(V)

REF REF

REF REF REF

REF

CCPRG

CCIO

– 0.2 – 0.2

– 0.2 – 0.18 – 0.18

– 0.1

Document #: 38-03039 Rev. *H Page 17 of 86

Delta39K™ ISR

™

Switching Characteristics — Parameter Descriptions Over the Operating Range

Parameter Description

Combinatorial Mode Parameters

PRR

PRO

PRW

Synchronous Clocking Parameters

MCS

MCH

MCCO

IOS

IOH

IOCO

SCS

SCS2

ICS

OCS

CHZ

CLZ

MAX

MAX2

Product Term Clock

MCSPT

MCHPT

MCCOPT

SCS2PT

Channel Interconnect Parameters

CHSW

CL2CL

Miscellaneous Delays

CPLD

MCCD

IOD

IOIN

Note:

13. Add t

Delay from any pin input, through a ny cluster on the c hannel a ssociated with tha t pin inp ut, to an y pin ou tput on th e horizontal or vertical channel associated with that cluster

Global control to output enable Global control to output disable Asynchronous macrocell RESET o r PRESET recovery ti me from any pi n input on t he horizon tal or verti cal channel

associated with the cluster the macrocell is in Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated

with the cluster that the macrocell is in to any pin output on those same channels Asynchronous macroc ell RESET or PRESET min imum pulse width, from a ny pin inpu t to a macroc ell in the farthest

cluster on the horizontal or vertical channel the pin is associated with

Set-up time of any i nput pi n t o a mac rocell in an y cl ust er on t he cha nnel assoc iated with th at inp ut pin , relati ve to a global clock

Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock

Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in

Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock Clock to output of an I/O cell register to the output pin associated with that register Macrocell clock to macrocell clock through array logic within the same cluster Macrocell clock to macrocell clock through array logic in different clusters on the same channel I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the

macrocell is in Clock to output disable (high-impedance) Clock to output enable (low-impedance) Maximum frequency with internal feedback—within the same cluster Maximum frequenc y with int ernal feed back—w ithin dif ferent clusters at the op posite e nds of a horizont al or v ertical

channel

Set-up time for macrocell used as input register, from input to product term clock Hold time of macrocell used as an input register Product term clock to output delay from input pin Register to register delay through array logic in different clusters on the same channel using a product term clock

Adder for a signal to switch from a horizontal to vertical channel and vice-versa Cluster-to-cluster delay adder (through channels and channel PIM)

Delay from the input of a cluster PIM, th rough a macro cell in the c luster , back to a cluster PIM i nput. This p arameter can be added to the tPD and t signal path

parameters for each extra pass through the AND/OR array required by a given

SCS

Adder for carry chain logic per macrocell Delay from the input of the output buffer to the I/O pin Delay from the I/O pin to the input of the channel buffer

to signals making a horizontal to vertical channel switch or vice-versa.

CHSW

CPLD Fami

[13]

Document #: 38-03039 Rev. *H Page 18 of 86

Delta39K™ ISR

™

Switching Characteristics — Parameter Descriptions Over the Operating Range

Parameter Description

CKIN

IOREGPIN

PLL Parameters

MCCJ

DWSA

DWOSA

LOCK

INDUTY

PLLI

PLLO

PLLVCO

SAPLLI

MPLLI

JTAG Parameters

JCKH

JCKL

JCP

JSU

JCO

JXZ

JZX

Cluster Memory Timing Parameter Descriptions Ov er the Op erating Range

Parameter Description

Asynchronous Mode Parameters

CLMAA

CLMPWE

CLMSA

CLMHA

CLMSD

CLMHD

Synchronous Mode Parameters

CLMCYC1

CLMCYC2

CLMS

CLMH

CLMDV1

CLMDV2

CLMMACS1

CLMMACS2

MACCLMS1

Delay from the clock pin to the input of the clock driver Delay from the I/O pin to the input of the I/O register

Maximum cycle to cycle jitter time PLL zero phase delay with clock tree deskewed PLL zero phase delay without clock tree deskewed Lock time for the PLL Input duty cycle Input frequency of the PLL Output frequency of the PLL PLL VCO frequency of operation Percentage modulation allowed (spread awareness) on the PLL input clock Frequency of modulation allowed on PLL input clock. This specifies how fast the f

(1–P

SAPLLI

/100) and f

PLLI

* (1+ P

SAPLLI

/100)

TCLK HIGH time TCLK LOW time TCLK clock period JTAG port set-up time (TDI/TMS inputs) JTAG port hold time (TDI/TMS inputs) JTAG port clock to output time (TDO) JTAG port valid output to high impedance (TDO) JTAG port high impedance to valid output (TDO)

Cluster memory access time. Delay from address change to Read data out Write Enable pulse width Address set-up to the beginning of Write Enable with both signals from the same I/O block Address hold after the end of Write Enable with both signals from the same I/O block Data set-up to the end of Write Enable Data hold after the end of Write Enabl e

Clock cycle time for flow through Read and Write operations (from macro cell register through cluster memory back to a macrocell register in the same cluster)

Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the memory to cluster memory output register)

Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data Cluster memory input clock to macr oc el l clock in the same cluster Cluster memory output clock to macrocell clock in the same cluster Macrocell clock to cluster memory input clock in the same cluster

CPLD Fami

[13]

(continued)

sweeps between f

PLLI

Document #: 38-03039 Rev. *H Page 19 of 86

Delta39K™ ISR

™

Cluster Memory Timing Parameter Descriptions Ov er the Op erat ing Range (continued)

Parameter Description

MACCLMS2

Internal Parameters

CLMCLAA

Channel Memory Timing Parameter Descriptions Over the Operating Range

Parameter Description

Dual Port Asynchronous Mode Parameters

CHMAA

CHMPWE

CHMSA

CHMHA

CHMSD

CHMHD

CHMBA

Dual Port Synchronous Mode Parameters

CHMCYC1

CHMCYC2

CHMS

CHMH

CHMDV1

CHMDV2

CHMBDV

CHMMACS1

CHMMACS2

MACCHMS1

MACCHMS2

Synchronous FIFO Data Parameters

CHMCLK

CHMFS

CHMFH

CHMFRDV

CHMMACS

MACCHMS

Synchronous FIFO Flag Parameters

CHMFO

CHMMACF

CHMFRS

CHMFRSR

CHMFRSF

CHMSKEW1

CHMSKEW2

CHMSKEW3

Macrocell clock to cluster memory output clock in the same cluster

Asynchronous cluster memory access time from input of cluster memory to output of cluster memory

Channel memory access time. Delay from address change to Read data out Write enable pulse width Address set-up to the beginning of Write enable with both signals from the same I/O block Address hold after the end of Write enable with both signals from the same I/O block Data set-up to the end of Write enable Data hold after the end of Write enable Channel memory asynchronous dual port address match (busy access time)

Clock cycle time for flow through Read and Write operations (from macrocell register through channel memory back to a macrocell register in the same cluster)

Clock cycle time for pipeline d Read and Write operatio ns (from channel memo ry input register through the memory to channel memory output register)

Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data. Channel memory synchronous dual-port address match (busy, clock to data valid) Channel memory input clock to macrocell clock in the same cluster Channel memory output clock to macrocell clock in the same cluster Macrocell clock to channel memory input clock in the same cluster Macrocell clock to channel memory output clock in the same cluster

Read and Write minimum clock cycle time Data, Read enable, and Write enable set-up time relative to pin inputs Data, Read enable, and Write enable hold time relative to pin inputs Data access time to output pins from rising edge of Read clock (Read clock to data valid) Channel memory FIFO Read clock to macrocell clock for Read data Macrocell clock to channel memory FIFO Write clock for Write data

Read or Write clock to respective flag output at output pins Read or Write clock to macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recove r y Time Master Reset to Flag and Data Output Time Read/Write Clock Skew Time for Full Flag Read/Write Clock Skew Time for Empty Flag Read/Write Clock Skew Time for Boundary Flags

CPLD Fami

Document #: 38-03039 Rev. *H Page 20 of 86

Delta39K™ ISR

™

Channel Memory Timing Parameter Descriptions Over the Operating Range (continued)

Parameter Description

Internal Parameters

CHMCHAA

Switching Characteristics — Parameter Values Over the Operating Range

Parameter

Combinatorial Mode Parameters

PRR

PRO

PRW

Synchronous Clocking Parameters

MCS

MCH

MCCO

IOS

IOH

IOCO

SCS

SCS2

ICS

OCS

CHZ

CLZ

MAX

MAX2

Product Term Clocking Parameters

MCSPT

MCHPT

MCCOPT

SCS2PT

Channel Interconnect Parameters

CHSW

CL2CL

Miscellaneous Parameters

CPLD

MCCD

PLL Parameters

MCCJ

DWSA

DWOSA

LOCK

Asynchronous channel memory access time from input of channel memory to output of channel memory

233 200 181

125 83

7.2 7.5 8.5 10 15 ns

4.5 5.0 5.6 9.0 10 ns

4.5 5.0 5.3 9.0 10 ns

6.0 6.0 6.0 8.0 10 ns

9.5 10 10.5 13 15 ns

3.3 3.6 4.0 6.0 7.0 ns

2.7 3.0 3.5 5.0 6.7 ns 0000 0 ns

5.8 6.0 7.0 10 12 ns

1.0 1.0 1.2 2.0 2.5 ns

0.9 1.0 1.2 2.0 2.5 ns

3.8 4.0 4.5 7.0 8.0 ns

3.4 3.5 3.6 6.4 9.6 ns

4.3 4.5 5.5 8.0 12 ns

4.5 5.0 5.5 8.0 12 ns

3.5 3.5 3.8 6.0 7.0 ns

1.5 1.5 1.5 1.5 1.5 ns

294 286 278 156 104 MHz 233 222 181 125 83 MHz

2.7 3.0 3.3 5.0 6.0 ns

0.9 1.0 1.4 2.0 2.5 ns

7.5 8.0 8.8 11.0 15.0 ns

6.0 6.5 7.2 10.0 15.0 ns

0.9 1.0 1.2 1.7 2.0 ns

1.8 2.0 2.3 2.8 3.0 ns

2.8 3.0 3.3 4.0 5.0 ns

0.22 0.25 0.28 0.35 0.38 ns

–150 150 –150 150 –150 150 –180 180 –200 200 ps

–1.35 –0.85 –1.35 –0.85 –1.35 –0.85 –2.0 –1.5 –2.9 –2.4 ns

–150 150 –150 150 –150 150 –180 180 –200 200 ps

250 250 250 250 250 ms

CPLD Fami

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Document #: 38-03039 Rev. *H Page 21 of 86

Delta39K™ ISR

™

Switching Characteristics — Parameter Values Over the Operating Range (continued)

125 83

Parameter

INDUTY

[14]

PLLO

[14]

PLLI

PLLVCO

SAPLLI

MPLLI

JTAG Parameters

JCKH

JCKL

JCP

JSU

JCO

JXZ

JZX

233 200 181

40 60 40 60 40 60 40 60 40 60 %

6.2 266 6.2 266 6.2 266 6.2 200 6.2 200 MHz

12.5 133 12.5 133 12.5 133 12.5 100 12.5 100 MHz 100 266 100 266 100 266 100 266 100 266 MHz

–0.3 +0.3 –0.3 +0.3 –0.3 +0.3 –0.3 +0.3 –0.3 +0.3 %

50 50 50 50 50 KHz

25 25 25 25 25 ns 25 25 25 25 25 ns 50 50 50 50 50 ns 10 10 10 10 10 ns 10 10 10 10 10 ns

20 20 20 20 20 ns 20 20 20 20 20 ns 20 20 20 20 20 ns

CPLD Fami

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Input and Output Standard Timing Delay Adjustments

All the timing specifications in this data sheet are specified based on LVCMOS compliant inputs and outputs (fast slew

[15]

rates). are configured to operate at other standards.

Notes:

14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operat ion.

15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.

16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.

Apply following adjus tments if the input s and output s

Output Delay Adjustments

Slow Slew Rate

Input Delay AdjustmentsFast Slew Rate

CKIN

I/O Standard

IOD

(additional delay to fast slew rate)

IODSLOW

EASLOWtERSLOWtIOIN

LVTTL – 2 mA 2.75 0 0 2.6 2.0 2.0 0 0 0 LVTTL – 4 mA 1.8 0 0 2.5 2.0 2.0 0 0 0 LVTTL – 6 mA 1.8 0 0 2.5 2.0 2.0 0 0 0

LVTTL – 8 mA 1.2 0 0 2.4 2.0 2.0 0 0 0 LVTTL – 12 mA 0.6 0 0 2.3 2.0 2.0 0 0 0 LVTTL – 16 mA 0.16 0 0 2.0 2.0 2.0 0 0 0 LVTTL – 24 mA 0 0 0 1.6 2.0 2.0 0 0 0

LVCMOS 0 0 0 2.0 2.0 2.0 0 0 0 LVCMOS3 0.14 0.05 0 2.0 2 .0 2.0 0.1 0.1 0.2 LVCMOS2 0.41 0.1 0 2.0 2.0 2.0 0.2 0.2 0.4

LVCMOS18 1.6 0.7 0.1 2.1 2.0 2.0 0.5 0.4 0.3

3.3V PCI –0.14 0 0 2.0 2.0 2.0 0 0 0 GTL+ 0.02

[16]

0.6

[16]

0.9

[16]

2.0 2.0 2.0 0.5 0.4 0.2

SSTL3 I –0.15 0.3 0.1 2.0 2.0 2.0 0.5 0.3 0.3

SSTL3 II –0.4 0.2 0 2.0 2.0 2.0 0.5 0.3 0.3

IOREGPIN

Document #: 38-03039 Rev. *H Page 22 of 86

Delta39K™ ISR

™

Output Delay Adjustments

(additional delay to fast slew rate)

I/O Standard

IOD

IODSLOW

SSTL2 I –0.02 0.4 0 2.0 2.0 2.0 0.9 0.5 0.6

SSTL2 II –0.22 0.2 0 2.0 2.0 2.0 0.9 0.5 0.6

HSTL I 0.94 0.9 0.5 2.0 2.0 2.0 0.5 0.5 0.3

HSTL II 0.79 0.8 0.5 2.0 2.0 2.0 0.5 0.5 0.3

HSTL III 0.77 0.5 0.1 2.0 2.0 2.0 0.5 0.5 0.3

HSTL IV 0.44 0.6 0 2.0 2.0 2.0 0.5 0.5 0.3

Cluster Memory Timing Parameter Values Over the Operating Range

233 200 181 125

Parameter

Asynchronous Mode Parameters

CLMAA

CLMPWE

CLMSA

CLMHA

CLMSD

CLMHD

5.5 6 6.5 10 12 ns

1.8 2.0 2.2 3.2 4.0 ns

0.9 1.0 1.1 1.8 2.0 ns

5.5 6.0 6.5 10 12 ns

0.4 0.5 0.6 0.9 1.0 ns

10.2 11 12 17 20 ns

Synchronous Mode Parameters

CLMCYC1

CLMCYC2

CLMS

CLMH

CLMDV1

CLMDV2

CLMMACS1

CLMMACS2

MACCLMS1

MACCLMS2

9.5 10 10.5 15 20 ns

5.0 5.0 5.5 8.0 10.0 ns

2.8 3.0 3.8 4.0 5.0 ns 0000 0 ns

10 11 12 17 20 ns

7.0 7.5 8.0 10 15 ns

7.7 8.0 8.5 12 15 ns

4.5 5.0 5.5 8.0 10 ns

3.6 4.0 4.4 6.6 8.0 ns

6.0 6.5 7.0 10 12 ns

Internal Parameters

CLMCLAA

666.510 12 ns

Channel Memory Timing Parameter Values Over the Operating Range

Slow Slew Rate

EASLOWtERSLOWtIOIN

CPLD Fami

Input Delay AdjustmentsFast Slew Rate

CKIN

IOREGPIN

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

233 200 181 125

Parameter

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Dual-Port Asynchronous Mode Parameters

CHMAA

CHMPWE

CHMSA

CHMHA

CHMSD

CHMHD

CHMBA

5.5 6.0 6.5 10 12 ns

1.8 2.0 2.2 3.2 4.0 ns

0.9 1.0 1.1 1.8 2.0 ns

5.5 6.0 6.5 10 12 ns

0.4 0.5 0.6 0.9 1.0 ns

Document #: 38-03039 Rev. *H Page 23 of 86

10 1 1 12 17 20 ns

8.5 9.0 10.0 14.0 16.0 ns

Delta39K™ ISR

™

Channel Memory Timing Parameter Values Over the Operating Range (continued)

Dual-Port Synchronous Mode Parameters

CHMCYC1

CHMCYC2

CHMS

CHMH

CHMDV1

CHMDV2

CHMBDV

CHMMACS1

CHMMACS2

MACCHMS1

MACCHMS2

Synchronous FIFO Data Parameters

CHMCLK

CHMFS

CHMFH

CHMFRDV

CHMMACS

MACCHMS

Synchronous FIFO Flag Parameters

CHMFO

CHMMACF

CHMFRS

CHMFRSR

CHMFRSF

CHMSKEW1

CHMSKEW2

CHMSKEW3

Internal Parameters

CHMCHAA

Switching Waveforms

9.5 10 10 15 20 ns

5.0 5.3 5.4 7.4 10.6 ns

3.0 3.3 3.9 5.0 6.0 ns 0000 0 ns

10 1 1 12 17 20 ns

7.0 7.5 8.0 10 15 ns

8.5 9.0 10.0 14.0 16.0 ns

4.8 5.0 5.5 8.0 10 ns

4.6 5.0 5.4 7.6 9.0 ns

7.3 7.3 7.7 10.0 13.0 ns

4.8 5.0 5.4 7.4 10.6 ns

3.7 4.0 4.3 6.0 7.0 ns 0000 0 ns

6.5 7.0 7.5 10.0 13.0

4.6 5.0 5.4 7.4 10.6 ns

4.7 5.0 5.4 7.4 10.6 ns

10.5 11 11.5 15 20 ns

8.599.513 17 ns

4.5 5.0 5.5 8.0 10 ns

3.6 4.0 4.4 6.6 8.0 ns

9.5 10.0 11.0 15.0 18.0 ns

1.8 2.0 2.2 3.2 4.0 ns

4.6 5.0 5.4 7.4 10.6 ns

6.5 7.0 7.5 10.0 13.0 ns

CPLD Fami

Combinatorial Output

INPUT

COMBINATORIAL

Document #: 38-03039 Rev. *H Page 24 of 86

OUTPUT

Delta39K™ ISR

™

Switching Waveforms (continued)

Registered Output with Synchronous Clocking (Macrocell)

INPUT

SYNCHRONOUS

CLOCK

REGISTERED

OUTPUT

Registered Input in I/O Cell

DATA

INPUT

MCS

IOS

MCH

MCCO

IOH

CPLD Fami

INPUT REGISTER

CLOCK

REGISTERED

OUTPUT

Clock to Clock

INPUT REGISTER

CLOCK

MACROCELL

PT Clock to PT Clock

DATA

INPUT

PT CLOCK

ICS

MCSPT

IOCO

SCS

SCS2PT

Document #: 38-03039 Rev. *H Page 25 of 86

Delta39K™ ISR

™

Switching Waveforms (continued)

Asynchronous Reset/Preset

RESET/PRESET

INPUT

REGISTERED

OUTPUT

CLOCK

Output Enable/Disable

GLOBAL CONTROL

INPUT

PRO

PRW

CPLD Fami

PRR

OUTPUTS

Document #: 38-03039 Rev. *H Page 26 of 86

+ 60 hidden pages

CYPRESS 39K30, 39K50, 39K100, 39K165, 39K200 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual