Cypress 37000 CPLD User Manual
Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
• High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI-compatible
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
— Product term sharing among local macrocells
• Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
• Consistent package/pinout offering across all densities
— Simplifies design migration
— Same pinout for 3.3V and 5.0V devices
• Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
BGA, and Fine-Pitch BGA packages
— Lead (Pb)-free packages available
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V
[1]
General Description
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both
design and manufacturing flows, thereby reducing costs. The
ISR feature provides the ability to reconfigure the devices
without having design changes cause pinout or timing
changes. The Cypress ISR function is implemented through a
JTAG-compliant serial interface. Data is shifted in and out
through the TDI and TDO pins, respectively. Because of the
superior routability and simple timing model of the Ultra37000
devices, ISR allows users to change existing logic designs
while simultaneously fixing pinout assignments and
maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. V
capability of interfacing to either a 5V or 3.3V bus. By
connecting the V
on the outputs. If V
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
pins to 5V the user insures 5V TTL levels
CCO
is connected to 3.3V the output levels
CCO
These devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all V
pins, reducing the device’s power consumption. These
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
, PCI V
CC
IH
= 2V.
connections provide the
CCO
CCO
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03007 Rev. *E Revised March 7, 2004
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Ultra37000 CPLD Family
Selection Guide
5.0V Selection Guide
General Information
Device Macrocells Dedicated Inputs I/O Pins Speed (t
CY37032 32 5 32 6 200
CY37064 64 5 32/64 6 200
CY37128 128 5 64/128 6.5 167
CY37192 192 5 120 7.5 154
CY37256 256 5 128/160/192 7.5 154
CY37384 384 5 160/192 10 118
CY37512 512 5 160/192/264 10 118
Speed Bins
Device 200 167 154 143 125 100 83 66
CY37032 X X X
CY37064 X X X
CY37128 X X X
CY37192 X X X
CY37256 X X X
CY37384 X X
CY37512 X X X
)Speed (f
PD
MAX
)
Device-Package Offering and I/O Count
Device
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
160-
Lead
CQFP
208-
Lead
PQFP
208-
Lead
CQFP
292-
Lead
PBGA
CY37032 37 37
CY37064 37 37 37 69 69
CY37128 69 69 69 133
CY37192 125
CY37256 133 133 165 197
CY37384 165 197
CY37512 165 165 197 269
3.3V Selection Guide
General Information
Device Macrocells Dedicated Inputs I/O Pins Speed (t
)Speed (f
PD
CY37032V 32 5 32 8.5 143
CY37064V 64 5 32/64 8.5 143
CY37128V 128 5 64/80/128 10 125
CY37192V 192 5 120 12 100
CY37256V 256 5 128/160/192 12 100
CY37384V 384 5 160/192 15 83
CY37512V 512 5 160/192/264 15 83
388-
Lead
PBGA
MAX
)
Document #: 38-03007 Rev. *E Page 2 of 64
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Ultra37000 CPLD Family
Speed Bins
Device 200 167 154 143 125 100 83 66
CY37032V X X
CY37064V X X
CY37128V X X
CY37192V XX
CY37256V XX
CY37384V XX
CY37512V XX
Device-Package Offering and I/O Count
Device
44-
44-
Lead
TQFP
48-
Lead
CLCC
84-
Lead
FBGA
100-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
FBGA
160-
Lead
TQFP
208-
Lead
CQFP
Lead
208-
PQFP
292-
Lead
CQFP
Lead
256-
PBGA
388-
Lead
Lead
FBGA
PBGA
CY37032V 37 37
CY37064V 37 37 37 69 69
CY37128V 69 69 85 133
CY37192V 125
CY37256V 133 133 165 197 197
CY37384V 165 197
CY37512V 165 165 197 269 269
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The PIM consists of a completely global routing matrix for
signals from I/O pins and feedbacks from the logic blocks. The
PIM provides extremely robust interconnection to avoid fitting
and density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic blocks. Each logic block receives 36
inputs from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also
improves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing
specifications for each device. There is no additional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing parameters on the Ultra37000 devices. The worst-case PIM delays
are incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary. Warp
automatically route designs for the Ultra37000 family in a
matter of minutes. Finally, the rich routing resources of the
Ultra37000 family accommodate last minute logic changes
while maintaining fixed pin assignments.
®
and third-party development packages
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used. Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product
term array. This array accepts 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 87 product
terms in the array can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Four of the remaining
seven product terms in the logic block are output enable (OE)
product terms. Each of the OE product terms controls up to
eight of the 16 macrocells and is selectable on an individual
macrocell basis. In other words, each I/O cell can select
between one of two OE product terms to control the output
buffer. The first two of these four OE product terms are
available to the upper half of the I/O macrocells in a logic block.
The other two OE product terms are available to the lower half
of the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final product term is the product term clock. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
400-
Lead
FBGA
Document #: 38-03007 Rev. *E Page 3 of 64
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FROM
PIM
72 x 87
PRODUCT TERM
ARRAY
Ultra37000 CPLD Family
2
3
0−16
PRODUCT
TERMS
7
8036
PRODUCT
TERM
ALLOCATOR
0−16
PRODUCT
TERMS
MACRO-
CELL
0
MACRO-
CELL
1
I/O
CELL
0
to cells
2
2, 4, 6 8, 10, 12
TO
PIM
16
8
Figure 1. Logic Block with 50% Buried Macrocells
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block
by logic block basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator
provides two important capabilities without affecting performance: product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Ultra37000 devices,
product terms are steered on an individual basis. Any number
between 0 and 16 product terms can be steered to any
macrocell. Note that 0 product terms is useful in cases where
a particular macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator
allows sharing across groups of four output macrocells in a
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
MACRO-
CELL
14
MACRO-
CELL
15
I/O
CELL
14
variable fashion. The software automatically takes advantage
of this capability—the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
worst-case steering and sharing configurations have been
incorporated in the timing specifications for the Ultra37000
devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Buried Macrocell
Figure 2 displays the architecture of buried macrocells. The
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or asynchronously
reset at the logic block level with the separate set and reset
product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset
based on an AND expression or an OR expression.
Clocking of the register is very flexible. Four global
synchronous clocks and a product term clock are available to
clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as
well as rising edges (see the Clocking section). Clock polarity
is chosen at the logic block level.
Document #: 38-03007 Rev. *E Page 4 of 64
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Ultra37000 CPLD Family
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many applications.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
I/O MACROCELL
FROM PTM
0−16
PRODUCT
TERMS
0
1
2
3
4
C24
C0
C1
0
1
C25
D/T/L
O
1
0
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface applications. Bus-hold additionally allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connections to V
note Understanding Bus-Hold—A Feature of Cypress CPLDs.
or GND. For more information, see the application
CC
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance.
FAST
SLEW
SLOW
0
1
DECODE
C2 C3
O
P
Q
R
O
0
1
C4
“0”
“1”
C26
0
1
2
3
C6 C5
I/O CELL
O
BURIED MACROCELL
FROM PTM
0−16
PRODUCT
TERMS
ASYNCHRONOUS
BLOCK RESET
ASYNCHRONOUS
BLOCK PRESET
0
1
2
3
4
C24
C0
C1
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
0
1
C25
0
O
1
Q
1
0
C7
D/T/L Q
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
0
1
DECODE
C2 C3
O
OE0
OE1
P
R
Figure 2. I/O and Buried Macrocells
Document #: 38-03007 Rev. *E Page 5 of 64
[+] Feedback
FROM CLOCK
POLARITY MUXES
0
1
2
3
C10
INPUT PIN
O
C11
D
Q
D
Q
LE
Figure 3. Input Macrocell
Ultra37000 CPLD Family
0
1
O
D
Q
2
3
C12 C13
TO PIM
INPUT/CLOCK PIN
FROM CLOCK
POLARITY INPUT
CLOCK PINS
0
1
O
2
3
C8
C9
D
Q
D
Q
LE
D
Figure 4. Input/Clock Macrocell
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are designated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
0
O
1
C12
0
1
O
2
Q
3
C10C11
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO PIM
0
O
1
C13, C14, C15 OR C16
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used.
Figure 5 illustrates the true timing model for the 167-MHz
devices in high speed mode. For combinatorial paths, any
input to any output incurs a 6.5-ns worst-case delay regardless
of the amount of logic used. For synchronous systems, the
input set-up time to the output macrocells for any input is 3.5
ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless
of the logic used.
The Ultra37000 features:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
TO CLOCK MUX
IN EACH
LOGIC BLOCK
Document #: 38-03007 Rev. *E Page 6 of 64
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Ultra37000 CPLD Family
COMBINATORIAL SIGNAL
t
= 6.5 ns
INPUT
tS = 3.5 ns
INPUT
CLOCK
PD
REGISTERED SIGNAL
D,T,L O
t
CO
OUTPUT
= 4.5 ns
OUTPUT
Figure 5. Timing Model for CY37128
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable
timing model ensures compliance with the PCI AC specifications independent of the design.
IEEE 1149.1-compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,
Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in Figure 6.
Instruction Register
TDI
TMS
TCK
JTAG
TAP
CONTROLLER
Bypass Reg.
Boundary Scan
idcode
Usercode
ISR Prog.
Data Registers
Figure 6. JTAG Interface
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
TDO
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Development Software Support
Warp
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry, Warp provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a
graphical finite state machine editor. It provides optimized
synthesis and fitting by replacing basic circuits with ones
pre-optimized for the target device, by implementing logic in
unused memory and by perfect communication between fitting
and synthesis. To facilitate design and debugging, Warp
provides graphical timing simulation and analysis.
Warp Professional
Warp Professional contains several additional features. It
provides an extra method of design entry with its graphical
block diagram editor. It allows up to 5 ms timing simulation
instead of only 2 ms. It allows comparison of waveforms before
and after design changes.
Warp Enterprise
Warp Enterprise provides even more features. It provides
unlimited timing simulation and source-level behavioral
simulation as well as a debugger. It has the ability to generate
graphical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features
are not available in the UNIX version. For further information
see the Warp for PC, Warp for UNIX, Warp Professional and
Warp Enterprise data sheets on Cypress’s web site
(www.cypress.com).
Third-Party Software
Although Warp is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
Ultra37000 family of devices. Refer to the third-party software
data sheet or contact your local sales office for a list of
currently supported third-party vendors.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000
UltraISR programming cable and software. With this method,
the ISR pins of the Ultra37000 devices are routed to a
connector at the edge of the printed circuit board. The 37000
UltraISR programming cable is then connected between the
parallel port of the PC and this connector. A simple configuration file instructs the ISR software of the programming
operations to be performed on each of the Ultra37000 devices
in the system. The ISR software then automatically completes
all of the necessary data manipulations required to accomplish
the programming, reading, verifying, and other ISR functions.
For more information on the Cypress ISR Interface, see the
ISR Programming Kit data sheet (CY3700i).
The second method for programming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through
a file created by the ISR software. Check the Cypress website
for the latest ISR software download information.
™
™
Document #: 38-03007 Rev. *E Page 7 of 64
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Ultra37000 CPLD Family
The third programming option for Ultra37000 devices is to
utilize the embedded controller or processor that already
exists in the system. The Ultra37000 ISR software assists in
this method by converting the device JEDEC maps into the
ISR serial stream that contains the ISR instruction information
and the addresses and data of locations to be programmed.
The embedded controller then simply directs this ISR stream
to the chain of Ultra37000 devices to complete the desired
reconfiguring or diagnostic operations. Contact your local
sales office for information on availability of this option.
The fourth method for programming Ultra37000 devices is to
use the same programmer that is currently being used to
program F
For all pinout, electrical, and timing requirements, refer to
device data sheets. For ISR cable and software specifications,
refer to the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available on
a wide variety of third-party programmers. All major third-party
programmers (including BP Micro, Data I/O, and SMS) support
the Ultra37000 family.
LASH370i devices.
Document #: 38-03007 Rev. *E Page 8 of 64
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Logic Block Diagrams
Ultra37000 CPLD Family
CY37032/CY37032V
I/O
CY37064/CY37064V
-I/O
I/O
0
15
I/O16-I/O
31
−I/O
0
16 I/Os
16 I/Os
16 I/Os
15
BLOCK
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
4
LOGIC
A
Clock/
Input
Input
1
36
16
16
PIM
4
36
LOGIC
BLOCK
16
B
16
TDI
TCK
TMS
4
16 I/Os
JTAG Tap
Controller
JTAG
I/O16−I/O
TDO
EN
31
Clock/
Input
Input
1
4
4
36
16
36
16
LOGIC
BLOCK
16 I/Os
I/O48-I/O
63
D
36
16
PIM
36
16
LOGIC
BLOCK
16 I/Os
I/O32-I/O
47
C
TDI
TCK
TMS
JTAG Tap
Controller
TDO
32
32
Document #: 38-03007 Rev. *E Page 9 of 64
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Logic Block Diagrams (continued)
Ultra37000 CPLD Family
CY37128/CY37128V
I/O
–I/O
0
I/O16–I/O
I/O32–I/O
I/O28–I/O
CY37192/CY37192V
15
31
47
63
16 I/Os
16 I/Os
16 I/Os
16 I/Os
CLOCK
INPUTS
INPUTS
41
INPUT
MACROCELL
INPUT/CLOCK
MACROCELLS
4 4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
64
36
16
36
16
PIM
36
16
36
16
36 36
Input
1
16
36
16
Clock/
Input
16
36
16
LOGIC
BLOCK
LOGIC
BLOCK
LOGIC
BLOCK
LOGIC
BLOCK
64
4
TDI
TCK
TMS
JTAG Tap
Controller
JTAG
EN
TDO
16 I/Os
I/O
–I/O
112
H
16 I/Os
G
I/O96–I/O
127
111
16 I/Os
F
I/O80–I/O
95
16 I/Os
E
I/O64–I/O
79
TDI
TCK
TMS
JTAG Tap
Controller
–I/O
I/O
0
I/O10–I/O
I/O20–I/O
I/O30–I/O
I/O40–I/O
I/O50–I/O
10 I/Os
9
10 I/Os
19
10 I/Os
29
10 I/Os
39
10 I/Os
49
10 I/Os
59
TDO
LOGIC
BLOCK
L
LOGIC
BLOCK
K
LOGIC
BLOCK
J
LOGIC
BLOCK
I
LOGIC
BLOCK
H
LOGIC
BLOCK
G
6060
4
10 I/Os
I/O
–I/O
110
119
10 I/Os
I/O
–I/O
100
109
10 I/Os
I/O90–I/O
99
10 I/Os
I/O80–I/O
89
10 I/Os
I/O70–I/O
79
10 I/Os
I/O60–I/O
69
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
PIM
36
16
36
16
36
16
36
16
36
16
36
16
Document #: 38-03007 Rev. *E Page 10 of 64
[+] Feedback
Logic Block Diagrams (continued)
CY37256/CY37256V
Input
1
Clock/
Input
Ultra37000 CPLD Family
4
TDI
TCK
TMS
I/O
I/O12−I/O
I/O24−I/O
I/O36−I/O
I/O48−I/O
I/O60−I/O
I/O72−I/O
I/O84−I/O
JTAG Tap
Controller
0
−I/O
12 I/Os
11
12 I/Os
23
12 I/Os
35
12 I/Os
47
12 I/Os
59
12 I/Os
71
12 I/Os
83
12 I/Os
95
TDO
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
LOGIC
BLOCK
G
LOGIC
BLOCK
H
36
16
36
16
36
16
36
16
36
PIM
16
36
16
36
16
36
16
96
36
LOGIC
BLOCK
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
P
LOGIC
BLOCK
O
LOGIC
BLOCK
N
LOGIC
BLOCK
M
LOGIC
BLOCK
L
LOGIC
BLOCK
K
LOGIC
BLOCK
J
LOGIC
BLOCK
I
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
−I/O
180
I/O
−I/O
168
I/O
−I/O
156
I/O
−I/O
144
I/O
−I/O
132
I/O
−I/O
120
I/O
−I/O
108
I/O96−I/O
191
179
167
155
143
131
119
107
96
4
Document #: 38-03007 Rev. *E Page 11 of 64
[+] Feedback
Logic Block Diagrams (continued)
Ultra37000 CPLD Family
CY37384/CY37384V
I/O
0
I/O12−I/O
I/O24−I/O
I/O
36
I/O48−I/O
I/O60−I/O
I/O72−I/O
I/O
84
−I/O
−I/O
−I/O
12 I/Os
11
12 I/Os
23
12 I/Os
35
12 I/Os
47
12 I/Os
59
12 I/Os
71
12 I/Os
83
12 I/Os
95
4
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
LOGIC
BLOCK
AE
LOGIC
BLOCK
AF
LOGIC
BLOCK
AG
LOGIC
BLOCK
AH
LOGIC
BLOCK
AI
LOGIC
BLOCK
AJ
LOGIC
BLOCK
AK
LOGIC
BLOCK
AL
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
Input
1
PIM
Clock/
Input
4
4
36
LOGIC
BLOCK
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
BL
LOGIC
BLOCK
BK
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BI
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
LOGIC
BLOCK
BD
LOGIC
BLOCK
BC
LOGIC
BLOCK
BB
LOGIC
BLOCK
BA
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
168
156
144
132
120
108
96
96
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
191
179
167
155
143
131
119
107
TDI
TCK
TMS
JTAG Tap
Controller
TDO
96
96
Document #: 38-03007 Rev. *E Page 12 of 64
[+] Feedback
Logic Block Diagrams (continued)
Ultra37000 CPLD Family
CY37512/CY37512V
I/O
I/O12−I/O
I/O24−I/O
I/O36−I/O
I/O48−I/O
I/O60−I/O
I/O72−I/O
I/O84−I/O
I/O
I/O
108
I/O
120
Input
Clock/
Input
1
4
12 I/Os
−I/O
0
11
12 I/Os
23
12 I/Os
35
12 I/Os
47
12 I/Os
59
12 I/Os
71
12 I/Os
83
12 I/Os
95
12 I/Os
−I/O
96
107
12 I/Os
−I/O
119
12 I/Os
−I/O
131
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
LOGIC
BLOCK
AE
LOGIC
BLOCK
AF
LOGIC
BLOCK
AG
LOGIC
BLOCK
AH
LOGIC
BLOCK
AI
LOGIC
BLOCK
AJ
LOGIC
BLOCK
AK
LOGIC
BLOCK
AL
LOGIC
BLOCK
AM
LOGIC
BLOCK
AN
LOGIC
BLOCK
AO
LOGIC
BLOCK
AP
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
PIM
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
4
4
36
LOGIC
BLOCK
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
BP
LOGIC
BLOCK
BO
LOGIC
BLOCK
BN
LOGIC
BLOCK
BM
LOGIC
BLOCK
BL
LOGIC
BLOCK
BK
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BI
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
LOGIC
BLOCK
BD
LOGIC
BLOCK
BC
LOGIC
BLOCK
BB
LOGIC
BLOCK
BA
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
252
240
228
216
204
192
180
168
156
144
132
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
263
251
239
227
215
203
191
179
167
155
143
132132
TDI
TCK
TMS
JTAG Tap
Controller
TDO
Document #: 38-03007 Rev. *E Page 13 of 64
[+] Feedback
Ultra37000 CPLD Family
5.0V Device Characteristics
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Operating Range
Range Ambient Temperature
[2]
[2]
Junction Temperature Output Condition V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage............................................. 4.5 to 5.5V
Current into Outputs .................................................... 16 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
CC
V
CCO
Commercial 0°C to +70°C 0°C to +90°C 5V 5V ± 0.25V 5V ± 0.25V
3.3V 5V ± 0.25V 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
[3]
Military
–55°C to +125°C –55°C to +130°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
5.0V Device Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Ty p. Max. Unit
V
OH
Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)
IOH = –2.0 mA (Mil)
V
OHZ
Output HIGH Voltage with
Output Disabled
[5]
VCC = Max. IOH = 0 µA (Com’l)
IOH = 0 µA (Ind/Mil)
IOH = –100 µA (Com’l)
IOH = –150 µA (Ind/Mil)
V
OL
Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)
IOL = 12 mA (Mil)
V
IH
V
IL
I
IX
I
OZ
I
OS
I
BHL
I
BHH
I
BHLO
I
BHHO
Notes:
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”
3. T
A
4. I
OH
5. Tested initially and after any design or process changes that may affect these parameters.
6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
problems caused by tester ground degradation.
Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs
Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs
Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10 µA
Output Leakage Current VO = GND or VCC, Output Disabled, Bus-Hold Disabled –50 50 µA
Output Short Circuit Current
Input Bus-Hold LOW
[5, 8]
VCC = Max., V
= 0.5V –30 –160 mA
OUT
VCC = Min., VIL = 0.8V +75 µA
Sustaining Current
Input Bus-Hold HIGH
VCC = Min., VIH = 2.0V –75 µA
Sustaining Current
Input Bus-Hold LOW
VCC = Max. +500 µA
Overdrive Current
Input Bus-Hold HIGH
VCC = Max. –500 µA
Overdrive Current
is the “Instant On” case temperature.
= –2 mA, IOL = 2 mA for TDO.
[4]
2.4 V
[4]
[6]
[6]
[4]
= 0.5V has been chosen to avoid test
OUT
2.4 V
[6]
[6]
[4]
[7]
2.0 V
[7]
–0.5 0.8 V
4.2 V
4.5 V
3.6 V
3.6 V
0.5 V
0.5 V
CCmax
V
Document #: 38-03007 Rev. *E Page 14 of 64
[+] Feedback
Ultra37000 CPLD Family
Inductance
Parameter Description Test Conditions
L Maximum Pin
Capacitance
[5]
Inductance
[5]
V
= 5.0V
IN
at f = 1 MHz
44-Lead
TQFP
44-Lead
PLCC
44-Lead
CLCC
84-Lead
PLCC
84-Lead
CLCC
100-Lead
TQFP
160-Lead
TQFP
208-Lead
PQFP Unit
25285 8 9 11nH
Parameter Description Test Conditions Max. Unit
C
I/O
C
CLK
C
DP
Endurance Characteristics
Input/Output Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 10 pF
Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 12 pF
Dual-Function Pins
[5]
[9]
VIN = 5.0V at f = 1 MHz at TA = 25°C 16 pF
Parameter Description Test Conditions Min. Typ . Unit
N Minimum Reprogramming Cycles Normal Programming Conditions
3.3V Device Characteristics
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Operating Range
[2]
Range Ambient Temperature
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage............................................. 3.0 to 3.6V
Current into Outputs ......................................................8 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
[2]
Junction Temperature V
[2]
1,000 10,000 Cycles
[10]
CC
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 3.3V ± 0.3V
[3]
Military
–55°C to +125°C –55°C to +130°C 3.3V ± 0.3V
3.3V Device Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min. IOH = –4 mA (Com’l)
IOH = –3 mA (Mil)
V
OL
Output LOW Voltage VCC = Min. IOL = 8 mA (Com’l)
IOL = 6 mA (Mil)
V
IH
V
IL
I
IX
I
OZ
I
OS
I
BHL
I
BHH
I
BHLO
I
BHHO
Notes:
9. Dual pins are I/O with JTAG pins.
10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: V
Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for
all Inputs
Input LOW Voltage Guaranteed Input Logical LOW Voltage for
all Inputs
[7]
[7]
Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10 µA
Output Leakage Current VO = GND or VCC, Output Disabled,
Bus-Hold Disabled
Output Short Circuit Current
[5, 8]
VCC = Max., V
= 0.5V –30 –160 mA
OUT
Input Bus-Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 µA
Input Bus-Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V –75 µA
Input Bus-Hold LOW Overdrive Current VCC = Max. +500 µA
Input Bus-Hold HIGH Overdrive Current VCC = Max. –500 µA
[4]
[4]
[4]
[4]
2.4 V
0.5 V
2.0 5.5 V
–0.5 0.8 V
–50 50 µA
is 3.3V± 0.16V.
CC
Document #: 38-03007 Rev. *E Page 15 of 64
[+] Feedback
Ultra37000 CPLD Family
Inductance
Parameter Description Test Conditions
L Maximum Pin
Capacitance
[5]
Inductance
[5]
V
= 3.3V
IN
at f = 1 MHz
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
208-
Lead
PQFP Unit
252858911nH
Parameter Description Test Conditions Max. Unit
C
I/O
C
CLK
C
DP
Endurance Characteristics
Input/Output Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 8 pF
Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 12 pF
Dual Functional Pins
[5]
[9]
VIN = 3.3V at f = 1 MHz at TA = 25°C 16 pF
Parameter Description Test Conditions Min. Typ . Unit
N Minimum Reprogramming Cycles Normal Programming Conditions
[2]
1,000 10,000 Cycles
AC Characteristics
5.0V AC Test Loads and Waveforms
5 pF
238Ω (COM'L)
319Ω (MIL)
170Ω (COM'L)
236Ω (MIL)
3.0V
GND
ALL INPUT PULSES
90%
10%
<2 ns
(c)
238Ω (COM'L)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
319Ω (MIL)
35 pF
170Ω (COM'L)
236Ω (MIL)
(a) (b)
99Ω (COM'L)
136Ω (MIL)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
2.08V (COM'L)
2.13V (MIL)
90%
10%
<2 ns
5 OR 35 pF
3.3V AC Test Loads and Waveforms
5 pF
295Ω (COM'L)
393Ω (MIL)
340Ω (COM'L)
453Ω (MIL)
3.0V
GND
<2 ns
ALL INPUT PULSES
90%
10%
(c)
90%
10%
<2 ns
295Ω (COM'L)
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
393Ω (MIL)
35 pF
340Ω (COM'L)
453Ω (MIL)
(a) (b)
158Ω (COM’L)
270Ω (MIL)
5 OR 35 pF
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1.77V (COM'L)
1.77V (MIL)
Document #: 38-03007 Rev. *E Page 16 of 64
[+] Feedback
Ultra37000 CPLD Family
t
ER(–)
t
ER(+)
t
EA(+)
t
EA(–)
[11]
V
X
1.5V
2.6V
1.5V
V
the
Output Waveform—Measurement Level
V
OH
0.5V
0.5V
V
OL
0.5V
V
X
V
X
0.5V
V
X
V
X
V
OH
V
OL
Parameter
(d) Test Waveforms
Switching Characteristics Over the Operating Range
[12]
Parameter Description Unit
Combinatorial Mode Parameters
[13, 14, 15]
t
PD
t
PDL
t
PDLL
[13, 14, 15]
t
EA
[11, 13]
t
ER
[13, 14, 15]
[13, 14, 15]
Input to Combinatorial Output ns
Input to Output Through Transparent Input or Output Latch ns
Input to Output Through Transparent Input and Output Latches ns
Input to Output Enable ns
Input to Output Disable ns
Input Register Parameters
t
WL
t
WH
t
IS
t
IH
t
ICO
t
ICOL
[13, 14, 15]
[13, 14, 15]
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-up Time ns
Input Register or Latch Hold Time ns
Input Register Clock or Latch Enable to Combinatorial Output ns
Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns
[8]
[8]
Synchronous Clocking Parameters
[14, 15]
t
CO
[13]
t
S
t
H
[13, 14, 15]
t
CO2
[13]
t
SCS
[13]
t
SL
t
HL
Notes:
measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
11. t
ER
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add t
14. Outputs using Slow Output Slew Rate, add t
15. When V
= 3.3V, add t
CCO
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output ns
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable ns
Register or Latch Data Hold Time ns
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK
, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
0
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0
CLK
, CLK2, or CLK3) or Latch Enable
1
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK
, CLK2, or CLK3) or Latch Enable
1
to this spec.
LP
to this spec.
to this spec.
3.3IO
SLEW
ns
ns
ns
ns
ns
ns
Document #: 38-03007 Rev. *E Page 17 of 64
[+] Feedback
Ultra37000 CPLD Family
Switching Characteristics Over the Operating Range (continued)
[12]
Parameter Description Unit
Product Term Clocking Parameters
[13, 14, 15]
t
COPT
t
SPT
t
HPT
t
ISPT
t
IHPT
t
CO2PT
[13]
[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output ns
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns
Register or Latch Data Hold Time ns
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time ns
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns
Pipelined Mode Parameters
[13]
t
ICS
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous
Clock (CLK
, CLK1, CLK2, or CLK3)
0
Operating Frequency Parameters
f
MAX1
f
MAX2
f
MAX3
f
MAX4
Maximum Frequency with Internal Feedback (Lesser of 1/t
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),
1/(t
S+tH
), or 1/tCO)
[5]
, 1/(tS + tH), or 1/tCO)
SCS
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)
Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/t
or 1/t
SCS
[5]
)
, 1/(tWL + tWH), 1/(tIS + tIH),
ICS
[5]
[5]
Reset/Preset Parameters
t
RW
[13]
t
RR
[13, 14, 15]
t
RO
t
PW
[13]
t
PR
[13, 14, 15]
t
PO
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Asynchronous Reset to Output ns
Asynchronous Preset Width
Asynchronous Preset Recovery Time
Asynchronous Preset to Output ns
[5]
[5]
[5]
[5]
User Option Parameters
t
LP
t
SLEW
t
3.3IO
Low Power Adder ns
Slow Output Slew Rate Adder ns
3.3V I/O Mode Timing Adder
[5]
JTAG Timing Parameters
t
S JTAG
t
H JTAG
t
CO JTAG
f
JTAG
Set-up Time from TDI and TMS to TCK
Hold Time on TDI and TMS
Falling Edge of TCK to TDO
[5]
[5]
Maximum JTAG Tap Controller Frequency
[5]
[5]
ns
ns
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-03007 Rev. *E Page 18 of 64
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Ultra37000 CPLD Family
Switching Characteristics Over the Operating Range
200 MHz 167 MHz
Parameter
Min.
Max.
Min.
Combinatorial Mode Parameters
[13, 14, 15]
t
PD
t
PDL
t
PDLL
[13, 14, 15]
t
EA
[11, 13]
t
ER
[13, 14, 15]
[13, 14, 15]
6 6.5 7.5 8.5 10 12 15 20 ns
11 12.5 14.5 16 16.5 17 19 22 ns
12 13.5 15.5 17 17.5 18 20 24 ns
8 8.5 11 13 14 16 19 24 ns
8 8.5 11 13 14 16 19 24 ns
Input Register Parameters
t
WL
t
WH
t
IS
t
IH
t
ICO
t
ICOL
[13, 14, 15]
[13, 14, 15]
2.5 2.5 2.5 2.5 3 3 4 5 ns
2.5 2.5 2.5 2.5 3 3 4 5 ns
2 222 2 2.5 3 4ns
2 222 2 2.5 3 4ns
11 11 11 12.5 12.5 16 19 24 ns
12 12 12 14 16 18 21 26 ns
Synchronous Clocking Parameters
[14, 15]
t
CO
t
S
t
H
t
CO2
t
SCS
t
SL
t
HL
[13]
[13, 14, 15]
[13]
[13]
4 4 4.5 6 6.5
44555.5
0000 0 0 0 0ns
9.5 10 11 12 14 16 19 24 ns
5 66.57 8
7.5 7.5 8.5 9 10 12 15 15 ns
0 000 0 0 0 0ns
Product Term Clocking Parameters
[13, 14, 15]
t
COPT
t
SPT
t
HPT
t
ISPT
t
IHPT
t
CO2PT
15]
[13]
[13, 14,
7101013 13 13 1520ns
2.5 2.5 2.5 3 5 5.5 6 7 ns
2.5 2.5 2.5 3 5 5.5 6 7 ns
0000 00 00ns
6 6.5 6.5 7.5 9 11 14 19 ns
12 14 15 19 19 21 24 30 ns
154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz
Max.
Min.
Max.
Min.
[12]
Max.
[16]
[16]
Min.
Min.
Max.
[18]
8
[18]
8
[16]
Max.
Min.
[17]
6
6.5
Max.
[17]
10 12 15 ns
Min.
Unit
Max.
10 ns
10 ns
Pipelined Mode Parameters
t
ICS
[13]
56678
[16]
10 12 15 ns
Operating Frequency Parameters
f
MAX1
f
MAX2
f
MAX3
f
MAX4
200 167 154 143 125
200 200 200 167 154 153
125 125 105 91 83 80
167 167 154 125 118 100 83 66 MHz
[16]
100 83 66 MHz
[17]
[17]
[18]
125
100 MHz
62.5 50 MHz
Reset/Preset Parameters
t
RW
[13]
t
RR
Notes:
16. The following values correspond to the CY37512 and CY37384 devices: t
17. The following values correspond to the CY37192V and CY37256V devices: t
for the CY37512 devices: t
18. The following values correspond to the CY37512V and CY37384V devices: t
8 8 8 8 10 12 15 20 ns
10 10 10 10 12 14 17 22 ns
= 7 ns.
S
= 5 ns, tS = 6.5 ns, t
CO
= 6 ns, tS = 7 ns, f
CO
= 6.5 ns, tS = 9.5 ns, and f
CO
= 8.5 ns, t
SCS
= 143 MHz, f
MAX2
ICS
= 105 MHz.
MAX2
= 8.5 ns, f
= 77 MHz, and f
MAX3
MAX1
= 118 MHz.
MAX4
= 100 MHz; and
Document #: 38-03007 Rev. *E Page 19 of 64
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Ultra37000 CPLD Family
Switching Characteristics Over the Operating Range (continued)
200 MHz 167 MHz
Parameter
[13, 14, 15]
t
RO
t
PW
[13]
t
PR
[13, 14, 15]
t
PO
Min.
12 13 13 14 15 18 21 26 ns
8 8 8 8 10 12 15 20 ns
10 10 10 10 12 14 17 22 ns
12 13 13 14 15 18 21 26 ns
User Option Parameters
t
LP
t
SLEW
t
3.3IO
[19]
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
3333 3 3 33ns
0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns
JTAG Timing Parameters
t
S JTAG
t
H JTAG
t
CO JTAG
f
JTAG
0 000 00 00ns
20 20 20 20 20 20 20 20 ns
20 20 20 20 20 20 20 20 ns
20 20 20 20 20 20 20 20 MHz
Max.
Min.
154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz
Max.
Min.
Max.
Min.
Max.
Min.
Switching Waveforms
Combinatorial Output
[12]
Max.
Min.
Max.
Min.
Max.
Min.
Unit
Max.
INPUT
COMBINATORIAL
OUTPUT
Registered Output with Synchronous Clocking
INPUT
SYNCHRONOUS
CLOCK
REGISTERED
OUTPUT
REGISTERED
OUTPUT
SYNCHRONOUS
CLOCK
t
WH
t
PD
t
S
t
H
t
CO
t
CO2
t
WL
Note:
19. Only applicable to the 5V devices.
Document #: 38-03007 Rev. *E Page 20 of 64
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