CYGNL C8051F016 Datasheet
C8051F016 C8051F016 Mixed-Signal 32KB ISP FLASH MCU
PRELIMINARY
ANALOG PERIPHERALS
8051-COMPATIBLE µµC Core
10-bit, 100 KSPS ADC
- ±1LSB INL
- No Missing Codes
- Programmable Throughput up to 100ksps
- 8 External Inputs; Programmable as Single-Ended or Differential
- Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
- Data Dependent Windowed Interrupt Generator
- Built-in Temperature Sensor (± 3°C)
Two 12-bit DACs
- Voltage Output
- 10usec Settling Time
Two Comparators
- 16 Programmable Hysteresis Values
- Configurable to Generate Interrupts or Reset
Reference
- 2.4V; 15 ppm/°C
- External Reference Input
VDD Monitor and Brown-out Detector
ON-CHIP JTAG EMULATION
- On-Chip Emulation Circuitry Facilitates Full Speed, Non-
Intrusive In-Circuit Emulation
- Supports Breakpoints, Single Stepping, Watchpoints
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-Chips,
Target Pods, and Sockets
- Fully Compliant with IEEE 1149.1 Specification
- $99 Emulation Kit (C8051F015DK)
VDD
VDD
DGND
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
XTAL1
XTAL2
Digital Power
Analog Power
JTAG
Logic
VDD
Monitor,
WDT
External
Oscillator
Circuit
Internal
Oscillator
Boundry Scan
Emulation HW
Reset
System Clock
8
0
5
1
C
o
r
e
32kbyte
FLASH
256 byte
RAM
2048 byte
XRAM
SFR Bus
Clock & Reset
Configuration
- Pipelined Instruction Architecture; Executes 70% of Instructions in
1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- Expanded Interrupt Handler; Up to 22 Interrupt Sources
MEMORY
- 2304 Bytes Data RAM
- 32k Bytes FLASH; In-System Programmable in 512 byte Sectors
DIGITAL PERIPHERALS
- 16 Port I/O; All are 5V tolerant
- Hardware I2CTM/SMBusTM, SPITM, and UART Serial Ports
Available Concurrently
- 16-bit Programmable Counter/Timer Array with 5
Capture/Compare Modules (Each Configurable as an 8-Bit PWM)
- 4 General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC,C, or Clock
- Can Switch Between Clock Sources on-the-fly; Useful in Power
Saving Modes
SUPPLY VOLTAGE ......................................................2.7V to 3.6V
- Typical Operating Current: 12mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
48-Pin TQFP Package
Temperature Range: –40°°C to +85°°C
I2C is a trademark of Philips Semi.; SMBus is a trademark of Intel Corp.; SPI is a trademark of Motorola, Inc.
Port I/O
Config.
UART
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
Latch
Port 1
Latch
Port 2
Latch
Crossbar
Config.
Port 3
Latch
Analog Config.
& Control
C
R
O
S
S
B
A
R
S
W
I
T
C
H
ADC
100ksps
(10-Bit)
VREF
DAC0
(12-Bit)
Prog
Gain
TEMP
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
A
M
U
X
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VREF
DAC0
DAC1
(12-Bit)
CP0
CP1
DAC1
CP0+
CP0-
CP1+
CP1-
12.20.2000
C8051F016 C8051F016 Mixed-Signal 32KB ISP FLASH MCU
PRELIMINARY
PACKAGE INFORMATION
C8051F015DK DEVELOPMENT KIT ($99)
SELECTED ELECTRICAL SPECIFICATIONS TA = -40°C to +85°C unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
GLOBAL CHARACTERISTICS
Analog Supply Voltage 2.7 3.6 V
Analog Supply Current Internal REF, ADC, DAC, Comparators all
active
Analog Supply Current with
analog sub-systems inactive
Internal REF, ADC, DAC, Comparators all
disabled
Digital Supply Voltage 2.7 3.6 V
Digital Supply Current with
CPU active
Clock=25MHz
Clock=1MHz
Clock=32kHz
Digital Supply Current
Oscillator not running 2
(shutdown mode)
VDD Data Retention Voltage RAM remains valid 1.5 V
CPU & DIGITAL I/O
Clock Frequency Range DC 25 MHz
Port Output High Voltage IOH = -3mA, Port I/O push-pull VDD – 0.7 V
Port Output Low Voltage IOL = 8.5mA 0.6 V
Input High Voltage 0.8 x VDD V
Input Low Voltage 0.2 x VDD V
SMBus SCL Frequency SYSCLK = MCU system clock SYSCLK/8 MHz
SPI Bus Clock Frequency SYSCLK = MCU system clock SYSCLK/2 MHz
A/D CONVERTER
Resolution 10 bits
Integral Nonlinearity ±1 LSB
Differential Nonlinearity Guaranteed Monotonic
Throughput Rate 100 ksps
Input Voltage Range 0 VREF V
D/A CONVERTERS
Resolution 12 bits
Integral Nonlinearity Specified from Data Word 014h to FEBh
Differential Nonlinearity Guaranteed Monotonic ±1 LSB
Offset Error Data Word = 014h
Output Settling Time To ½ LSB of full-scale 10
Output Voltage Swing 0 VREF- 1LSB V
COMPARATORS
Supply Current (each Comparator) 1.5 µA
Response Time | CP+ – CP- | = 100mV 4
Input Voltage Range -0.25 (AV+) +0.25 V
Input Bias Current -5 0.001 +5 nA
Input Offset Voltage -10 +10 mV
0.8 mA
5
12
0.5
20
µA
mA
mA
µA
µA
±1
±4
±3
LSB
LSB
LSB
µs
µs
D
D1
48
PIN 1
IDENTIFIER
1
A2
e
A1
b
MIN
NOM
(mm)
-
-
1.00
0.22
9.00
7.00
0.50
9.00
7.00
MAX
(mm)
1.20
0.15
1.05
0.27
-
-
-
-
-
(mm)
A
-
A1
A2
D
D1
E
E1
0.05
0.95
b
0.17
-
-
e
-
-
-
E1
E
A
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