CyberPowerPC MPC603EC User Manual
MPR603HSU-03
(IBM Order Number)
(Motorola Order Number)
MPC603EC/D
5/95
REV 2
™
Advance Information
PowerPC
603
™
RISC Microprocessor
Hardware Specifications
The PowerPC 603 microprocessor is an implementation of the PowerPC™ family of
reduced instruction set computer (RISC) microprocessors. This document contains
pertinent physical characteristics of the 603. For functional characteristics of the processor,
refer to the
This document contains the following topics:
Topic Page
Section 1.1, “Overview” 2
Section 1.2, “General Parameters” 4
Section 1.3, “Electrical and Thermal Characteristics” 4
Section 1.4, “Pinout Diagram” 14
Section 1.5, “Pinout Listing” 15
Section 1.6, “Package Description” 17
Section 1.7, “System Design Information” 21
Section 1.8, “Ordering Information” 26
Appendix A, “General Handling Recommendations for the IBM Package” 27
In this document, the term “603” is used as an abbreviation for the phrase, “PowerPC 603
Microprocessor.” The PowerPC 603 microprocessors are available from Motorola as
MPC603 and from IBM as PPC603.
PowerPC 603 RISC Microprocessor User’s Manual.
603 Hardware Specifications
The PowerPC name, PowerPC logotype, PowerPC Architecture, and PowerPC 603 are trademarks of International Business Machines Corp.
used by Motorola under license from International Business Machines Corp.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to
change or discontinue this product without notice.
©
Motorola Inc. 1995
Instruction set and other portions
©
International Business Machines Corp. 1991–1995
1.1 Overview
The 603 is the first low-power implementation of the PowerPC microprocessor family of RISC
microprocessors. The 603 implements the 32-bit portion of the PowerPC Architecture™ specification,
which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data
types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit
integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603 provides four software controllable power -saving modes. Three of the modes (doze, nap, and sleep
modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. The
fourth is a dynamic power management mode that causes the functional units in the 603 to automatically
enter a low-power mode when the functional units are idle without affecting operational performance,
software execution, or any external hardware.
The 603 is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; howe ver , the 603 makes completion appear
sequential.
The 603 integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to ex ecute five
instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency
and throughput for 603-based systems. Most integer instructions execute in one clock cycle. The FPU is
pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603 provides independent on-chip, 8-Kbyte, two-way set-associative, physically addressed caches for
instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603 also
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the Po werPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603 interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603 provides a
three-state coherency protocol that supports the exclusiv e, modified, and invalid cache states. This protocol
is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603 supports single-beat and burst data transfers
for memory accesses; it also supports both memory-mapped I/O and direct-store addressing.
The 603 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with
TTL devices.
1.1.1 PowerPC 603 Microprocessor Features
Major features of the 603 are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
2 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
• Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR) and special-purpose register (SPR) instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides look-ahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 8-Kbyte data cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— 8-Kbyte instruction cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR look-ahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
— Bus extensions for direct-store operations
• Integrated power management
— Low-power 3.3 volt design
— Internal processor/bus clock multiplier that provides 1/1, 2/1, 3/1 and 4/1 ratios
— Three power saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability
603 Hardware Specifications, REV 2 3
Preliminary—Subject to Change without Notice
±
θ
°
° C
°
1.2 General Parameters
The following list provides a summary of the general parameters of the 603.
Technology 0.5
CMOS (four-layer metal)
µ
Die size 11.5 mm x 7.4 mm
Transistor count 1.6 million
Logic design Fully-static
Max. internal frequency 80 MHz
Max. bus frequency 66.67 MHz
Package Surface mount, 240-pin CQFP
Power supply 3.3
5% V dc
For ordering information, refer to Section 1.8, “Ordering Information.”
1.3 Electrical and Thermal Characteristics
This section provides both the AC and DC electrical specifications and thermal characteristics for the 603.
The following specifications are preliminary and subject to change without notice.
1.3.1 DC Electrical Characteristics
Table 1 and Table 2 provide the absolute maximum ratings, thermal characteristics, and DC electrical
characteristics for the 603.
Table 1. Absolute Maximum Ratings
Characteristic Symbol Value Unit
Supply voltage Vdd –0.3 to 4.0 V
Input voltage V
Storage temperature range T
Notes : 1. Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the
maximum listed may affect device reliability or cause permanent damage to the device.
2. Caution : Input voltage must not be greater than the supply voltage by more than 2.5 V at all times
including during power-on reset.
Table 2. Thermal Characteristics
Characteristic Symbol Value Rating
Motorola wire-bond CQFP package thermal resistance,
junction-to-case (typical)
IBM C4-CQFP package thermal resistance,
junction-to-heat sink base
Note: Refer to Section 1.7, “System Design Information,” for more information about thermal management.
in
stg
θ
JS
–0.3 to 5.5 V
–55 to 150
JC
2.2
1.1
C/W
C/W
4 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
≤
µ
µ
Table 3 provides the DC electrical characteristics for the 603.
Table 3. DC Electrical Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T
Characteristic Symbol Min Max Unit
105 ° C
j
≤
Input high voltage (all inputs except SYSCLK) V
Input low voltage (all inputs except SYSCLK) V
SYSCLK input high voltage CV
SYSCLK input low voltage CV
Input leakage current, Vin = 3.465 V
Vin = 5.5 V
Hi-Z (off-state) leakage current, V
Output high voltage, I
Output low voltage, I
Capacitance, V
DBB
, and ARTRY)
Capacitance, V
AR
TRY)
in =
in =
= –9
OH
14
OL
=
0 V, f = 1 MHz
0 V, f = 1 MHz
1
1
=
3.465 V
in
=
V
5.5
in
1
1
V
mA V
mA V
2
(excludes TS
2
(for TS
, ABB,
, ABB, DBB, and
I
in
Iin— TBD
I
TSI
I
TSI
C
C
IH
IL
IH
IL
OH
OL
in
in
2.2 5.5 V
GND 0.8 V
2.4 5.5 V
GND 0.4 V
—10
—10
— TBD
2.4 — V
— 0.4 V
— 10.0 pF
— 15.0 pF
Notes : 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals). For detailed
leakage information, please contact your local Motorola or IBM sales office.
2. Capacitance is periodically sampled rather than 100% tested.
µ
A
A
µ
A
A
Table 4 provides the power dissipation for the 603.
Table 4. Power Dissipation
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T
CPU Clock:
SYSCLK
25 MHz 33 MHz 40 MHz 50 MHz 66 MHz
Full-On Mode
Typical
1:1
Max.
Typical
2:1
Max.
Doze Mode
1
1:1 Typical
2:1 Typical
105 ° C
j
Bus Frequency (SYSCLK)
1.8 2.0 W
2.5 2.9 W
745 800 mW
Unit
1.8 W
2.5 W
740 mW
603 Hardware Specifications, REV 2 5
Preliminary—Subject to Change without Notice
Table 4. Power Dissipation (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T
105 ° C
j
≤
≤
CPU Clock:
SYSCLK
Nap Mode
1
25 MHz 33 MHz 40 MHz 50 MHz 66 MHz
1:1 Typical
2:1 Typical
Sleep Mode
1
140 160 mW
1:1 Typical
2:1 Typical
Sleep Mode—PLL Disabled
1
110 130 mW
1:1 Typical
2:1 Typical
30 40 mW
Sleep Mode—PLL and SYSCLK Disabled
1:1 Typical
2:1 Typical
2.0 2.0 mW
Bus Frequency (SYSCLK)
160 mW
125 mW
70 mW
1
2.0 mW
Note : 1. The values provided for this mode do not include pad driver power (OVDD) or analog supply power
(AVDD). Worst-case AVDD = 15 mW.
Unit
1.3.2 AC Electrical Characteristics
This section provides the clock and AC electrical characteristics for the 603.
1.3.2.1 Clock AC Specifications
Table 5 provides the clock AC timing specifications as defined in Figure 1. These specifications are for 25,
33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies.
Table 5. Clock AC Timing Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 ≤ T
25 MHz 33.33 MHz 40 MHz 50 MHz 66.67
Num Characteristic
Min Max Min Max Min Max Min Max Min Max
Frequency of
operation
1 SYSCLK cycle
time
2,3 SYSCLK rise
and fall time
4 SYSCLK duty
cycle
measured at
1.4 V
16.67 25.0 25.0 33.33 33.33 40.0 40.0 50.0 50.0 66.67 MHz
40.0 60.0 30.0 40.0 25.0 30.0 20.0 25.0 15.0 20.0 ns
— 2.0 — 2.0 — 2.0 — 2.0 — 2.0 ns 1
40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 % 3
J
105 ° C
Unit Notes
6 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
Table 5. Clock AC Timing Specifications (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 ≤ T
25 MHz 33.33 MHz 40 MHz 50 MHz 66.67
Num Characteristic
Min Max Min Max Min Max Min Max Min Max
J
105 °C
±
Unit Notes
±
±
±
µ
≤
8 SYSCLK
short- and
long-term jitter
9 603 internal
PLL relock time
Notes : 1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
2. This is the sum total of both short- and long-term jitter, and is guaranteed by design.
3. Timing is guaranteed by design and characterization, and is not tested.
4. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached
during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET
bus clocks after the PLL relock time (100 µ s) during the power-on reset sequence.
5. Caution : The SYSCLK frequency and PLL_CFG0–PLL_CFG3 settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG0–PLL_CFG3 signal description in Section 1.7,
“System Design Information,” for valid PLL_CFG0–PLL_CFG3 settings, and to Section 1.8, “Ordering Information,”
for available frequencies and part numbers.
SYSCLK
—
— 100 — 100 — 100 — 100 — 100
150 — ± 150 —
1
VM
150 —
CVil
150 —
must be held asserted for a minimum of 255
CVih
150 ps 2
s 3,4
2 3
VM = Midpoint Voltage (1.4 V)
Figure 1. SYSCLK Input Timing Diagram
1.3.2.2 Input AC Specifications
Table 6 provides the input AC timing specifications for the 603 as defined in Figure 2 and Figure 3. These
specifications are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies
603 Hardware Specifications, REV 2 7
Preliminary—Subject to Change without Notice
.
Table 6. Input AC Timing Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ TJ ≤ 105 °C
Num Characteristic
10a Address/data/transfer
attribute inputs valid
to SYSCLK (input
setup)
10b All other inputs valid
to SYSCLK (input
setup)
10c Mode select inputs
valid to HRESET
(input setup)
(for DRTRY, QACK
and TLBISYNC)
11a SYSCLK to
address/data/transfer
attribute inputs
invalid (input hold)
11b SYSCLK to all other
inputs invalid (input
hold)
11c HRESET to mode
select inputs invalid
(input hold)
(for DRTRY, QACK,
and TLBISYNC)
25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 MHz
Min Max Min Max Min Max Min Max Min Max
4.5 — 4.0 — 3.5 — 3.0 — 2.5 — ns 2
6.5 — 6.0 — 5.5 — 5.0 — 4.5 — ns 3
8 *
t
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns 2
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns 3
— 8 *
sys
0—0—0—0—0—ns4,6,7
t
sys
— 8 *
t
sys
— 8 *
t
sys
— 8 *
t
sys
Unit
Notes
— ns 4,5,
6,7
Notes: 1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the
rising edge of the input SYSCLK. Both input and output timings are measured at the pin. See Figure 2.
2. Address/data/transfer attribute input signals are composed of the following: A0–A31, AP0–AP3, TT0–TT4,
TC0–TC1, T
3. All other input signals are composed of the following: TS, XATS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA,
DRTRY, TEA, DBDIS,HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 3.
5. t
SYS
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of
255 bus clocks after the PLL relock time (100 µs) during the power-on reset sequence.
BST , TSIZ0–TSIZ2, GBL, DH0–DH31, DL0–DL31, DP0–DP7.
is the period of the external clock (SYSCLK) in nanoseconds.
8 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
ALL INPUTS
VMSYSCLK
10a
10b
11a
11b
VM = Midpoint Voltage (1.4V)
Figure 2. Input Timing Diagram
HRESET
VM
10c
11c
MODE PINS
VM = Midpoint Voltage (1.4 V)
Figure 3. Mode Select Input Timing Diagram
1.3.2.3 Output AC Specifications
Table 7 provides the output AC timing specifications for the 603 (shown in Figure 4). These specifications
are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies.
Table 7. Output AC Timing Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 °C
25 33.33 40 50 66.67
Num Characteristic
Min Max Min Max Min Max Min Max Min Max
Unit Notes
12 SYSCLK to output
driven (output enable
time)
13a SYSCLK to output
valid (5.5 V to
0.8 V— TS, ABB,
TRY, DBB)
AR
13b SYSCLK to output
valid (TS, ABB,
ARTRY, DBB)
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
— 14.0 — 13.0 — 12.0 — 11.0 — 10.0 ns 4
— 13.0 — 12.0 — 11.0 — 10.0 — 9.0 ns 6
603 Hardware Specifications, REV 2 9
Preliminary—Subject to Change without Notice
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