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CT-CIB61
Intel® 3rd Generation Core™ Processor i7/i5/i3/Celeron
COM Express™ Type 6 Module
User’s Manual
Version 1.0
C&T Solution Inc.
12F. -1, No.700, Zhongzheng Rd., Zhonghe Dist., New Taipei City 235, Taiwan
TEL: 886-2-77317888
http://www.candtsolution.com
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Table of Contents
I. Preface ..................................................................................................... ５
1.1 Disclaimer ...................................................................................... ５
1.2 Copyright Notice ............................................................................. ５
1.3 Trademarks Acknowledgment ........................................................ ５
II. Introduction.............................................................................................. ６
2.1 Product Description ........................................................................ ６
2.2 Specifications ................................................................................. ７
2.3 Block Diagram ................................................................................ ９
2.4 SKU ............................................................................................. １０
III. Mechanical Specification ..................................................................... １１
3.1 Module Dimensions ..................................................................... １１
3.2 Layout ......................................................................................... １２
3.3 Connectors and Switch ............................................................... １４
3.3.1 LPC Debug Port: CN3 ....................................................... １４
3.3.2 CPLD JTAGE .................................................................... １４
3.3.3 COM Express Connectors ................................................ １４
3.3.4 PCIE Port Bifurcation: SW1............................................... １８
3.4 Thermal Solutions ....................................................................... １８
3.4.1 Fan Sink ............................................................................ １８
3.4.2 Heat Spreader ................................................................... ２０
IV. Features & Interfaces .......................................................................... ２２
4.1 Processor .................................................................................... ２２
4.2 BIOS............................................................................................ ２２
4.3 System Memory .......................................................................... ２２
4.4 Chipset ........................................................................................ ２２
4.5 Graphics ...................................................................................... ２２
4.5.1 VGA Output ....................................................................... ２３
4.5.2 LVDS ................................................................................. ２４
4.5.3 DDI .................................................................................... ２４
4.6 USB ............................................................................................. ２７
4.6.1 USB 2.0 ............................................................................. ２７
4.6.2 USB 3.0 ............................................................................. ２８
4.7 SATA ........................................................................................... ２８
4.8 PCI Express ................................................................................ ２９
4.8.1 PCI Express x1 ................................................................. ２９
4.8.2 PCI Express x16 ............................................................... ３０
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4.9 High Definition Audio ................................................................... ３０
4.10 Ethernet ..................................................................................... ３０
4.11 LPC ........................................................................................... ３１
4.12 SPI ............................................................................................ ３１
4.13 SMBus ....................................................................................... ３２
4.14 ExpressCard ............................................................................. ３３
4.15 General Purpose Input Output .................................................. ３３
4.15.1 GPIO Configuration ......................................................... ３３
4.15.2 Registers Description ...................................................... ３４
4.15.3 PSUEDO CODE .............................................................. ３６
4.16 Watchdog Timer ........................................................................ ３７
4.16.1 Board Design .................................................................. ３７
4.16.2 PSUEDO CODE .............................................................. ３７
4.17 Power and System Management Signals .................................. ３８
4.18 Thermal Management Signals .................................................. ３８
4.19 Miscellaneous Signals ............................................................... ３８
V. SYSTEM BIOS ..................................................................................... ３９
5.1 Main ............................................................................................ ３９
5.2 Advanced .................................................................................... ４０
5.2.1 ACPI Settings .................................................................... ４１
5.2.2 Trusted Computing ............................................................ ４２
5.2.1 CPU Configuration ............................................................ ４３
5.2.2 SATA Configuration .......................................................... ４４
5.2.3 USB Configuration ............................................................ ４５
5.2.4 W83627DHG Super IO Configuration ............................... ４６
5.2.5 W83627DHG H/W Monitor ................................................ ４８
5.2.6 F81801 Super IO Configuration ........................................ ４９
5.2.7 F81801 H/W Monitor ......................................................... ５１
5.2.8 Serial Port Console Redirection ........................................ ５２
5.2.9 CPU PPM Configuration ................................................... ５３
5.3 Chipset ........................................................................................ ５４
5.3.1 PCH-IO Configuration ....................................................... ５５
5.3.2 System Agent Configuration.............................................. ６０
5.4 Boot ............................................................................................. ６５
5.4.1 CSM16 Parameters ........................................................... ６６
5.4.2 CSM Parameters ............................................................... ６７
5.5 Security ....................................................................................... ６８
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5.6 Save and Exit .............................................................................. ６９
VI. Address Map ....................................................................................... ７０
6.1 I/O Port Address Map .................................................................. ７０
6.2 Interrupt Controller (IRQ) Map ..................................................... ７２
6.3 Memory Map ............................................................................... ７５
VII. Electrical Specification ....................................................................... ７６
7.1 Input Power ................................................................................. ７６
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I. Preface
1.1 Disclaimer
All specifications and information in this User’s Manual are believed to be
accurate and up to date. C&T Solution Inc. does not guarantee that the
contents herein are complete, true, accurate or non-misleading. The
information in this document is subject to change without notice and does not
represent a commitment on the part of C&T Solution Inc.
C&T Solution Inc. disclaims all warranties, express or implied, including,
without limitation, those of merchantability, fitness for a particular purpose with
respect to contents of this User’s Manual. Users must take full responsibility for
the application of the product.
1.2 Copyright Notice
All rights reserved. No part of this manual may be reproduced or transmitted in
any form or by any means, electronic or mechanical, including photocopying,
recording, or information storage and retrieval systems, without the prior
written permission of C&T Solutions Inc.
Copyright © 2012 C&T Solutions Inc.
1.3 Trademarks Acknowledgment
Intel®, Celeron® and Pentium® are trademarks of Intel Corporation.
Windows® is registered trademark of Microsoft Corporation.
AMI is trademark of American Megatrend Inc.
IBM, XT, AT, PS/2 and Personal System/2 are trademarks of International
Business Machines Corporation
All other products and trademarks mentioned in this manual are trademarks of
their respective owners.
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II. Introduction
2.1 Product Description
The CT-CIB61 is a new COM (computer-on-module) Express® basic form
factor (125x95mm) in embedded computing platforms. It combines a socket G
for Intel® 3rd Generation Core i7/i5/i3 processors with Intel® QM77 Express
chipset. With specified configurations, three display could be supported. The
CT-CIB61 is based on the COM Express® specification and features a
standardized connector layout that carries a specified set of signals. With the
Type 6 pin-out connectors, the CT-CIB61 supports HDMI/DVI/LVDS/VGA,
SATA, HD audio, Gigabit Ethernet, PCIe and USB3.0. This system requires a
Carrier Board to bring out I/O and power up. The benefit of this standardization
pin-out is making the application design more flexible. To accommodate
different ODM requirements, the COM Express module with a Carrier Board is
the best cost-effective solution and reduces development time.
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2.2 Specifications
CPU
Intel® 3rd Generation Core i7/ i5/ i3/ Celeron processor
Socket G (rPGA988)
Chipset
Intel® QM77 Express Chipset
System Memory
Two 204-pin DDR3/DDR3L SODIMM sockets
Up to 1600MHz
Up to 32GB
BIOS
AMI uEFI BIOS
8MB SPI Flash ROM
iAMT
iAMT8.0
Graphics
Intel® HD Graphics 4000 integrated with CPU
Support up to three displays
Resolution up to 2560x1600
Two channels of 24-bit LVDS interface
Support HDMI / DVI / LVDS/DisplayPort / SDVO
Ethernet
Intel® 82579LM
10/100/1000 Mbps
Audio
Integrated in chipset Intel® QM77
SATA Interface
Two SATA 6Gb/s ports
Two SATA 3Gb/s ports
PCIe Lane
One PCIex16 Lanes
Six PCIex1 Lanes
USB Interface
Eight USB 2.0 ports
Four USB 3.0 ports
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Two UART Ports
LPC Interface
SMBus
SPI Interface
8-bit GPIO
Watchdog Timer
H/W Monitor
Power Management
ACPI (Advanced Configuration and Power Interface)
Form Factor
Basic size, 125mm x 95mm
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2.3 Block Diagram
Connector ROW A
,
B
CPU
Ivy Bridge
DDR3
/DDR3L
1333/1600MHz
2xSATA 6G; 2xSATA 3G
SPI
PCIEx1, Port 0~Port5
8xUSB2.0
VGA
HDA
Connector ROW C
,
D
PEG; 1x16;
2x8 &2x4
GbE
PCH
Intel QM77
GPIx4; GPOx4
Debug
Port
TPM
Channel A
204pin
SODIMM
HWM
NCT7802Y
DMI
SM Bus
24-
bit LVDS dual
-
channel
BIOS
LPC
CPLD
FDI
Channel B
204pin
SODIMM
DDR3
/DDR3L
1333/1600MHz
Super
I/O
I2C
Tx/Rx x2
SM Bus
Intel
82579LM
PCIEx1
Port 7
SDVO/Display Port/HDMI
Display Port/HDMI
Display Port/HDMI
PCIEx1, Port 6
4xUSB3.0
System
clock out
25 MHz
crystal
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2.4 SKU
Product
Number
Processor PCH Features
CT-CIB61 Socket G for 3rd
Gen Core i7,i5,i3
QM77 2xDDR3, LVDS, VGA, 3xDDI, PCIex16, 7xPCIex1,
GbE, 4xUSB3.0, 8xUSB2.0, 4xSATA, GPIO,
iAMT8.0
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III. Mechanical Specification
3.1 Module Dimensions
The PCB size of CT-CIB61 is 125mm x 95mm, the standard COM Express
Basic Module size.
The holes shown in the drawing below is for stacking the module with the Heat
Spreader / Fan Sink and the Carrier Board. The mounting holes are 2.7mm,
and the 2.5mm hardware shall be used. The position and the dimension of the
holes are shown in the unit of millimeters.
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3.2 Layout
There are two SODIMM sockets. Each of them is mounted separately on each
side of the CT-CIB61. Two 220-pin COM Express connectors are mounted at
the bottom side of the PCB.
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Top Side:
Bottom Side:
CN1
CN4 CN3
SW1
CN5
CN6
CN2
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3.3 Connectors and Switch
Connector Description
CN1 Top DDR3 SO-DIMM Connector
CN2 Bottom DDR3 SO-DIMM Connector
CN3 LPC Debug Port
CN4 CPLD JTAGE
CN5
COM™ Express connector Row A, B
CN6
COM™ Express connector Row C, D
SW1 PCIE Port Bifurcation Straps
LPC Debug Port: CN3
3.3.1
1 GND 2 3.3V
3 LPC_AD3 4 BIOS_DIS0_L
5 LPC_AD2 6 RESET
7 LPC_AD1 8 CLOCK
9 LPC_AD0 10 FRAME
CPLD JTAGE
3.3.2
1 3.3V 2 GND
3 TDO 4 GND
5 TDI 6 GND
7 TMS 8 GND
9 TCK 10 GND
COM Express Connectors
3.3.3
The CT-CIB61 is connected to the carrier board via two 220-pin connectors.
Each connector is break down into two rows. The first connector, CN5,
consists Row A and Row B; the second connector, CN6, consists Row C and
Row D. Their pin-out is as table below.
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Pin Row A Row B Row C Row D
1 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
2 GBE0_MDI3- GBE0_ACT# GND GND
3 GBE0_MDI3+ LPC_FRAME# USB_SSRX0- USB_SSTX0-
4 GBE0_LINK100# LPC_AD0 USB_SSRX0+ USB_SSTX0+
5 GBE0_LINK1000# LPC_AD1 GND GND
6 GBE0_MDI2- LPC_AD2 USB_SSRX1- USB_SSTX1-
7 GBE0_MDI2+ LPC_AD3 USB_SSRX1+ USB_SSTX1+
8 GBE0_LINK# LPC_DRQ0# GND GND
9 GBE0_MDI1- LPC_DRQ1# USB_SSRX2- USB_SSTX2-
10 GBE0_MDI1+ LPC_CLK USB_SSRX2+ USB_SSTX2+
11 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
12 GBE0_MDI0- PWRBTN#- USB_SSRX3- USB_SSTX3-
13 GBE0_MDI0+ SMB_CK USB_SSRX3+ USB_SSTX3+
14 GBE0_CTREF SMB_DAT GND GND
15 SUS_S3# SMB_ALERT# DDI1_PAIR6+
DDI1_CTRLCLK_AUX+
16 SATA0_TX+ SATA1_TX+ DDI1_PAIR6-
DDI1_CTRLDATA_AUX-
17 SATA0_TX- SATA1_TX- NC NC
18 SUS_S4# SUS_STAT# NC NC
19 SATA0_RX+ SATA1_RX+ PCIE_RX6+ PCIE_TX6+
20 SATA0_RX- SATA1_RX- PCIE_RX6- PCIE_TX6-
21 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
22 SATA2_TX+ SATA3_TX+ NC NC
23 SATA2_TX- SATA3_TX- NC NC
24 SUS_S5# PWR_OK DDI1_HPD NC
25 SATA2_RX+ SATA3_RX+ DDI1_PAIR4+ NC
26 SATA2_RX- SATA3_RX- DDI1_PAIR4- DDI1_PAIR0+
27 BATLOW# WDT NC DDI1_PAIR0-
28 (S)ATA_ACT# AC/HAD_SDIN2 NC NC
29 AC/HDA_SYNC AC/HAD_SDIN1 DDI1_PAIR5+ DDI1_PAIR1+
30 AC/HAD_RST# AC/HAD_SDIN0 DDI1_PAIR5- DDI1_PAIR1-
31 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
32 AC/HDA_BITCLK SPKR
DDI2_CTRLCLK_AUX+
DDI1_PAIR2+
33 AC/HAD_SDOUT I2C_CK
DDI2_ CTRLDATA_AUX-
DDI1_PAIR2-
34 BIOS_DIS0# I2C_DAT
DDI2_DDC_AUX_SEL DDI1_DDC_AUX_SEL
35 THRMTRIP# THRM# NC NC
36 USB6- USB7-
DDI3_CTRLCLK_AUX+
DDI1_PAIR3+
37 USB6+ USB7+
DDI3_ CTRLDATA_AUX-
DDI1_PAIR3-
38 USB_6_7_OC# USB_4_5_OC#
DDI3_DDC_AUX_SEL
NC
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Pin Row A Row B Row C Row D
39 USB4- USB5- DDI3_PAIR0+ DDI2_PAIR0+
40 USB4+ USB5+ DDI3_PAIR0- DDI2_PAIR0-
41 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
42 USB2- USB3- DDI3_PAIR1+ DDI2_PAIR1+
43 USB2+ USB3+ DDI3_PAIR1- DDI2_PAIR1-
44 USB_2_3_OC# USB_0_1_OC# DDI3_HPD DDI2_HPD
45 USB0- USB1- NC NC
46 USB0+ USB1+ DDI3_PAIR2+ DDI2_PAIR2+
47 VCC_RTC EXCD1_PERST# DDI3_PAIR2- DDI2_PAIR2-
48 EXCD0_PERST# EXCD1_CPPE# NC NC
49 EXCD0_CPPE# SYS_RESET# DDI3_PAIR3+ DDI2_PAIR3+
50 LPC_SERIRQ CB_RESET# DDI3_PAIR3- DDI2_PAIR3-
51 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
52 PCIE5_TX+ PCIE5_RX+ PEG_RX0+ PEG_TX0+
53 PCIE5_TX- PCIE5_RX- PEG_RX0- PEG_TX0-
54 GPI0 GPO1 NC PEG_LANE_RV#
55 PCIE4_TX+ PCIE4_RX+ PEG_RX1+ PEG_TX1+
56 PCIE4_TX- PCIE4_RX- PEG_RX1- PEG_TX1-
57 GND GPO2 NC GND
58 PCIE3_TX+ PCIE3_RX+ PEG_RX2+ PEG_TX2+
59 PCIE3_TX- PCIE3_RX- PEG_RX2- PEG_TX2-
60 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
61 PCIE2_TX+ PCIE2_RX+ PEG_RX3+ PEG_TX3+
62 PCIE2_TX- PCIE2_RX- PEG_RX3- PEG_TX3-
63 GPI1 GPO3 NC NC
64 PCIE1_TX+ PCIE1_RX+ NC NC
65 PCIE1_TX- PCIE1_RX- PEG_RX4+ PEG_TX4+
66 GND WAKE0# PEG_RX4- PEG_TX4-
67 GPI2 WAKE1# NC GND
68 PCIE0_TX+ PCIE0_RX+ PEG_RX5+ PEG_TX5+
69 PCIE0_TX- PCIE0_RX- PEG_RX5- PEG_TX5-
70 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
71 LVDS_A0+ LVDS_B0+ PEG_RX6+ PEG_TX6+
72 LVDS_A0- LVDS_B0- PEG_RX6- PEG_TX6-
73 LVDS_A1+ LVDS_B1+ GND GND
74 LVDS_A1- LVDS_B1- PEG_RX7+ PEG_TX7+
75 LVDS_A2+ LVDS_B2+ PEG_RX7- PEG_TX7-
76 LVDS_A2- LVDS_B2- GND GND
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Pin Row A Row B Row C Row D
77 LVDS_VDD_EN LVDS_B3+ NC NC
78 LVDS_A3+ LVDS_B3- PEG_RX8+ PEG_TX8+
79 LVDS_A3- LVDS_BKLT_EN PEG_RX8- PEG_TX8-
80 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
81 LVDS_A_CK+ LVDS_B_CK+ PEG_RX9+ PEG_TX9+
82 LVDS_A_CK- LVDS_B_CK- PEG_RX9- PEG_TX9-
83 LVDS_I2C_CK LVDS_BKLT_CTRL NC NC
84 LVDS_I2C_DAT VCC_5V_SBY GND GND
85 GPI3 VCC_5V_SBY PEG_RX10+ PEG_TX10+
86 NC VCC_5V_SBY PEG_RX10- PEG_TX10-
87 NC VCC_5V_SBY GND GND
88 PCIE_CK_REF0+ BIOS_DIS1# PEG_RX11+ PEG_TX11+
89 PCIE_CK_REF0- VGA_RED PEG_RX11- PEG_TX11-
90 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
91 SPI_POWER VGA_GRN PEG_RX12+ PEG_TX12+
92 SPI_MISO VGA_BLU PEG_RX12- PEG_TX12-
93 GPO0 VGA_HSYNC GND GND
94 SPI_CLK VGA_VSYNC PEG_RX13+ PEG_TX13+
95 SPI_MOSI VGA_I2C_CK PEG_RX13- PEG_TX13-
96 TPM_PP VGA_I2C_DAT GND GND
97 NC SPI_CS# NC NC
98 SER0_TX NC PEG_RX14+ PEG_TX14+
99 SER0_RX NC PEG_RX14- PEG_TX14-
100 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
101 SER1_TX FAN_PWMOUT PEG_RX15+ PEG_TX15+
102 SER1_RX FAN_TACHIN PEG_RX15- PEG_TX15-
103 LID# SLEEP# GND GND
104 VCC_12V VCC_12V VCC_12V VCC_12V
105 VCC_12V VCC_12V VCC_12V VCC_12V
106 VCC_12V VCC_12V VCC_12V VCC_12V
107 VCC_12V VCC_12V VCC_12V VCC_12V
108 VCC_12V VCC_12V VCC_12V VCC_12V
109 VCC_12V VCC_12V VCC_12V VCC_12V
110 GND(FIXED) GND(FIXED) GND(FIXED) GND(FIXED)
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PCIE Port Bifurcation: SW1
3.3.4
Pin1&4 Pin2&3 Function Switch
OFF OFF (Default) x16 Device 1 function 1 and 2
disabled
OFF ON X8, x8 – Device 1 function enabled;
function 2 disabled
ON OFF Reserved – (Device 1 function
disabled; function 2 enabled)
ON ON x8, x4, x4 – Device 1 functions 1 & 2
enabled
3.4 Thermal Solutions
There are two thermal solutions for the COM Module CT-CIB61 to dissipate
the heat. One is by using a fan sink and the other one is by using a heat
spreader.
Fan Sink
3.4.1
Step 1: Place the fan sink on top of the CT-CIB61 module.
Step 2: Use three screws (M2.5x5L) to secure the fan sink with the CT-CIB61,
as illustrated below.
Step 3: Connect the COM Express connectors on the CT-CIB61 to the
corresponding COM connectors on the Carrier Board. Make sure the four
holes at the corners of CT-CIB61 module align to the corresponding pillars on
the Carrier Board.
Step4: Use five screws (M2.5x15L) to secure the fan sink with the Carrier
Board through the corresponding holes on the CT-CIB61.
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Heat Spreader
3.4.2
A heat spreader is designed for the CT-CIB61 to dissipate heat. All heat
generating components are thermally conducted to the heat spreader in order
to avoid hot spots.
Step 1: Place the heat spreader plate on top of the CT-CIB61 module.
Step 2: Use three screws (M2.5x5L) to secure the heat spreader with the
CT-CIB61, as illustrated below.
Step 3: Connect the COM Express connectors on the CT-CIB61 to the
corresponding COM connectors on the Carrier Board. Make sure the four
holes at the corners of CT-CIB61 module align to the corresponding pillars on
the Carrier Board.
Step4: Use five screws (M2.5x15L) to secure the heat spreader with the
Carrier Board through the corresponding holes on the CT-CIB61.
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CT-CIB61 Intel® 3rd Generation Core™ Processor i7/i5/i3 COM Express Type 6 Module
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IV. Features & Interfaces
4.1 Processor
The CT-CIB61 with Socket G supports Intel® 3rd Generation Core i7/ i5/ i3
rPGA988B type processor. This is the next generation of 64-bit and multi-core
mobile processors built on 22-nanometer process technology. This processor
is designed for a two-chip platform, which consists a processor and Platform
Controller Hub (PCH). The processor includes Integrated Display Engine,
Processor Graphics and Integrated Memory Controller. Such platform enables
higher performance, lower cost, easier validation and improved x-y footprint.
4.2 BIOS
The AMI uEFI BIOS, 8MB SPI Flash Rom is used in CT-CIB61 module.
4.3 System Memory
The Integrated Memory Controller (IMC) of the processor supports DDR3
protocols with two independent, 64-bit wide channels. Each channel allows the
data transfer rate of 1333/1600MHz with a 204-pin SODIMM socket. With
standard 1-Gb, 2-Gb and 4-Gb DDR3 DRAM technologies, these two
SODIMM sockets on the CT-CIB61 support the maximum memory of 32GB.
However, the memory size of the first channel, CN3, must be greater or equal
to the memory size of the second channel, CN4.
4.4 Chipset
The Platform Controller Hub (PCH) used on CT-CIB61 is QM77. The PCH
provides extensive I/O support with two COM™ Express connectors.
4.5 Graphics
The graphics is integrated in the processor. There are three display pipes in
the Graphic Engine. Each of them operates independently and sends display
data to the PCH over the Intel Flexible Display Interface, Intel® FDI. The PCH
integrates the latest display technologies such as HDMI, DisplayPort,
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CT-CIB61 Intel® 3rd Generation Core™ Processor i7/i5/i3 COM Express Type 6 Module
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Embedded DisplayPort, Intel® SDVO and DVI along with legacy display
technologies-Analog Port (VGA) and LVDS. The Analog Port and LVDS Port
are dedicated ports on the PCH, and the Digital Ports B, C, and D can be
configured to drive HDMI, DVI, or DisplayPort. Digital Port B can also be
configured as Intel SDVO while Digital Port D can be configured as eDP.
The two displays mode can be any combination of DisplayPort, HDMI, DVI,
and VGA. However, the three display configuration is restricted to 2
DisplayPorts and any other display interface. The Chanel A of FDI has 4
transmit (Tx) differential pairs and supports maximum resolution of
2560x1600@60Hz while Channel B and C have two transmit (Tx) differential
pairs and support maximum resolution of 1920x1200@60Hz.
Digital Port [FDI
CH A –x4]
Digital Port [FDI
CH B –x2]
Digital Port [FDI
CH C –x2]
Configuration 1 LVDS
2560x1600, 60Hz
DisplayPort
1920x1200, 60Hz
DisplayPort
1920x1200, 60Hz
Configuration 2 VGA
2560x1600, 60Hz
DisplayPort
1920x1200, 60Hz
DisplayPort
1920x1200, 60Hz
Configuration 3 DisplayPort
2560x1600, 60Hz
DisplayPort
1920x1200, 60Hz
DisplayPort
1920x1200, 60Hz
Configuration 4 LVDS
2560x1600, 60Hz
VGA
2560x1600, 60Hz
None
Configuration 5 VGA
2560x1600, 60Hz
HDMI
2560x1600, 60Hz
None
VGA Output
4.5.1
The Analog Port provides a RGB signal output along with a HSYNC and
VSYNC signal. There is an associated Display Data Channel (DDC) signal pair
dedicated to the Analog Port. The intended target device is for a monitor with a
VGA connector.
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Signal I/O Description
VGA_RED O
Red for monitor. Analog DAC output, designed to
drive a 37.5Ω equivalent load.
VGA_GRN O
Green for monitor. Analog DAC output, designed
to drive a 37.5Ω equivalent load.
VGA_BLU O
Blue for monitor. Analog DAC output, designed
to drive a 37.5Ω equivalent load.
VGA_HSYNC O
Horizontal sync output to VGA monitor
VGA_VSYNC O
Vertical sync output to VGA monitor
VAG_I2C_CLK
I/O
Monitor Control Clock
VGA_I2C_DATA
I/O
Monitor Control Data
LVDS
4.5.2
There are two LVDS transmitter channels (Channel A and Channel B) in the
LVDS interface. Each channel consists of 4-data pairs and a clock pair.
In the single channel mode, only Channel A is used. Channel B cannot be
used for single channel mode. In the dual channel mode, both Channel A and
Channel B pins are used concurrently to drive one LVDS display.
Signal I/O Description
LVDS_A[0:3]+
LVDS_A[0:3]-
O
LVDS Channel A differential pairs
LVDS_A_CK+
LVDS_A_CK-
O
LVDS Channel A differential clock
LVDS_B[0:3]+
LVDS_B[0:3]-
O
LVDS Channel B differential pairs
LVDS_B_CK+
LVDS_B_CK-
O
LVDS Channel B differential clock
LVDS_VDD_EN O
LVDS panel power enable
LVDS_BKLT_EN
O
LVDS panel backlight enable
LVDS_BKLT_CTRL
O
LVDS panel backlight brightness control
LVDS_I2C_CK
I/O
I2C clock output for LVDS display use
LVDS_I2C_DAT
I/O
I2C data line for LVDS display use
DDI
4.5.3
There are three Digital Display Interfaces, DDI1, DDI2 and DDI3. Each DDI
can transmit data according to one or more protocols. All three DDI can be
configured to drive natively HDMI, DisplayPort, or DVI. DDI1 also supports
Serial Digital Video Out(SDVO).
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Signal I/O Description
DDI[1:3]_PAIR[0:3]+
DDI[1:3]_PAIR[0:3]-
O
DDI 1 to 3 Pair[0:3] differential pairs
DDI[1:3]_DDC_AUX_SEL I
Selects the function of
DDI[1:3]_CTRLCLK_AUX+ and
DDI[1:3]_CTRLDATA_AUX-. This pin shall have
a 1M pull-down to logic ground on the Module. If
this input is floating the AUX pair is used for the
DP AUX+/- signals. If pulled-high the AUX pair
contains the CTRLCLK and CTRLDATA signals.
DDI[1:3]_CTRLCLK_AUX+ I/O
DP AUX+ function if DDI[1:3]_DDC_AUX_SEL is
no connect
I/O
HDMI/DVI I2C CTRLCLK if
DDI[1:3]_DDC_AUX_SEL is pulled high
DDI[1:3]_CTRLDATA_AUX- I/O
DP AUX- function if DDI[1:3]_DDC_AUX_SEL is
no connect
I/O
HDMI/DVI I2C CTRLDATA if
DDI[1:3]_DDC_AUX_SEL is pulled high
DDI[1:3]_HPD I
DDI Hot-Plug Detect
Signal Pin SDVO DP HDMI/DVI
DDI
1
DDI1_PAIR0+ D26 SDVO1_RED+ DP1_LANE0+
TMDS1_DATA2+
DDI1_PAIR0- D27 SDVO1_RED- DP1_LANE0-
TMDS1_DATA2-
DDI1_PAIR1+ D29 SDVO1_GRN+ DP1_LANE1+
TMDS1_DATA1+
DDI1_PAIR1- D30 SDVO1_GRN- DP1_LANE1-
TMDS1_DATA1-
DDI1_PAIR2+ D32 SDVO1_BLU+ DP1_LANE2+
TMDS1_DATA0+
DDI1_PAIR2- D33 SDVO1_BLU- DP1_LANE2-
TMDS1_DATA0-
DDI1_PAIR3+ D36 SDVO1_CK+ DP1_LANE3+ TMDS1_CLK+
DDI1_PAIR3- D37 SDVO1_CK- DP1_LANE3- TMDS1_CLK-
DDI1_PAIR4+ C25 SDVO1_INT+
DDI1_PAIR4- C26 SDVO1_INT-
DDI1_PAIR5+ C29
SDVO1_TVCLKIN+
DDI1_PAIR5- C30
SDVO1_TVCLKIN-
DDI1_PAIR6+ C15
SDVO1_FLDSTALL+
DDI1_PAIR6- C16
SDVO1_FLDSTALL-
DDI1_HPD
C24
DP1_HPD HDMI1_HPD
DDI1_CTRLCLK_AUX+
D15
SDVO1_CTRLCLK
DP1_AUX+ HDMI1_CTRLCLK
DDI1_CTRLDATA_AUX-
D16
SDVO1_CTRLDATA
DP1_AUX- HDMI1_CTRLDATA
DDI1_DDC_AUX_SEL
D34
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Signal Pin SDVO DP HDMI/DVI
DDI
2
DDI2_PAIR0+ D39 DP2_LANE0+ TMDS2_DATA2+
DDI2_PAIR0- D40 DP2_LANE0- TMDS2_DATA2-
DDI2_PAIR1+ D42 DP2_LANE1+ TMDS2_DATA1+
DDI2_PAIR1- D43 DP2_LANE1- TMDS2_DATA1-
DDI2_PAIR2+ D46 DP2_LANE2+ TMDS2_DATA0+
DDI2_PAIR2- D47 DP2_LANE2- TMDS2_DATA0-
DDI2_PAIR3+ D49 DP2_LANE3+ TMDS2_CLK+
DDI2_PAIR3- D50 DP2_LANE3- TMDS2_CLK-
DDI2_HPD
D44 DP2_HPD HDMI2_HPD
DDI2_CTRLCLK_AUX+
C32 DP2_AUX+ HDMI2_CTRLCLK
DDI2_CTRLDATA_AUX-
C33 DP2_AUX- HDMI2_CTRLDATA
DDI2_DDC_AUX_SEL
C34
DDI
3
DDI3_PAIR0+ C39 DP3_LANE0+ TMDS3_DATA2+
DDI3_PAIR0- C40 DP3_LANE0- TMDS3_DATA2-
DDI3_PAIR1+ C42 DP3_LANE1+ TMDS3_DATA1+
DDI3_PAIR1- C43 DP3_LANE1- TMDS3_DATA1-
DDI3_PAIR2+ C46 DP3_LANE2+ TMDS3_DATA0+
DDI3_PAIR2- C47 DP3_LANE2- TMDS3_DATA0-
DDI3_PAIR3+ C49 DP3_LANE3+ TMDS3_CLK+
DDI3_PAIR3- C50 DP3_LANE3- TMDS3_CLK-
DDI3_HPD
C44 DP3_HPD HDMI3_HPD
DDI3_CTRLCLK_AUX+
C36 DP3_AUX+ HDMI3_CTRLCLK
DDI3_CTRLDATA_AUX-
C37 DP3_AUX- HDMI3_CTRLDATA
DDI3_DDC_AUX_SEL
C38
4.5.3.1 DDI Signals: DisplayPort
DP Signal I/O Description
DP[1:3]_LANE[0:3]+
DP[1:3]_LANE[0:3]-
O
Uni-directional main link for the transport of
isochronous streams and secondary-data
packets
DP[1:3]_AUX+
DP[1:3]_AUX-
I/O
Half-duplex bi-directional AUX channel for
services such as link configuration or
maintenance and EDID access
DP[1:3]_HPD I
Detection of Hot Plug/ Unplug and notification of
the link layer
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4.5.3.2 DDI Signals: SDVO
SDVO Signal I/O Description
SDVO1_RED+
SDVO1_RED-
O
Serial Digital Video red output differential pair
SDVO1_GRN+
SDVO1_GRN-
O
Serial Digital Video green output differential pair
SDVO1_BLU+
SDVO1_BLU-
O
Serial Digital Video blue output differential pair
SDVO1_CK+
SDVO1_CK-
O
Serial Digital Video clock output differential pair
SDVO1_INT+
SDVO1_INT-
I
Serial Digital Video interrupt input differential pair
SDVO1_TVCLKIN+
SDVO1_TVCLKIN-
I
Serial Digital Video TVOUT synchronization
clock input
SDVO1_FLDSTALL+
SDVO1_FLDSTALL-
I
Serial Digital Video Field Stall input differential
pair
SDVO1_CTRLCLK I/O
SDVO I2C clock line – to set up SDVO
peripherals
SDVO1_CTRLDATA I/O
SDVO I2C data line – to set up SDVO
peripherals
4.5.3.3 DDI Signals: HDMI / DVI
The HDMI or DVI supports the resolution up to 1920x1200 at 60Hz.
HDMI Signal I/O Description
TMDS[1:3]_CLK+
TMDS[1:3]_CLK-
O
HDMI/DVI TMDS Clock differential pair
TMDS[1:3]_DATA[0:2]+
TMDS[1:3]_DATA[0:2]-
O
HDMI/DVI TMDS lanes 0, 1 and 2 differential
pairs
HDMI[1:3]_CTRL_CLK I/O
HDMI/DVI I2C control clock
HDMI[1:3]_CTRL_DAT I/O
HDMI/DVI I2C control data
HDMI[1:3]_HPD I
HDMI/DVI Hot-Plug Detect
4.6 USB
USB 2.0
4.6.1
The two EHCI Controllers of Intel® QM77 offer 8 USB ports. Each port
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supports USB 1.1 and 2.0 compliant devices.
Signal I/O Description
USB[0:7]+
USB[0:7]-
I/O
USB differential pairs, channels 0 through 7,
transmit Data/Address/Command signals.
USB_0_1_OC# I
USB over-current sense, USB channels 0 and 1.
A pull-up for this line shall be present on the
Module. An open drain driver from a USB current
monitor on the Carrier Board may drive this line
low. Do not pull this line high on the Carrier
Board.
USB_2_3_OC# I
USB over-current sense, USB channels 2 and 3.
A pull-up for this line shall be present on the
Module. An open drain driver from a USB current
monitor on the Carrier Board may drive this line
low. Do not pull this line high on the Carrier
Board.
USB_4_5_OC# I
USB over-current sense, USB channels 4 and 5.
A pull-up for this line shall be present on the
Module. An open drain driver from a USB current
monitor on the Carrier Board may drive this line
low. Do not pull this line high on the Carrier
Board.
USB_6_7_OC# I
USB over-current sense, USB channels 6 and 7.
A pull-up for this line shall be present on the
Module. An open drain driver from a USB current
monitor on the Carrier Board may drive this line
low. Do not pull this line high on the Carrier
Board.
USB 3.0
4.6.2
There are four USB 3.0 ports.
Signal I/O Description
USB_SSTX[0:3]+
USB_SSTX[0:3]-
O
Additional transmit signal differential pairs for the
SuperSpeed USB data path.
USB_SSRX[0:3]+
USB_SSRX[0:3]-
I
Additional receive signal differential pairs for the
SuperSpeed USB data path.
4.7 SATA
The PCH QM77 provides four Serial ATA (SATA) ports. The Port 0 and 1
support SATA 6 Gb/s, and the other two support up to SATA 3.0 Gb/s device
transfers. This interface may be used for Serial Attached SCSI (SAS).
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Signal I/O Description
SATA0_TX+
SATA0_TX-
O
Serial ATA or SAS Channel 0 transmits
differential pair.
SATA0_RX+
SATA0_RX-
I
Serial ATA or SAS Channel 0 receives
differential pair.
SATA1_TX+
SATA1_TX-
O
Serial ATA or SAS Channel 1 transmits
differential pair.
SATA1_RX+
SATA1_RX-
I
Serial ATA or SAS Channel 1 receives
differential pair.
SATA2_TX+
SATA2_TX-
O
Serial ATA or SAS Channel 2 transmits
differential pair.
SATA2_RX+
SATA2_RX-
I
Serial ATA or SAS Channel 2 receives
differential pair.
SATA3_TX+
SATA3_TX-
O
Serial ATA or SAS Channel 3 transmits
differential pair.
SATA3_RX+
SATA3_RX-
I
Serial ATA or SAS Channel 3 receives
differential pair.
(S)ATA_ACT# I/O
ATA (parallel and serial) or SAS activity
indicator, active low.
4.8 PCI Express
PCI Express x1
4.8.1
There are eight one-lane PCI Express ports available in the PCH QM77. The
ports are compliant to the PCI Express 2.0 specification running at 5.0 GT/z.
Port 7 is occupied by GbE, so 7 PCIe x1 Ports, 0~6, are left on the COM™
Express connector.
Signal I/O Description
PCIE_TX[0:3]+
PCIE_TX[0:3]-
O
PCI Express Differential transmit Pairs 0 through
3
PCIE_RX[0:3]+
PCIE_RX[0:3]-
I
PCI Express Differential receive Pairs 0 through
3
PCIE_TX[4:6]+
PCIE_TX[4:6]-
O
PCI Express Differential transmit Pairs 4 through
6
PCIE_RX[4:6]+
PCIE_RX[4:6]-
I
PCI Express Differential receive Pairs 4 through
6
PCIE_CLK_REF0+
PCIE_CLK_REF0-
O
Reference clock output for all PCI Express and
PCI Express Graphics lanes
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PCI Express x16
4.8.2
The processor contains one PCI Express controller that supports one external
x16 PCI Express Graphics port. This port can also operate at Gen 2 speed,
5.0GT/s.
Signal I/O Description
PEG_TX[0:15]+
PEG_TX[0:15]-
O
PCI Express Differential transmit Pairs 0 through
15
PEG_RX[0:15]+
PEG_RX[0:15]-
I
PCI Express Differential receive Pairs 0 through
15
PEG_LANE_RV# I
PCI Express Graphics lane reversal input strap.
Pull low on the Carrier Board to reverse lane
order.
4.9 High Definition Audio
The High Definition Audio (HDA) controller is integrated with PCH QM77. It
communicates with the external codec(s) over the Intel® High Definition Audio
serial link. The controller consists of a set of DMA engines that are used to
move samples of digitally encoded data between system memory and an
external codec(s). The PCH implements a single Serial Data Output signal
(HDA_SDOUT) that is connected to all external codecs. Three Serial Digital
Input signals (HDA_SDIN[0:02] provided by the PCH support up to three
codecs.
Signal I/O Description
AC/HDA_RST# O
Reset output to CODEC, active low
AC/HDA_SYNC O
Sample-synchronization signal to the CODEC(s)
AC/HDA_BITCLK I/O
Serial data clock generated by the external
CODEC(s)
AC/HDA_SDOUT O
Serial TDM data output to the CODEC
AC/HDA_SDIN[0:2] I/O
Serial TDM data input from up to 3 CODECs
4.10 Ethernet
The QM77 integrates a Gigabit Ethernet (GbE) controller. The controller with
Intel® 82579LM LAN PHY provides 10/100/1000Mb/s interface. The Intel®
82579 is connected to Port 7 of the PCIe x1 in the PCH. Gigabit transformer
has to be designed on the Carrier Board.
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The integrated GbE controller contains power management registers for PCI,
so it supports the Advanced Configuration and Power Interface (ACPI)
specification. This enables the network-related activity (using an internal host
wake signal) to wake up the host.
Signal I/O Description
GBE0_MDI[0:3]+
GBE0_MDI[0:3]-
I/O
Gigabit Ethernet Controller 0: Media Dependent
Interface Differential Pairs 0, 1, 2, 3. The MDI
can operate in 1000, 100 and 10 Mbit/sec
modes. Some pairs are unused in some modes,
per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/MDI[3]+/- B1_DD+/-
GBE0_ACT# OD
Gigabit Ethernet Controller 0 activity indicator,
active low
GBE0_LINK# OD
Gigabit Ethernet Controller 0 link indicator, active
low
GBE0_LINK100# OD
Gigabit Ethernet Controller 0 100 Mbit/sec link
indicator, active low
GBE0_LINK1000# OD
Gigabit Ethernet Controller 0 1000 Mbit/sec link
indicator, active low
GBE0_CTREF REF
Reference voltage for Carrier Board Ethernet
channel 0 magnetics center tap. The reference
voltage is 3.3V.
4.11 LPC
The LPC interface provides legacy I/O support on a Carrier Board via a Super
I/O and system management devices.
Signal I/O Description
LPC_AD[0:3] I/O
LPC multiplexed address, command and data
bus
LPC_FRAME# O
LPC frame indicates the start of an LPC cycle
LPC_DRQ[0:1]# I
LPC serial DMA request
LPC_SERIRQ I/O
LPC serial interrupt
LPC_CLK O
LPC clock output-33MHz nominal
4.12 SPI
The Serial Peripheral Interface (SPI) is a 4-pin interface that supports
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SPI-compatible flash devices. The SPI flash device can be up to 16MB
(128Mb). The SPI bus is clocked at either 20MHz, 25MHz, 33MHz or 50 MHz.
SPI devices selected should support one of these frequencies.
Signal I/O Description
SPI_CS# O
Chip select for Carrier Board SPI - may be
sourced from chipset SPI0 or SPI1
SPI_MISO I
Data in to Module from Carrier SPI
SPI_MISI O
Data out from Module to Carrier SPI
SPI_CLK O
Clock from Module to Carrier SPI
SPI_POWER O
Power supply for Carrier Board SPI – sourced
from Module – nominally 3.3V. The Module shall
provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100ma of
SPI_POWER. SPI_POWER shall only be used
to power SPI devices on the Carrier Board.
BIOS_DIS[0:1]# I
Selection straps to determine the BIOS boot
device. The Carrier should only float these or pull
them low, please refer to the table below for
strapping option of BIOS disable signals.
BIOS_DIS1# BIOS_DIS0#
Chipset
SPI CS1#
Destination
Chipset
SPI CS0#
Destination
Carrier
SPI_CS#
SPI
Descriptor
BIOS
Entry
Ref
Line
1 1 Module Module High
Module SPI0/SPI1 0
1 0 Module Module High
Module Carrier FWH 1
0 1 Module Carrier SPI0
Carrier SPI0/SPI1 2
0 0 Carrier Module SPI1
Module SPI1/SPI1 3
4.13 SMBus
The SMBus port is specified for system management functions. It is used on
the Module to manage system function such as reading the DRAM SPD
EEPROM and setting clock synthesizer parameters. If the SMBus is used on
the baseboard, then great care must be taken that no conflicts with the
on-Module SMBus devices occur. It may be useful for implementation on the
Carrier Board of standards such as Smart Battery. The maximum capacitance
on the Carrier Board shall not exceed 100pF.
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Signal I/O Description
SMB_CK I/O
System Management Bus bidirectional clock line
SMB_DAT I/O
System Management Bus bidirectional data line
SMB_ALERT# I
System Management Bus Alert – active low input
can be used to generate an SMI# (System
Management Interrupt) or to wake the system.
4.14 ExpressCard
ExpressCard is a small form factor expansion card that uses PCI Express or
USB as the interface. It is similar in concept and scope to CardBus. The
CT-CIB61 supports two Express Card interface.
Signal I/O Description
EXCD[0:1]_CPPE# I
PCI ExpressCard: PCI Express capable card
request, active low, one per card
EXCD[0:1]_PERST# O
PCI ExpressCard: reset, active low, one per card
4.15 General Purpose Input Output
GPI and GPO pins may be implemented as GPIO (Module specific). GPI and
GPO pins may be implemented as SDIO.
Signal I/O Description
GPO[0:3] O
General purpose output pins. Upon a hardware
reset, these outputs should be low
GPI[0:3] I
General purpose input pins. Pulled high
internally on the Module.
GPIO Configuration
4.15.1
Output Pin default setting is HIGH.
Pin # GPIO# Default Configuration
B63 GPIO7 GPO3
B57 GPIO6 GPO2
B54 GPIO5 GPO1
A93 GPIO4 GPO0
A85 GPIO3 GPI3
A67 GPIO2 GPI2
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Pin # GPIO# Default Configuration
A63 GPIO1 GPI1
A54 GPIO0 GPI0
The GPIO function, provided by Intel Panther IC, can be accessed through
GPIO Base Address Register (GPIOBASE). The configuration on CT-CIB61 is
described as below.
Register Address
GPIO Base Address 0x500
The general I/O read/write function is used to access and configure the
Panther Point. Through the I/O read or write command, the current status of
GPIO can configure each pin to input or output.
Registers Description
4.15.2
4.15.2.1 GPIO Use Select
4.15.2.1.1 GPIO Use Select Register 1
(Offset GPIOBASE+0x00)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset GPIOBASE+0x02)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3 GPIO2 GPIO1
4.15.2.1.2 GPIO Use Select Register 2
(Offset GPIOBASE+0x30)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5
Note:
Bit X = 0 means Native Function
Bit X = 1 means GPIO Function
4.15.2.2 GPIO Input/Output Select
4.15.2.2.1 GPIO Input/Output Select Register 1
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(Offset GPIOBASE+0x04)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset GPIOBASE+0x06)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3
GPIO2 GPIO1
4.15.2.2.2 GPIO Input/Output Select Register 2
(Offset GPIOBASE+0x34)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5
Note:
Bit X = 0 means Output Pin
Bit X = 1 means Input Pin
4.15.2.3 GPIO Level for Input or Output
If Pin X configures as output pin, users can decide its output value (0 or 1).
If it is programmed as an input, this register reflects the state of the input
signal.
4.15.2.3.1 GPIO Level for Input or Output Register 1
(Offset GPIOBASE+0x0C)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset GPIOBASE+0x0E)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3
GPIO2 GPIO1
4.15.2.3.2 GPIO Level for Input or Output Register 2
(Offset GPIOBASE+0x38)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5
4.15.2.4 GPIO Signal Invert Register
This will invert the polarity of the Input Port register data.
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(Offset GPIOBASE+0x2C)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset GPIOBASE+0x2E)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3
GPIO2 GPIO1
Note:
Bit X = 0 means Polarity is retained
Bit X = 1 means Polarity is inverted
The GPIO4~GPIO7 can’t be set to inverted.
PSUEDO CODE
4.15.3
4.15.3.1 Example 1: Change GPIO2 from input to output
Step1: ByteData = ReadIOByte(0x506) //Read current setting from
configuration
//Register
Step2: ByteData = ByteData | 0xFD //Set Bit1 to 0. It means output
Step3: WriteIOByte(0x506, ByteData) //Write back to configuration register
4.15.3.2 Example2 Set GPIO7 to output LOW
Step1: ByteData = ReadIOByte(0x538) //Read current setting from Output Port
//Register
Step2: ByteData =ByteData & 0xEF //Set Bit4 to 0. It means output low
Step3: WriteIOByte(0x538, ByteData) //Write back to Output Port Register
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4.16 Watchdog Timer
Board Design
4.16.1
The WDT (Watchdog Timer) is implemented by using Fintek F81801.
Register Address
WDT Base 0xA00
PSUEDO CODE
4.16.2
4.16.2.1 Set WDT Time Unit (Second Unit)
Step1: ByteData = ReadIOByte(0xA05) //Read current setting
Step2: ByteData = ByteData & 0xF7 //Set time unit to “second”
Step3: WriteIOByte(0xA05, ByteData) //Write back
.
4.16.2.2 Set WDT Time Value
Step1: WriteIOByte(0xA06, Time) //Set watch dog time value
4.16.2.3 Enable WDT
Step1: ByteData = ReadIOByte(0xA05) //Read current setting
Step2: ByteData = ByteData | 0x20 //Enable WDT
Step3: WriteIOByte(0xA05, ByteData) //Write back
Enable TCO Timer Reboot Function
Set Initial Value into Timer Register
Reload Timer Value into Register
Start to Count
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4.17 Power and System Management Signals
Signal I/O Description
SUS_S3# O
Indicates system is suspended to RAM state.
Active low output.
SUS_S4# O
Indicates system is suspended to Disk state.
Active low output.
SUS_S5# O
Indicates system is in Soft Off state.
SUS_STAT# O
Indicates imminent suspend operation.
PWRBTN# I
Power button to bring system out of S5 (soft off),
active on rising edge.
PWR_OK I
Power OK from main power supply
BATLOW# I
Indicates that external battery is low.
SYS_RESET# I
Reset button input. Active low input.
CB_RESET# O
Carrier Board Reset. Active low input.
WAKE0# I
PCI Express wake up signal.
WAKE1# I
General purpose wake up signal.
VCC_RTC I
RTC External Battery
LID# I
LID switch
SLEEP# I
Sleep Button
FAN_PWMOUT O
FAN PWM out
FAN_TACHIN I
Fan Tacho in
4.18 Thermal Management Signals
Signal I/O Description
THRMTRIP# O
Active low output indicating that the CPU has
entered thermal shutdown.
THRM# I
Input from off-module temp sensor indicating and
over-temp situation.
4.19 Miscellaneous Signals
Signal I/O Description
I2C_CK O
General purpose I2C port clock output
I2C_DAT I/O
General purpose I2C port data I/O lin
WDT O
Indicator for Watchdog Timeout
SPKR O
Output for audio enunciator-the “speaker” in
PC-AT systems
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V. SYSTEM BIOS
The system BIOS software is stored on EEPROM. The BIOS provides an
interface to modify the configuration. When the battery is removed, all the
parameters will be reset.
Turn on the computer and press <DEL> or <F2> to enter the setup screens.
5.1 Main
The Main setup screen is showed as following when the setup utility is entered.
System Date/Time is set up in the Main Menu.
System Date: MM/DD/YYYY
System Time: HH:MM:SS
Use Tab to switch between Date and Time elements.
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5.2 Advanced
Launch PXE OpROM : Enable or Disable Boot Option for Legacy Network
Devices.
AMT Configuration: Enable/Disable Intel® Active Management Technology
BIOS Extension. Note: iAMT H/W is always enabled. This option just controls
the BIOS extension execution. If enabled, this requires additional firmware in
the SPI device.
Intel(R) Smart Connect Technology : Enable or Disable ISCT
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ACPI Settings
5.2.1
Enables or disables BIOS ACPI Auto Configuration.
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Trusted Computing
5.2.2
Security Device Support enables or disables BIOS support for security
device. O.S. will not show Security Device. TCG EFI protocol and INT1A
interface will not be available.
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CPU Configuration
5.2.1
Hyper-threading: Enabled for Windows XP and Linux (OS optimized for
Hyper-Threading Technology) and disabled for other OS (OS not optimized for
Hyper-Threading Technology). When disabled, only one thread per enabled
core is enabled.
Limit CPUID Maximum: Disabled for Windows XP.
Execute Disable Bit: XP can prevent certain classes of malicious buffer
overflow attacks when combined with a supporting OS (Windows Server 2003
SP1, Windows XP SP2, SusE Linux 9.2, RedHat Enterprise 3 Update 3.)
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SATA Configuration
5.2.2
The BIOS automatically detects the presence of SATA device and the
hardware installed in the SATA ports will be showed in the configuration. Each
port can be enabled or disabled individually.
Hot Plug: Designates this port as Hot Pluggable.
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USB Configuration
5.2.3
Legacy USB Support: AUTO option disables legacy support if no USB
devices are connected. DISABLE option will keep USB devices available only
for EFI applications.
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W83627DHG Super IO Configuration
5.2.4
Two serial ports could be configured.
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5.2.4.1 Serial Port 1 Configuration
Each serial port could be enabled or disabled.
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W83627DHG H/W Monitor
5.2.5
Smart Fan Configuration: Select CPU Smart Fan 0 Mode
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F81801 Super IO Configuration
5.2.6
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5.2.6.1 Serial Port 0 Configuration
Each serial port could be enabled or disabled.
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F81801 H/W Monitor
5.2.7
Smart Fan Configuration: Select CPU Smart Fan 0 Mode
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Serial Port Console Redirection
5.2.8
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CPU PPM Configuration
5.2.9
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5.3 Chipset
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PCH-IO Configuration
5.3.1
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5.3.1.1 PCI Express Configuration
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5.3.1.1.1 PCI Express Root Port
Each PCI Express Root Port can be enabled or disabled individually.
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5.3.1.2 USB Configuration
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5.3.1.3 PCH Azalia Configuration
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System Agent Configuration
5.3.2
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5.3.2.1 Graphics Configuration
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5.3.2.1.1 LCD Control
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5.3.2.2 NB PCIe Configuration
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5.3.2.3 Memory Configuration
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5.4 Boot
Boot Configuration: Number of seconds to wait for setup activation key.
65535 (0xFFFF) means indefinite waiting.
Bootup NumLock State: Select [Enable] or [Disable] for the keyboard
NumLock state.
Quiet Boot: Enables or disables Quiet Boot option.
Boot Option #1: Set the system boot order.
Hard Drive BBS Priorities: Set the order of the legacy devices in this group.
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CSM16 Parameters
5.4.1
OpROM execution, boot options filter, etc.
GateA20 Active:
[Upon Request] – GA20 can be disabled using BIOS services.
[Always] – do not allow disabling GA20; this option is useful wen any RT
code is executed above 1MB.
Option ROM Message: Set display mode [Force BIOS] or [Keep Current] for
Option ROM.
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CSM Parameters
5.4.2
OpROM execution, boot options filter, etc.
Launch CSM: This option controls if CSM will be launched always or never.
Boot option filer: This option controls what devices system can boot to [UEFI
and Legacy], [Legacy only] or [UEFI only].
Launch PXE OpROM policy: This controls the execution of UEFI and Legacy
PXE OpROM, [Do not launch], [UEFI only] or [Legacy only].
Launch Storage OpROM policy: This controls the execution of UEFI and
Legacy Storage OpROM, [Do not launch], [UEFI only] or [Legacy only].
Launch Video OpROM policy: This controls the execution of UEFI and
Legacy Video OpROM, [Do not launch], [UEFI only] or [Legacy only].
Other PCI device ROM priority: For PCI devices other than Network, Mass
storage or Video defines which OpROM to launch, [UEFI OpROM] or [Legacy
OpROM].
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5.5 Security
Administrator’s and User’s passwords could be set.
If ONLY the Administrator’s password is set, then this only limits access to
Setup and is only asked for when entering Setup. If ONLY the User’s password
is set, then this is a power on password and must be entered to boot or enter
Setup. In Setup, the user will have administrator rights. The minimum length of
the password is 3 and the maximum length is 20.
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5.6 Save and Exit
Save Changes and Exit: Exit system setup after saving the changes.
Discard Changes and Exit: Exit system setup without saving any changes.
Save Changes and Reset: Reset the system after saving the changes.
Discard Changes and Reset: Reset system setup without saving any
changes.
Save Changes: Save Changes done so far to any of the setup options.
Discard Changes: Discard Changes done so far to any of the setup options.
Restore Defaults: Restore/Load Default values for all the setup options.
Save as User Defaults: Save the changes done so far as user Defaults.
Restore user Defaults: Restore the User Defaults to all the setup options.
Launch EFI Shell from filesystem device: Attempts to Launch EFI Shell
application (Shellx64.efi) from one of the available filesystem devices.
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VI. Address Map
6.1 I/O Port Address Map
The assignment of the I/O port addresses for the CT-CIB61 with CT-BT601
baseboard under Windows® 7 Ultimate/64bit are shown below.
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6.2 Interrupt Controller (IRQ) Map
The interrupt controller map for the CT-CIB61 with the CT-BT601 baseboard
under Windows® 7 Ultimate/64bit are as shown below.
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6.3 Memory Map
The memory map of DRAM for the CT-CIB61 with CT-BT601 baseboard under
Windows® 7 Ultimate/64bit are shown below.
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VII. Electrical Specification
7.1 Input Power
The baseboard for the CT-CIB61 shall supply a single main power rail with a
nominal value of +12V and two additional rails, a +5V standby power and +3V
RTC power.
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