Datasheet CAT93C86U-TE13, CAT93C86U-1.8TE13, CAT93C86SI-TE13, CAT93C86SI-1.8TE13, CAT93C86SA-TE13 Datasheet (CTLST)
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CAT93C46/56/57/66/86
8
7
6
5
V
CC
ORG
GND
DI
CS
SK
DO
1
2
3
4
NC (PE*)
1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
FEATURES
■ High Speed Operation:
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
■ Low Power CMOS Technology
■ 1.8 to 6.0 Volt Operation
■ Selectable x8 or x16 Memory Organization
■ Self-Timed Write Cycle with Auto-Clear
■ Hardware and Software Write Protection
DESCRIPTION
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial E2PROM memory devices which are configured
as either registers of 16 bits (ORG pin at VCC) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
PIN CONFIGURATION
DIP Package (P)
1
CS
SK
DI
DO
8
2
3
4
V
7
NC (PE*)
6
ORG
5
GND
CC
SOIC Package (J)
1
NC (PE*)
V
CC
CS
SK
8
2
7
3
6
4
5
SOIC Package (S)
ORG
CS
GND
SK
DO
DI
DI
DO
1
2
3
4
■ Power-Up Inadvertant Write Protection
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ Commercial, Industrial and Automotive
Temperature Ranges
■ Sequential Read (except 93C46)
■ Program Enable (PE) Pin (93C86 only)
CMOS E2PROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
SOIC Package (K)
8
V
CC
7
NC (PE*) NC (PE*)
6
ORG
5
GND
CS
SK
DO
1
2
3
DI
4
8
V
CC
7
6
ORG
5
GND
TSSOP Package (U)
*Only For 93C86
PIN FUNCTIONS
93C46/56/57/66/86
F01
BLOCK DIAGRAM
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
ORG
DO Serial Data Output
V
CC
+1.8 to 6.0V Power Supply
GND Ground
ORG Memory Organization
NC No Connection
PE* Program Enable
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
DI
CS
PE*
SK
V
CC
GND
MEMORY ARRA Y
ORGANIZATION
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
ADDRESS
DECODER
OUTPUT
BUFFER
DO
93C46/56/57/66/86 F02
Doc. No. 25056-00 2/98 M-1
93C46/56/57/66/86
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(1)
............ –2.0V to +VCC +2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
(3)
N
T
V
I
END
DR
ZAP
LTH
(3)
(3)
(3)(4)
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
Power Supply Current 3 mA fSK = 1MHz
(Operating Write) VCC = 5.0V
Power Supply Current 500 µAfSK = 1MHz
(Operating Read) VCC = 5.0V
Power Supply Current 10 µA CS = 0V
(Standby) (x8 Mode) ORG=GND
Power Supply Current 0 µA CS=0V
(Standby) (x16Mode) ORG=Float or V
Input Leakage Current 1 µAVIN = 0V to V
Output Leakage Current 1 µAV
= 0V to VCC,
OUT
CC
(Including ORG pin) CS = 0V
Input Low Voltage -0.1 0.8 4.5V≤VCC<5.5V
Input High Voltage 2 VCC+1
Input Low Voltage 0 VCCX0.2 1.8V≤VCC<2.7V
Input High Voltage VCCX0.7 VCC+1
Output Low Voltage 0.4 4.5V≤VCC<5.5V
Output High Voltage 2.4 IOL = 2.1mA
V
V
V
V
V
V
IOH = -400µA
Output Low Voltage 0.2 1.8V≤VCC<2.7V
Output High Voltage VCC-0.2 IOL = 1mA
V
IOH = -100µA
I
I
CC1
I
CC2
I
SB1
SB2
I
LI
I
LO
V
V
V
V
V
V
V
V
(5)
IL1
IH1
IL2
IH2
OL1
OH1
OL2
OH2
CC
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB2)=0µA (<900nA) for 93C46/56/57/66, (ISB2)=2µA for 93C86.
Doc. No. 25056-00 2/98 M-1
2
93C46/56/57/66/86
PIN CAPACITANCE
Symbol Test Max. Units Conditions
(3)
C
OUT
C
IN
INSTRUCTION SET
Instruction Device Start Opcode Address Data Comments PE
OUTPUT CAPACITANCE (DO) 5 pF V
(3)
INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF VIN=OV
Type Bit x8 x16 x8 x16
OUT
=OV
(2)
READ 93C46 1 10 A6-A0 A5-A0 Read Address AN–A0
93C56
(1)
1 10 A8-A0 A7-A0
93C66 1 10 A8-A0 A7-A0
93C57 1 10 A7-A0 A6-A0
93C86 1 10 A10-A0 A9-A0 X
ERASE 93C46 1 11 A6-A0 A5-A0 Clear Address AN–A0
93C56
(1)
1 11 A8-A0 A7-A0
93C66 1 11 A8-A0 A7-A0
93C57 1 11 A7-A0 A6-A0
93C86 1 11 A10-A0 A9-A0 I
WRITE 93C46 1 01 A6-A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0
93C56
(1)
1 01 A8-A0 A7-A0 D7-D0 D15-D0
93C66 1 01 A8-A0 A7-A0 D7-D0 D15-D0
93C57 1 01 A7-A0 A6-A0 D7-D0 D15-D0
93C86 1 01 A10-A0 A9-A0 D7-D0 D15-D0 I
EWEN 93C46 1 00
93C56 1 00
93C66 1 00
93C57 1 00
93C86 1 00
EWDS 93C46 1 00
93C56 1 00
93C66 1 00
93C57 1 00
93C86 1 00
11XXXXX 11XXXX
11XXXXXXX 11XXXXXX
11XXXXXXX 11XXXXXX
11XXXXXX 11XXXXX
11XXXXXXXXX 11XXXXXXXX
00XXXXX 00XXXX
00XXXXXXX 00XXXXXX
00XXXXXXX 00XXXXXX
00XXXXXX 00XXXXX
00XXXXXXXXX 00XXXXXXXX
Write Enable
Write Disable
X
X
ERAL 93C46 1 00
93C56 1 00
93C66 1 00
93C57 1 00
93C86 1 00
WRAL 93C46 1 00
93C56 1 00
93C66 1 00
93C57 1 00
93C86 1 00
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) Applicable only to 93C86
(3) This parameter is tested initially and after a design or process change that affects the parameter.
10XXXXX 10XXXX
10XXXXXXX 10XXXXXX
10XXXXXXX 10XXXXXX
10XXXXXX 10XXXXX
10XXXXXXXXX 10XXXXXXXX
01XXXXX 01XXXX
01XXXXXXX 01XXXXXX
01XXXXXXX 01XXXXXX
01XXXXXX 01XXXXX
01XXXXXXXXX 01XXXXXXXX
3
Clear All Addresses
D7-D0 D15-D0 Write All Addresses
D7-D0 D15-D0
D7-D0 D15-D0
D7-D0 D15-D0
D7-D0 D15-D0 I
Doc. No. 25056-00 2/98 M-1
I
93C46/56/57/66/86
A.C. CHARACTERISTICS (93C46/56/57/66)
Limits
VCC =V
1.8V-6V* 2.5V-6V 4.5V-5.5V Test
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions
=V
CC
CC
=
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
(1)
t
HZ
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
* Preliminary data for 93C56/57/66
CS Setup Time 200 100 50 ns
CS Hold Time 0 0 0 ns VIL = 0.45V
DI Setup Time 400 200 100 ns VIH = 2.4V
DI Hold Time 400 200 100 ns CL = 100pF
Output Delay to 1 1 0.5 0.25 µsVOL = 0.8V
Output Delay to 0 1 0.5 0.25 µsVOH = 2.0v
CL = 100pF
Output Delay to High-Z 400 200 100 ns
Program/Erase Pulse Width 10 10 10 ms
Minimum CS Low Time 1 0.5 0.25 µs
Minimum SK High Time 1 0.5 0.25 µs
Minimum SK Low Time 1 0.5 0.25 µs
Output Delay to Status Valid 1 0.5 0.25 µsCL = 100pF
Maximum Clock Frequency DC 250 DC 500 DC 1000 KHZ
A.C. CHARACTERISTICS (93C86)
Limits
VCC =V
=V
CC
CC
=
1.8V-6V* 2.5V-6V 4.5V-5.5V Test
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
(1)
t
HZ
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25056-00 2/98 M-1
CS Setup Time 200 150 50 ns
CS Hold Time 0 0 0 ns VIL = 0.45V
DI Setup Time 400 250 50 ns VIH = 2.4V
DI Hold Time 400 250 50 ns CL = 100pF
Output Delay to 1 1 0.5 0.1 µsVOL = 0.8V
Output Delay to 0 1 0.5 0.1 µsVOH = 2.0v
Output Delay to High-Z 400 200 100 ns
Program/Erase Pulse Width 5 5 5 ms
Minimum CS Low Time 1 0.5 0.1 µs
Minimum SK High Time 1 0.5 0.1 µs
Minimum SK Low Time 1 0.5 0.1 µs
Output Delay to Status Valid 1 0.5 0.1 µsCL = 100pF
Maximum Clock Frequency DC 250 DC 1000 DC 3000 KHZ
4
CL = 100pF
DEVICE OPERATION
93C46/56/57/66/86
The CAT93C46/56(57)66/86 is a 1024/2048/4096/
16,384-bit nonvolatile memory intended for use with
industry standard microprocessors. The CAT93C46/56/
57/66/86 can be organized as either registers of 16 bits
or 8 bits. When organized as X16, seven 9-bit instructions for 93C46; seven 10-bit instructions for 93C57;
seven 11-bit instructions for 93C56 and 93C66; seven
13-bit instructions for 93C86; control the reading, writing
and erase operations of the device. When organized as
X8, seven 10-bit instructions for 93C46; seven 11-bit
instructions for 93C57; seven 12-bit instructions for
93C56 and 93C66: seven 14-bit instructions for 93C86;
control the reading, writing and erase operations of the
device. The CAT93C46/56/57/66/86 operates on a single
power supply and will generate on chip, the high voltage
required during any write operation.
Instructions, addresses, and write data are clocked into
Figure 1. Sychronous Data Timing
t
SKHI
SK
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
t
SKLOW
t
CSH
t
DIS
DI
CS
DO
t
CSS
VALID VALID
Figure 2a. Read Instruction Timing (93C46)
SK
CS
ANA
N–1
DI
11 0
t
DIS
A
t
DIH
t
PD0,tPD1
DA TA VALID
0
t
CSMIN
STANDBY
93C46/56/57/66/86 F03
t
CS
DO
t
PD0
t
HZ
0
DND
N–1
D1D
0
5
HIGH-ZHIGH-Z
93C46/56/57/66/86 F04
Doc. No. 25056-00 2/98 M-1
93C46/56/57/66/86
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/
/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organizations).
Note: This note is applicable only to 93C86. The Write,
Erase, Write all and Erase all instructions require PE=1.
If PE is left floating, 93C86 is in Program Enabled mode.
For Write Enable and Write Disable instruction PE=don’t
care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46/
56/57/66/86 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t
PD0
or t
PD1
)
For the 93C56/57/66/86, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will automatically
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ
mode, only the initial data word is preceeded by a
dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
. The falling edge of CS will start the
CSMIN
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46/56/57/66/86 can be determined by selecting
the device and polling the DO pin. Since this device
features Auto-Clear before write, it is NOT necessary to
erase a memory location before it is written into.
Figure 2b. Read Instruction Timing (93C56/57/66/86)
SK
CS
DI
DO
111 111111111111
11 0
HIGH-Z
ANA
N–1
Dummy 0
A
0
Figure 3. Write Instruction Timing
SK
CS
ANA
N-1
DI
101
A
0
D
15 . . . D0
or
D
7 . . . D0
D
N
Don't Care
Address + 1
D
15 . . . D0
or
D
7 . . . D0
D
0
Address + 2
D
15 . . . D0
or
D
7 . . . D0
t
CS
STATUS
VERIFY
Address + n
D
15 . . .
or
D
7 . . .
STANDBY
DO
Doc. No. 25056-00 2/98 M-1
HIGH-Z
t
SV
t
BUSY
READY
EW
t
HZ
HIGH-Z
93C46/56/57/66/86 F05
6
93C46/56/57/66/86
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
. The falling edge of CS will start the self clocking
CSMIN
clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Once cleared,
the content of a cleared location returns to a logical “1”
state.
Erase/Write Enable and Disable
The CAT93C46/56/57/66/86 powers up in the write
disable state. Any writing after power-up or after an
EWDS (write disable) instruction must first be preceded
by the EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C46/56/57/66/86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of t
CSMIN
The falling edge of CS will start the self clocking clear
cycle of all memory locations in the device. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Once cleared,
the contents of all memory bits return to a logical “1”
state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46/56/57/66/86 can be determined
by selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
.
Figure 4. Erase Instruction Timing
SK
CS
A
N
DO
DI
11
1
A
N-1
HIGH-Z
STATUS VERIFY
t
A
0
t
SV
CS
BUSY READY
t
EW
STANDBY
t
HZ
HIGH-Z
93C46/56/57/66/86 F06
7
Doc. No. 25056-00 2/98 M-1
93C46/56/57/66/86
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
DI
10
0
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
DI
DO
10 1
00
HIGH-Z
STANDBY
*
93C46/56/57/66/86 F07
STANDBY
t
HZ
HIGH-Z
t
SV
STATUS VERIFY
t
CS
BUSY READY
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
DI
DO
Doc. No. 25056-00 2/98 M-1
10 1
00
93C46/56/57/66/86 F08
STATUS VERIFY
t
CS
D
N
D
0
t
SV
BUSY READ Y
t
EW
STANDBY
t
HZ
HIGH-Z
93C46/56/57/66/86 F09
8
ORDERING INFORMATION
Prefix Device # Suffix
93C46/56/57/66/86
CAT
Optional
Company ID
93C46
Product
Number
93C46: 1K
93C56: 2K
S
I
Temperature Range
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
-1.8
TE13
Tape & Reel
TE13: 2000/Reel
93C57: 2K
93C66: 4K
93C86: 16K
Package
P = PDIP
S = SOIC (JEDEC)
Operating V oltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
J = SOIC (JEDEC)
K = SOIC (EIAJ)
U = TSSOP
* -40˚ to +125˚C is available upon request
93C46/56/57/66/86 F10
Notes:
(1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
9
Doc. No. 25056-00 2/98 M-1
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