Datasheet CAT28LV64T13I-35T, CAT28LV64T13I-30T, CAT28LV64T13I-25T, CAT28LV64T13A-35T, CAT28LV64T13A-30T Datasheet (CTLST)
...
Preliminary
CAT28LV64
64K-Bit CMOS PARALLEL E2PROM
FEATURES
■ 3.0V to 3.6 V Supply
■ Read Access Times:
– 250/300/350ns
■ Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 µA Max.
■ Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
■ Fast Write Cycle Time:
– 5ms Max.
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel E2PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the selftimed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
■ CMOS and TTL Compatible I/O
■ Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
■ End of Write Detection:
– Toggle Bit
DATADATA
–
DATA Polling
DATADATA
■ Hardware and Software Write Protection
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
The CAT28LV64 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages.
BLOCK DIAGRAM
A5–A
12
V
CC
CE
OE
WE
A0–A
4
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
1
8,192 x 8
2
E
PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O
7
5094 FHD F02
Doc. No. 25035-00 2/98
CAT28LV64
I/O
2
V
SS
I/O
6
I/O
5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A
1
A
0
I/O
0
I/O
1
OE
A
10
CE
I/O
7
A
5
A
4
A
3
A
2
5
6
7
8
1
2
3
4
NC
A
12
A
7
A
6
A
9
A
11
28
27
26
25
V
CC
WE
NC
A
8
I/O
4
I/O
3
16
15
PIN CONFIGURATION
Preliminary
I/O
A
A
A
A
A
A
A
NC
NC
A
I/O
I/O
I/O
V
PLCC Package (N)
A7A12NCNCVCCWE
4321323130
5
6
6
5
7
4
8
3
9
2
10
1
11
0
12
13
0
14 15 16 17 18 19 20
I/O1I/O
DIP Package (P)
1
28
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
I/O3I/O4I/O
27
26
25
24
23
22
21
20
19
18
17
16
15
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
1
2
SS
TOP VIEW
2
SS
V
NC
29
28
27
26
25
24
23
22
21
5
V
WE
NC
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
8
9
11
10
7
6
5
4
3
A
A
A
NC
OE
A
CE
I/O
I/O
8
9
11
10
7
6
5094 FHD F01
V
A
OE
A
A
A
NC
WE
CC
NC
12
A
A
A
A
A
SOIC Package (J, K)
TSOP Top View (8mm x 13.4mm) (T13)
28
1
2
11
3
9
4
8
5
6
7
8
9
10
7
11
6
12
5
13
4
14
3
27
26
25
24
23
22
21
20
19
18
17
16
15
28LV64 F03
A
10
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
0
A
1
A
2
7
6
5
4
3
2
1
0
PIN FUNCTIONS
Pin Name Function Pin Name Function
A0–A
12
I/O0–I/O
CE Chip Enable V
OE Output Enable NC No Connect
Doc. No. 25035-00 2/98
7
Address Inputs WE Write Enable
Data Inputs/Outputs V
CC
SS
2
3.0 to 3.6 V Supply
Ground
Preliminary
CAT28LV64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(2)
........... –2.0V to +VCC + 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
N
T
V
I
LTH
END
DR
ZAP
(1)
(1)
(1)
(1)(4)
Endurance 10
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17
5
Cycles/Byte MIL-STD-883, Test Method 1033
MODE SELECTION
Mode
CECE
CE
CECE
Read L H L D
Byte Write (WE Controlled) L H D
Byte Write (CE Controlled) L H D
WEWE
WE
WEWE
OEOE
OE I/O Power
OEOE
OUT
IN
IN
ACTIVE
ACTIVE
ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Test Max. Units Conditions
(1)
C
I/O
(1)
C
IN
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
Input/Output Capacitance 10 pF V
I/O
= 0V
Input Capacitance 6 pF VIN = 0V
3
Doc. No. 25035-00 2/98
CAT28LV64
Preliminary
D.C. OPERATING CHARACTERISTICS
Vcc = 3.0V to 3.6V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
VCC Current (Operating, TTL) 8 mA CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
(3)
I
SBC
VCC Current (Standby, CMOS) 100 µA CE = V
IHC
,
All I/O’s Open
I
LI
I
LO
(3)
V
IH
V
IL
V
OH
V
OL
V
WI
Input Leakage Current –1 1 µAVIN = GND to V
Output Leakage Current –5 5 µAV
= GND to VCC,
OUT
CE = V
IH
High Level Input Voltage 2 VCC +0.3 V
Low Level Input Voltage –0.3 0.6 V
High Level Output Voltage 2 V IOH = –100µA
Low Level Output Voltage 0.3 V IOL = 1.0mA
Write Inhibit Voltage 2 V
CC
A.C. CHARACTERISTICS, Read Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
28LV64-25 28LV64-30 28LV64-35
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
t
RC
CE
Read Cycle Time 250 300 350 ns
CE Access Time 250 300 350 ns
t
AA
t
OE
(1)
t
LZ
(1)
t
OLZ
(1)(2)
t
HZ
(1)(2)
t
OHZ
(1)
t
OH
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) V
Doc. No. 25035-00 2/98
= VCC –0.3V to VCC +0.3V.
IHC
Address Access Time 250 300 350 ns
OEAccess Time 100 150 150 ns
CE Low to Active Output 0 0 0 ns
OE Low to Active Output 0 0 0 ns
CE High to High-Z Output 55 60 60 ns
OE High to High-Z Output 55 60 60 ns
Output Hold from Address Change 0 0 0 ns
4
Preliminary
CAT28LV64
Figure 1. A.C. Testing Input/Output Waveform
V - 0.3 V
CC
INPUT PULSE LEVELS REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
DEVICE
UNDER
TEST
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
(4)
1. 3K
2.0 V
0.6 V
Vcc
1.8 K
OUTPUT
C
= 100 pF
L
28LV64 F04
28LV64 F05
28LV64-25 28LV64-30 28LV64-35
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
WC
t
AS
t
AH
t
CS
t
CH
(2)
t
CW
t
OES
t
OEH
(2)
t
WP
t
DS
t
DH
(1)
t
INIT
(1)(3)
t
BLC
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
however a transition from HIGH to LOW within t
(4) Input rise and fall times (10% and 90%) < 10 ns.
Write Cycle Time 5 5 5 ms
Address Setup Time 0 0 0 ns
Address Hold Time 100 100 100 ns
CE Setup Time 0 0 0 ns
CE Hold Time 0 0 0 ns
CE Pulse Time 150 150 150 ns
OE Setup Time 10 10 10 ns
OE Hold Time 10 10 10 ns
WE Pulse Width 150 150 150 ns
Data Setup Time 100 100 100 ns
Data Hold Time 0 0 0 ns
Write Inhibit Period After Power-up 5 10 5 10 5 10 ms
Byte Load Cycle Time 0.1 100 0.1 100 0.1 100 µs
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
max. stops the timer.
BLC
5
Doc. No. 25035-00 2/98
CAT28LV64
Preliminary
DEVICE OPERATION
Read
Data stored in the CAT28LV64 is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system
environment.
Figure 3. Read Cycle
t
RC
ADDRESS
t
CE
CE
t
OE
OE
V
IH
t
WE
DATA OUT DA TA V ALIDDA TA V ALID
HIGH-Z
LZ
t
OLZ
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
t
OHZ
t
t
OH
t
AA
HZ
28LV64 F06
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
OE
WE
DATA OUT
DATA IN
t
AS
t
OES
t
CS
t
AH
t
WP
HIGH-Z
DATA VALID
t
DS
t
t
CH
DH
t
OEH
t
BLC
t
WC
5096 FHD F06
Doc. No. 25035-00 2/98
6
Preliminary
OE
CE
WE
ADDRESS
I/O
t
WP
t
BLC
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
t
WC
CAT28LV64
Page Write
The page write mode of the CAT28LV64 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single E2PROM write
cycle. This effectively reduces the byte-write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 32 byte temporary buffer. The page
address where data is to be written, specified by bits A
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A
Figure 5. Byte Write Cycle [CE Controlled]
ADDRESS
CE
t
AS
t
AH
t
CW
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t
BLC MAX
of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t
Upon completion of the page write sequence, WE must
stay high a minimum of t
BLC MAX
for the internal automatic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
5
only write data to the locations that were addressed and
will not rewrite the entire page.
4
t
WC
t
BLC
t
OEH
BLC MAX
.
OE
t
OES
WE
DATA OUT
DATA IN
t
CS
Figure 6. Page Mode Write Cycle
HIGH-Z
DATA VALID
t
DS
t
CH
t
DH
5094 FHD F07
7
5096 FHD F10
Doc. No. 25035-00 2/98
CAT28LV64
Preliminary
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O
are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
OE
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
data from the device will result in I/O6 toggling between
6
one and zero. However, once the write is complete, I/O
stops toggling and valid data can be read from the
device.
t
t
OE
t
WC
OES
6
I/O
7
D
= X D
IN
Figure 8. Toggle Bit
WE
CE
t
OEH
OE
I/O
6
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
(1)
t
OE
= X D
OUT
t
WC
OUT
(1)
= X
t
OES
28LV64 F10
28LV64 F11
Doc. No. 25035-00 2/98
8
Preliminary
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: 80
ADDRESS: 1555
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: 20
ADDRESS: 1555
CAT28LV64
HARDWARE DATA PROTECTION
The following is a list of hardware data protection features that are incorporated into the CAT28LV64.
(1) VCC sense provides for write protection when V
CC
falls below 2.0V min.
(2) A power on delay mechanism, t
(see AC charac-
INIT
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 2.40V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
WRITE DATA:
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
AA
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28LV64 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV64 is
in the standard operating mode).
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA: A0
ADDRESS: 1555
SOFTWARE DATA
PROTECTION A CTIV A TED
WRITE DATA: XX
TO ANY ADDRESS
WRITE LAST BYTE
TO
LAST ADDRESS
(1)
28LV64 F12 5094 FHD F09
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
9
Doc. No. 25035-00 2/98
CAT28LV64
Preliminary
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided.
Figure 11. Software Data Protection Timing
DATA
ADDRESS
CE
WE
AA
1555
55
0AAA
Figure 12. Resetting Software Data Protection Timing
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
A0
1555
t
WP
t
BLC
BYTE OR
PAGE
WRITES
ENABLED
t
WC
5094 FHD F13
DATA
ADDRESS
CE
WE
AA
1555
ORDERING INFORMATION
Prefix Device # Suffix
CAT
Optional
Company
ID
28LV64
Product
Number
55
0AAA
80
1555
NI
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Package
P: PDIP
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
AA
1555
55
0AAA
20
1555
t
WC
-25
Speed
25: 250ns
30: 300ns
35: 350ns
SDP
RESET
DEVICE
UNPROTECTED
5094 FHD F14
T
Tape & Reel
T: 500/Reel
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28LV64NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).
Doc. No. 25035-00 2/98
10
28LV64 F17
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