Datasheet CAT28LV256T13I-30T, CAT28LV256T13I-25T, CAT28LV256T13I-20T, CAT28LV256T13A-30T, CAT28LV256T13A-25T Datasheet (CTLST)
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CAT28LV256
256K-Bit CMOS PARALLEL E2PROM
FEATURES
■ 3.0V to 3.6V Supply
■ Read Access Times: 200/250/300 ns
■ Low Power CMOS Dissipation:
– Active: 15 mA Max.
– Standby: 150 µA Max.
■ Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
■ Fast Write Cycle Time:
– 10ms Max.
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
CMOS and TTL Compatible I/O
■
■ Automatic Page Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
■ End of Write Detection:
– Toggle Bit
DATADATA
–
DATA Polling
DATADATA
■ Hardware and Software Write Protection
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E2PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
BLOCK DIAGRAM
A6–A
A0–A
V
14
CC
CE
OE
WE
5
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
ROW
DECODER
HIGH VOL TAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O
7
28LV256 F01
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25040-00 4/01 P-1
CAT28LV256
PIN CONFIGURATION
DIP Package (P)
14
12
A
A
A
A
A
A
A
A
SS
1
2
3
7
4
6
5
5
6
4
7
3
8
2
9
1
10
0
11
0
12
1
13
2
14
A
A
I/O
I/O
I/O
V
V
A
A
WE
A
A
OE
11
A
A
13
CC
14
12
A
A
A
A
A
PLCC Package (N)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
13
8
9
11
10
A7A12A14NC
4321323130
5
A
6
6
A
5
7
A
4
8
A
3
9
A
2
A
1
A
I/O
0
NC
0
7
6
5
4
3
TOP VIEW
10
11
12
13
14 15 16 17 18 19 20
2
SS
I/O1I/O
NC
V
13
VCCWE
A
29
28
27
26
25
24
23
22
21
5
I/O3I/O4I/O
A
A
A
NC
OE
A
CE
I/O
I/O
8
9
11
10
7
6
28LV256 F02
TSOP Top View (8mm X 13.4mm) (T13)
1
2
3
9
4
8
5
6
7
8
9
10
7
11
6
12
5
13
4
14
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
0
A
1
A
2
7
6
5
4
3
2
1
0
PIN FUNCTIONS
Pin Name Function Pin Name Function
A0–A
14
I/O0–I/O
7
CE Chip Enable V
OE Output Enable NC No Connect
Doc. No. 25040-00 4/01 P-1
Address Inputs WE Write Enable
Data Inputs/Outputs V
CC
SS
2
3.0 to 3.6 V Supply
Ground
28LV256 F03
CAT28LV256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
V
with Respect to Ground ............... –2.0V to +7.0V
CC
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(2)
........... –2.0V to +VCC + 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Lead Soldering Temperature (10 secs)............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
(1)
N
T
V
I
END
DR
ZAP
LTH
(1)
(1)
(1)(4)
Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Test Max. Units Conditions
(1)
C
I/O
(1)
C
IN
Input/Output Capacitance 10 pF V
I/O
= 0V
Input Capacitance 6 pF VIN = 0V
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
Byte Write (WE Controlled) L H D
Byte Write (CE Controlled) L H D
OUT
IN
IN
ACTIVE
ACTIVE
ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
3
Doc. No. 25040-00 4/01 P-1
CAT28LV256
D.C. OPERATING CHARACTERISTICS
VCC = 3.0V to 3.6V, unless otherwise specified
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
I
SBC
I
LI
I
LO
V
V
V
V
V
IH
IL
OH
OL
WI
(2)
(2)
VCC Current (Operating, TTL) 15 mA CE = OE = VIL,
VCC Current (Standby, CMOS) 150 µA CE = V
Input Leakage Current –1 1 µAVIN = GND to V
Output Leakage Current –5 5 µAV
High Level Input Voltage 2 VCC +0.3 V
Low Level Input Voltage –0.3 0.6 V
High Level Output Voltage 2 V IOH = –100µA
Low Level Output Voltage 0.3 V IOL = 1.0mA
Write Inhibit Voltage 2 V
A.C. CHARACTERISTICS, Read Cycle
VCC = 3.0V to 3.6V, unless otherwise specified
f = 1/tRC min, All I/O’s Open
,
IHC
All I/O’s Open
CC
= GND to VCC,
OUT
CE = V
IH
28LV256-20 28LV256-25 28LV256-30
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
RC
t
CE
t
AA
t
OE
(1)
t
LZ
(1)
t
OLZ
(1)(3)
t
HZ
(1)(3)
t
OHZ
(1)
t
OH
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) V
(3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
= VCC –0.3V to VCC +0.3V.
IHC
Read Cycle Time 200 250 300 ns
CE Access Time 200 250 300 ns
Address Access Time 200 250 300 ns
OE Access Time 80 100 110 ns
CE Low to Active Output 0 0 0 ns
OE Low to Active Output 0 0 0 ns
CE High to High-Z Output 50 55 60 ns
OE High to High-Z Output 50 55 60 ns
Output Hold from Address Change 0 0 0 ns
Doc. No. 25040-00 4/01 P-1
4
CAT28LV256
Figure 1. A.C. Testing Input/Output Waveform
VCC - 0.3V
INPUT PULSE LEVELS REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
DEVICE
UNDER
TEST
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
VCC = 3.0V to 3.6V, unless otherwise specified
(2)
2.0 V
0.6 V
1.3K
V
cc
1.8K
28LV256 F04
OUTPUT
CL = 100 pF
28LV256 F05
28LV256-20 28LV256-25 28LV256-30
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
WC
t
AS
t
AH
t
CS
t
CH
(3)
t
CW
t
OES
t
OEH
(3)
t
WP
t
DS
t
DH
(1)
t
INIT
(1)(4)
t
BLC
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
however a transition from HIGH to LOW within t
Write Cycle Time 10 10 10 ms
Address Setup Time 0 0 0 ns
Address Hold Time 100 100 100 ns
CE Setup Time 0 0 0 ns
CE Hold Time 0 0 0 ns
CE Pulse Time 150 150 150 ns
OE Setup Time 0 0 0 ns
OE Hold Time 0 0 0 ns
WE Pulse Width 150 150 150 ns
Data Setup Time 50 50 50 ns
Data Hold Time 0 0 0 ns
Write Inhibit Period After Power-up 5 10 5 10 5 10 ms
Byte Load Cycle Time 0.15 100 0.15 100 0.15 100 µs
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
max. stops the timer.
BLC
5
Doc. No. 25040-00 4/01 P-1
CAT28LV256
DEVICE OPERATION
Read
Data stored in the CAT28LV256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Figure 3. Read Cycle
t
RC
ADDRESS
t
CE
CE
t
OE
OE
V
IH
WE
DATA OUT DA TA VALIDDA TA VALID
HIGH-Z
t
LZ
t
OLZ
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
t
OHZ
t
OH
t
AA
t
HZ
28LV256 F06
Figure 4. Byte Write Cycle [
ADDRESS
t
AS
CE
OE
WE
DATA OUT
DATA IN
WEWE
WE Controlled]
WEWE
t
t
CS
t
OES
AH
t
WP
HIGH-Z
DATA VALID
t
DS
t
t
CH
DH
t
OEH
t
BLC
t
WC
28LV256 F07
Doc. No. 25040-00 4/01 P-1
6
CAT28LV256
Page Write
The page write mode of the CAT28LV256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytes of data to be programmed within a single E
2
PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A
Figure 5. Byte Write Cycle [
ADDRESS
t
AS
CE
CECE
CE Controlled]
CECE
t
AH
t
CW
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t
BLC MAX
of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t
Upon completion of the page write sequence, WE must
stay high a minimum of t
BLC MAX
for the internal automatic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
6
only write data to the locations that were addressed and
will not rewrite the entire page.
5
t
WC
t
BLC
t
OEH
BLC MAX
.
OE
t
OES
WE
DATA OUT
DATA IN
t
CS
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
WP
HIGH-Z
DATA VALID
t
DS
t
BLC
t
CH
t
DH
28LV256 F08
ADDRESS
I/O
LAST BYTE
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
7
t
WC
28LV256 F09
Doc. No. 25040-00 4/01 P-1
CAT28LV256
DATADATA
DATA Polling
DATADATA
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O
are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Figure 7. DATA Polling
ADDRESS
CE
WE
OE
(I/O0–I/O
7
t
OEH
Toggle Bit
In addition to the DATA Polling feature, the device can
determine the completion of a write cycle, while a write
cycle is in progress, by reading data from the device.
This results in I/O6 toggling between one and zero. Once
6
the write is complete, however, I/O6 stops toggling and
valid data can be read from the device.
t
t
OE
OES
I/O
7
D
= X D
IN
Figure 8. Toggle Bit
WE
CE
t
OEH
OE
I/O
6
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
t
OE
(1) (1)
t
WC
= X D
OUT
t
WC
OUT
= X
t
OES
28LV256 F10
28LV256 F11
Doc. No. 25040-00 4/01 P-1
8
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 80
ADDRESS: 5555
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 20
ADDRESS: 5555
HARDWARE DATA PROTECTION
The following hardware data protection features are
incorporated into the CAT28LV256.
(1) VCC sense provides write protection when VCC falls
below 2.0V min.
(2) A power on delay mechanism, t
(see AC charac-
INIT
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 2.4V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high, or WE high.
CAT28LV256
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28LV256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV256
is in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: A0
ADDRESS: 5555
SOFTWARE DATA
PROTECTION A CTIV A TED
WRITE DATA: XX
TO ANY ADDRESS
Figure 10. Write Sequence for Deactivating
Software Data Protection
(1)
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
WRITE LAST BYTE
TO
LAST ADDRESS
28LV256 F12 28LV256 F13
BLC
9
Doc. No. 25040-00 4/01 P-1
CAT28LV256
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued, regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided.
Figure 11. Software Data Protection Timing
DATA
ADDRESS
CE
WE
AA
5555
55
2AAA
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
A0
5555
t
WP
t
BLC
BYTE OR
PAGE
WRITES
ENABLED
t
WC
28LV256 F14
Figure 12. Resetting Software Data Protection Timing
DATA
ADDRESS
CE
WE
AA
5555
55
2AAA
80
5555
ORDERING INFORMATION
Prefix Device # Suffix
CAT
Optional
Company
ID
28LV256
NI
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Product
Number
Package
P: PDIP
N: PLCC
T13: TSOP (8mmx13.4mm)
AA
5555
55
2AAA
20
5555
t
WC
-25
Tape & Reel
T: 500/Reel
Speed
20: 200ns
25: 250ns
30: 300ns
SDP
RESET
DEVICE
UNPROTECTED
28LV256 F15
T
28LV256 F16
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28LV256NI-25T (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns
Access Time, Tape & Reel).
Doc. No. 25040-00 4/01 P-1
10
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