Datasheet CAT28HT256HD-25, CAT28HT256HD-20, CAT28HT256D-25, CAT28HT256D-20 Datasheet (CTLST)
Advanced
CAT28HT256
256K-Bit CMOS PARALLEL E2PROM
FEATURES
■ Fast Read Access Times: 200/250 ns
■ Low Power CMOS Dissipation:
–Active: 30 mA Max.
–Standby: 150 µA Max.
■ Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
■ Fast Write Cycle Time:
–10ms Max
■ CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28HT256 is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 32K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28HT256 features hardware and software write
Extended Temperature: 170˚C
■ Automatic Page Write Operation:
–1 to 64 Bytes in 10ms
–Page Load Timer
■ End of Write Detection:
–Toggle Bit
DATADATA
–
DATA Polling
DATADATA
■ Hardware and Software Write Protection
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
protection as well as an internal Error Correction Code
(ECC) for extremely high reliability.
The CAT28HT256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin Ceramic DIP package.
BLOCK DIAGRAM
A6–A
14
V
CC
CE
OE
WE
A0–A
5
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOL TAGE
GENERAT OR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
8-91
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O
7
5096 FHD F02
CAT28HT256
PIN CONFIGURATION PIN FUNCTIONS
CERDIP Package (D)
1
I/O
I/O
I/O
V
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
1
2
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
13
8
9
11
10
RELIABILITY CHARACTERISTICS
7
6
5
4
3
5096 FHD F01
Pin Name Function
A0–A
14
I/O0–I/O
7
CE Chip Enable
OE Output Enable
WE Write Enable
V
CC
V
SS
NC No Connect
Advanced
Address Inputs
Data Inputs/Outputs
5V Supply
Ground
Symbol Parameter Min. Max. Units Test Method
N
T
V
I
LTH
END
DR
ZAP
(1)
(1)
(1)
(1)(2)
Endurance 104 or 10
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17
5
Cycles/Byte MIL-STD-883, Test Method 1033
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
Byte Write (WE Controlled) L H D
Byte Write (CE Controlled) L H D
OUT
IN
IN
ACTIVE
ACTIVE
ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
(1)
C
I/O
(1)
C
IN
Input/Output Capacitance 10 pF V
I/O
= 0V
Input Capacitance 6 pF VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
Stock No. 21065-03 2/98
8-92
Advanced
CAT28HT256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +150°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(1)
........... –2.0V to +VCC + 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Lead Soldering Temperature (10 secs)............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified. (Temperature 0˚C to 170˚C)
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
VCC Current (Operating, TTL) 30 mA CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
(3)
I
CCC
VCC Current (Operating, CMOS) 25 mA CE = OE = V
ILC
,
f = 1/tRC min, All I/O’s Open
I
SB
I
SBC
(4)
VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open
VCC Current (Standby, CMOS) 300 µA CE = V
IHC
,
All I/O’s Open
I
LI
I
LO
(4)
V
IH
(3)
V
IL
V
OH
V
OL
V
WI
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) V
(4) V
= –0.3V to +0.3V.
ILC
= VCC –0.3V to VCC +0.3V.
IHC
Input Leakage Current –10 20 µAVIN = GND to V
Output Leakage Current –10 20 µAV
= GND to VCC,
OUT
CE = V
IH
High Level Input Voltage 2 VCC +0.3 V
Low Level Input Voltage –0.3 0.8 V
High Level Output Voltage 2.4 V IOH = –400µA
Low Level Output Voltage 0.4 V IOL = 2.1mA
Write Inhibit Voltage 3.5 V
CC
8-93
Stock No. 21065-03 2/98
CAT28HT256
Advanced
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V ±10%, unless otherwise specified. (Temperature 0˚C to 170˚C)
28HT256-20 28HT256-25
Symbol Parameter Min. Max. Min. Max. Units
t
RC
t
CE
t
AA
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
(1)
(1)(4)
(1)
Read Cycle Time 200 250 ns
CE Access Time 200 250 ns
Address Access Time 200 250 ns
OE Access Time 80 100 ns
CE Low to Active Output 0 0 ns
(1)
OE Low to Active Output 0 0 ns
CE High to High-Z Output 50 50 ns
(1)(4)
OE High to High-Z Output 50 50 ns
Output Hold from Address Change 0 0 ns
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V ±10%, unless otherwise specified. (Temperature 0˚C to 170˚C)
28HT256-20 28HT256-25
Symbol Parameter Min. Max. Min. Max. Units
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
t
OES
t
OEH
t
WP
t
DS
t
DH
t
INIT
t
BLC
(2)
(2)
Write Cycle Time 10 10 ms
Address Setup Time 0 0 ns
Address Hold Time 75 75 ns
CE Setup Time 0 0 ns
CE Hold Time 0 0 ns
CE Pulse Time 100 100 ns
OE Setup Time 0 0 ns
OE Hold Time 0 0 ns
WE Pulse Width 100 100 ns
Data Setup Time 50 50 ns
Data Hold Time 10 10 ns
(1)
Write Inhibit Period After Power-up 5 10 5 10 ms
(1)(3)
Byte Load Cycle Time 0.1 100 0.1 100 µs
Note:
(1) This parameter is tested intitially and after a design or process change that affects the parameter..
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
however a transition from HIGH to LOW within t
(4) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Stock No. 21065-03 2/98
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
max. stops the timer.
BLC
8-94
Advanced
CAT28HT256
DEVICE OPERATION
Read
Data stored in the CAT28HT256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Figure 1. A.C. Testing Input/Output Waveform
2.4 V
INPUT PULSE LEVELS REFERENCE POINTS
0.45 V
Note:
(1) Input rise and fall times (10% and 90%) < 10 ns.
Figure 2. A.C. Testing Load Circuit (example)
(1)
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
2.0 V
0.8 V
5096 FHD F03
1.3V
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT DATA VALIDDATA VALID
1N914
3.3K
DEVICE
UNDER
TEST
CL INCLUDES JIG CAPACITANCE
t
RC
t
CE
t
OE
V
IH
t
LZ
t
HIGH-Z
OLZ
CL = 100 pF
t
OH
t
AA
OUT
t
OHZ
t
HZ
5096 FHD F04
8-95
Stock No. 21065-03 2/98
CAT28HT256
Advanced
Page Write
The page write mode of the CAT28HT256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytes of data to be programmed within a single E2PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A
Figure 4. Byte Write Cycle [
ADDRESS
CE
OE
WE WE
WE Controlled]
WE WE
t
AS
t
CS
t
AH
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t
BLC MAX
of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t
Upon completion of the page write sequence, WE must
stay high a minimum of t
BLC MAX
for the internal automatic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
6
only write data to the locations that were addressed and
will not rewrite the entire page.
5
t
WC
t
CH
BLC MAX
.
WE
DATA OUT
DATA IN
Figure 5. Byte Write Cycle [
ADDRESS
CE
OE
WE
DATA OUT
t
OES
CECE
CE Controlled]
CECE
t
AS
t
t
CS
OES
OEH
t
CH
t
DH
t
OEH
t
BLC
t
BLC
t
WC
t
WP
HIGH-Z
DATA VALID
t
DS
t
AH
t
CW
t
HIGH-Z
Stock No. 21065-03 2/98
DATA IN
DATA VALID
t
DS
8-96
t
DH
5096 FHD F07
5096 FHD F06
Advanced
CAT28HT256
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O
are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Figure 6. Page Mode Write Cycle
OE
CE
t
WP
WE
ADDRESS
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
Toggle Bit
In addition to the DATA Polling feature of the
CAT28HT256, the device offers an additional method
for determining the completion of a write cycle. While a
write cycle is in progress, reading data from the device
6
will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and
valid data can be read from the device.
t
BLC
t
WC
LAST BYTE
5096 FHD F10
Figure 7.
DATADATA
DATA Polling
DATADATA
ADDRESS
Figure 8. Toggle Bit
WE
CE
OE
CE
WE
t
OEH
OE
I/O
7
t
OEH
D
= X D
IN
t
OE
t
OE
t
WC
= X D
OUT
OUT
= X
t
OES
t
OES
5096 FHD F11
I/O
6
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
(1) (1)
t
WC
8-97
5096 FHD F12
Stock No. 21065-03 2/98
CAT28HT256
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 80
ADDRESS: 5555
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 20
ADDRESS: 5555
HARDWARE DATA PROTECTION
The following is a list of hardware data protection features that are incorporated into the CAT28HT256.
(1) VCC sense provides for write protection when V
falls below 3.5V min.
(2) A power on delay mechanism, t
(see AC charac-
INIT
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
CC
Advanced
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28HT256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28HT256
is in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: A0
ADDRESS: 5555
SOFTWARE DATA
PROTECTION ACTIVATED
WRITE DATA: XX
TO ANY ADDRESS
(12)
(1)
Figure 10. Write Sequence for Deactivating
Software Data Protection
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
Stock No. 21065-03 2/98
WRITE LAST BYTE
TO
LAST ADDRESS
5096 FHD F08 5096 FHD F09
BLC
8-98
Advanced
CE
WE
AA
5555
55
2AAA
DATA
ADDRESS
t
WC80
5555
AA
5555
55
2AAA
20
5555
SDP
RESET
DEVICE
UNPROTECTED
CAT28HT256
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided.
Figure 11. Software Data Protection Timing
DATA
ADDRESS
CE
WE
AA
5555
55
2AAA
Figure 12. Resetting Software Data Protection Timing
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
t
A0
5555
t
WP
t
BLC
BYTE OR
PAGE
WRITES
ENABLED
WC
5096 FHD F13
ORDERING INFORMATION
Prefix Device # Suffix
CAT
28HT256
H
D
-20
Product
Number
Package
D: CERDIP
Optional
Company
ID
Notes:
(1) The device used in the above example is a CAT28HT256HD-20 (100,000 Cycle Endurance, CERDIP, 200 ns Access Time).
Endurance
Blank = 10,000 Cycle
H = 100,000 Cycle
8-99
Speed
20: 200ns
25: 250ns
Stock No. 21065-03 2/98
5096 FHD F14
28HT256 F16
CAT28HT256
Advanced
Stock No. 21065-03 2/98
8-100
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