–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
■ High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
■ 12.0V ± 5% Programming and Erase Voltage
■ Electronic Signature
DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
■ Commercial, Industrial and Automotive
Temperature Ranges
■ Stop Timer for Program/Erase
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP ( 8 x 20)
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F512 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature....................... –65 °C to +150°C
Voltage on Any Pin with
Respect to Ground
Voltage on Pin A9 with
Respect to Ground
VPP with Respect to Ground
during Program/Erase
VCC with Respect to Ground
(1)
........... –2.0V to +VCC + 2.0V
(1)
................... –2.0V to +13.5V
(1)
.............. –2.0V to +14.0V
(1)
............ –2.0V to +7.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Package Power Dissipation
Capability (TA = 25°C).................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
SymbolParameterMin.Max.UnitsTest Method
(3)
N
T
V
I
LTH
END
DR
ZAP
(3)
(3)
(3)(4)
Endurance100KCycles/ByteMIL-STD-883, Test Method 1033
Data Retention10YearsMIL-STD-883, Test Method 1008
ESD Susceptibility2000VoltsMIL-STD-883, Test Method 3015
Latch-Up100mAJEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Limits
SymbolTestMinMax.UnitsConditions
(3)
C
IN
(3)
C
OUT
(3)
C
VPP
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
VCC Supply Voltage4.55.5V
VPP During Read Operations06.5V
VPP During Read/Erase/Program11.412.6V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified.
JEDEC Standard28F512-9028F512-12 28F512-15
SymbolSymbolParameterMin. Max.Min. Max. Min. Max. Unit
t
AVAV
t
RC
Read Cycle Time90120150ns
t
ELQV
t
AVQV
t
GLQV
t
AXQX
t
GLQX
t
ELQX
t
GHQZ
t
EHQZ
t
WHGL
t
CE
t
ACC
t
OE
t
OH
t
OLZ
(1)(6)
t
LZ
t
DF
t
DF
(1)
-Write Recovery Time Before Read666µs
CE Access Time90120150ns
Address Access Time90120150ns
OE Access Time355055ns
Output Hold from Address OE/CE Change000ns
(1)(6)
OE to Output in Low-Z000ns
CE to Output in Low-Z000ns
(1)(2)
OE High to Output High-Z203035ns
(1)(2)
CE High to Output High-Z304045ns
Figure 1. A.C. Testing Input/Output Waveform
2.4 V
INPUT PULSE LEVELSREFERENCE POINTS
0.45 V
Figure 2. A.C. Testing Load Circuit (example)
(3)(4)(5)
2.0 V
0.8 V
5096 FHD F03
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
5
5108 FHD F04
Doc. No. 25042-00 2/98 F-1
CAT28F512
A.C. CHARACTERISTICS, Program/Erase Operation
VCC = +5V ±10%, unless otherwise specified.
Preliminary
JEDEC
Standard
28F512-9028F512-1228F512-15
SymbolSymbolParameterMin. Max. Min. Max. Min. Max. Unit
t
AVAV
t
AVWL
t
WLAX
t
DVWH
t
WHDX
t
ELWL
t
WHEH
t
WLWH
t
WHWL
t
WHWH1
t
WHWH2
t
WHGL
t
GHWL
t
VPEL
t
WC
t
AS
t
AH
t
DS
t
DH
t
CS
t
CH
t
WP
t
WPH
(2)
-Program Pulse Width101010µs
(2)
-Erase Pulse Width9.59.59.5ms
Write Cycle Time90120150ns
Address Setup Time000ns
Address Hold Time404040ns
Data Setup Time404040ns
Data Hold Time101010ns
CE Setup Time000ns
CE Hold Time000ns
WE Pulse Width404040ns
WE High Pulse Width202020ns
-Write Recovery Time Before Read666µs
-Read Recovery Time Before Write000µs
-V
Setup Time to CE100100100ns
PP
ERASE AND PROGRAMMING PERFORMANCE
(1)
28F512-9028F512-1228F512-15
ParameterMin.Typ.Max.Min.Typ.Max.Min.Typ.Max.Unit
Chip Erase Time
Chip Program Time
Note:
(1) Please refer to Supply characteristics for the value of V
V
can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
PPL
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
(3)(5)
(3)(4)
0.5100.5100.510sec
161616sec
PPH
and V
. The VPP supply can be either hardwired or switched. If VPP is switched,
See Command Table
During Write Cycle
During Write Cycle
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.
Pins
First Bus CycleSecond Bus Cycle
ModeOperationAddressD
IN
Set ReadWriteX00HReadA
OperationAddress D
IN
IN
D
D
OUT
OUT
Read Sig. (MFG)WriteX90HRead0031H
Read Sig. (Device)WriteX90HRead01B8H
EraseWriteX20HWriteX20H
Erase VerifyWriteA
IN
ProgramWriteX40HWriteA
A0HReadXD
IN
D
IN
Program VerifyWriteXC0HReadXD
ResetWriteXFFHWriteXFFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, V
PPL
, V
PPH
)
OUT
OUT
7
Doc. No. 25042-00 2/98 F-1
CAT28F512
READ OPERATIONS
Read Mode
A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
the memory location corresponding to the state of the 16
address pins. The respective timing waveforms for the
read operation are shown in Figure 3. Refer to the AC
Read characteristics for specific timing parameters.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
Preliminary
The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
and applying the required high voltage on address pin A
while all other address lines are held at VIL.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O7:
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F512 Code = 1011 1000 (B8H)
Standby Mode
With CE at a logic-high level, the CAT28F512 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance
state.
9
Figure 3. A.C. Timing for Read Operation
POWER UP
ADDRESSES
CE (E)
OE (G)
WE (W)
HIGH-Z
DATA (I/O)
STANDBYDEVICE AND
ADDRESS SELECTION
t
WHGL
t
GLQX
ADDRESS STABLE
t
AVAV
(t
)
OLZ
t
(tLZ)
ELQX
t
(t
AVQV
ACC
OUPUTS
ENABLED
(tRC)
t
GLQV
)
(tOE)
DA T A VALIDSTANDBY
t
EHQZ
t
GHQZ
t
(tCE)
ELQV
OUTPUT VALID
t
AXQX
POWER DOWN
(tDF)
(tDF)
(tOH)
HIGH-Z
28F512 F06
Doc. No. 25042-00 2/98 F-1
8
Preliminary
CAT28F512
WRITE OPERATIONS
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register while keeping
VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F512 Code = 1011 1000 (B8H)
Erase Mode
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
erase operation, the identical command of 20H has to be
written again into the register. This two-step process
ensures against accidental erasure of the memory contents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H) is sent to the command register. During this cycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing specification. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.
Figure 4. A.C. Timing for Erase Operation
VCC POWER-UP
& STANDBY
ADDRESSES
CE (E)
OE (G)
WE (W)
DATA (I/O)
V
CC
V
PP
5.0V
0V
V
PPH
V
PPL
t
GHWL
HIGH-Z
SETUP ERASE
COMMAND
t
WC
t
CS
t
CH
t
WPH
t
WP
t
DS
DATA IN
= 20H
t
VPEL
ERASE
COMMAND
t
WC
t
DH
t
DS
ERASINGERASE VERIFY
t
AS
t
CH
t
CS
t
WHWH2
t
WP
t
DH
DATA IN
= 20H
COMMAND
t
WC
t
WP
t
DS
t
AH
DATA IN
= A0H
t
DH
t
CH
t
WHGL
VERIFICATION
t
OE
t
OLZ
t
LZ
t
CE
ERASE
t
RC
VCC POWER-DOWN/
VALID
DATA OUT
STANDBY
t
EHQZ
t
DF
t
OH
28F512 F11
9
Doc. No. 25042-00 2/98 F-1
CAT28F512
Preliminary
Figure 5. Chip Erase Algorithm
START ERASURE
APPLY V
PROGRAM ALL
BYTES TO 00H
WRITE ERASE
SETUP COMMAND
WRITE ERASE
PPH
INITIALIZE
ADDRESS
INITIALIZE
PLSCNT = 0
COMMAND
(1)
BUS
OPERATION
STANDBY
WRITE
WRITE
COMMANDCOMMENTS
VPP RAMPS TO V
(OR VPP HARDWIRED)
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
INITIALIZE ADDRESS
PLSCNT = PULSE COUNT
ERASE
ERASE
ACTUAL ERASE
NEEDS 10ms PULSE,
DATA = 20H
DATA = 20H
DATA = 20H
PPH
INCREMENT
ADDRESS
TIME OUT 10ms
WRITE ERASE
VERIFY COMMAND
TIME OUT 6µs
READ DATA
FROM DEVICE
DATA =
FFH?
NO
LAST
ADDRESS?
WRITE READ
COMMAND
APPLY V
YES
YES
PPL
NO
NO
INC PLSCNT
1000
= 3000 ?
YES
APPLY V
PPL
WRITE
READ
STANDBY
WRITE
STANDBY
ERASE
VERIFY
READ
WAIT
ADDRESS = BYTE TO VERIFY
STOPS ERASE OPERA TION
READ BYTE TO
VERIFY ERASURE
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
RESETS THE REGISTER
FOR READ OPERATION
VPP RAMPS TO V
(OR VPP HARDWIRED)
40H;
DATA = 20H;
A0H
WAIT
DATA = 00H
PPL
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 25042-00 2/98 F-1
10
5108 FHD F10
Preliminary
CAT28F512
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the programming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminating the need for a maximum program timing specification. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Programverify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
VCC POWER-UP
& STANDBY
ADDRESSES
CE (E)
OE (G)
WE (W)
DATA (I/O)
V
CC
V
PP
5.0V
0V
V
PPH
V
PPL
SETUP PROGRAM
COMMAND
t
GHWL
HIGH-Z
t
DS
t
VPEL
t
WC
t
CS
t
CH
t
WPH
t
WP
DATA IN
= 40H
LATCH ADDRESS
& DATA
t
AS
t
DH
t
DS
PROGRAMMING
t
AH
t
CH
t
WP
DATA IN
t
CS
t
WHWH1
t
DH
PROGRAM
VERIFY
COMMAND
t
WC
t
WP
t
DS
t
DH
DATA IN
= C0H
t
CH
t
WHGL
VERIFICATION
t
OE
t
OLZ
t
LZ
t
CE
PROGRAM
t
RC
DATA OUT
VCC POWER-DOWN/
STANDBY
t
EHQZ
t
DF
t
OH
VALID
28F512 F08
11
Doc. No. 25042-00 2/98 F-1
CAT28F512
Preliminary
Figure 7. Programming Algorithm
START
PROGRAMMING
APPLY V
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
WRITE PROG. CMD
ADDR AND DAT A
TIME OUT 10µs
PPH
INITIALIZE
ADDRESS
(1)
BUS
OPERATION
STANDBY
1ST WRITE
CYCLE
2ND WRITE
CYCLE
COMMANDCOMMENTS
VPP RAMPS TO V
(OR VPP HARDWIRED)
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
WRITE
SETUP
PROGRAM
DATA = 40H
VALID ADDRESS AND DA T A
WAIT
PPH
INCREMENT
ADDRESS
WRITE PROGRAM
VERIFY COMMAND
TIME OUT 6µs
READ DATA
FROM DEVICE
VERIFY
DATA ?
NO
LAST
ADDRESS?
WRITE READ
COMMAND
APPLY V
YES
YES
PPL
NO
INC
PLSCNT
= 25 ?
APPLY V
NO
YES
PPL
1ST WRITE
CYCLE
READ
STANDBY
1ST WRITE
CYCLE
STANDBY
PROGRAM
VERIFY
READ
DATA = C0H
WAIT
READ BYTE TO VERIFY
PROGRAMMING
COMPARE DATA OUTPUT
TO DATA EXPECTED
DA TA = 00H
SETS THE REGISTER FOR
READ OPERATION
VPP RAMPS TO V
(OR VPP HARDWIRED)
PPL
PROGRAMMING
COMPLETED
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 25042-00 2/98 F-1
PROGRAM
ERROR
12
28F512 F09
Preliminary
CAT28F512
Abort/Reset
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 8. Alternate A.C. Timing for Program Operation
POWER UP/DOWN PROTECTION
The CAT28F512 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and V
may power up in any order. Additionally VPP may be
hardwired to V
independent of the state of VCC and
PPH
any power up/down cycling. The internal command
register of the CAT28F512 is reset to the Read Mode on
power up.
CC
VCC POWER-UP
& STANDBY
ADDRESSES
WE (E)
OE (G)
CE (W)
DATA (I/O)
V
CC
V
PP
5.0V
0V
V
PPH
V
PPL
SETUP PROGRAM
COMMAND
t
GHEL
t
DVEH
HIGH-Z
t
WC
t
EHWH
t
VPEL
t
t
WLEL
t
EHEL
DATA IN
= 40H
LATCH ADDRESS
& DATA
AVEL
t
EHDX
PROGRAMMING
t
ELAX
t
WLEL
t
ELEH
t
DVEH
DATA IN
t
EHWH
t
WLEL
t
EHEH
t
EHDX
PROGRAM
VERIFY
COMMAND
t
ELEH
t
DVEH
t
WC
DATA IN
= C0H
t
EHWH
t
EHGL
VERIFICATION
t
OE
t
EHDX
t
OLZ
t
LZ
t
CE
PROGRAM
t
RC
DATA OUT
VCC POWER-DOWN/
STANDBY
t
EHQZ
t
DF
t
OH
VALID
28F512 F10
13
Doc. No. 25042-00 2/98 F-1
CAT28F512
Preliminary
ALTERNATE
CECE
CE-CONTROLLED WRITES
CECE
JEDEC Standard28F512-9028F512-1228F512-15
Symbol SymbolParameterMin. Max. Min. Max. Min. Max.Unit
t
AVAV
t
AVEL
t
ELAX
t
DVEH
t
EHDX
t
EHGL
t
GHEL
t
WLEL
t
EHWH
t
ELEH
t
EHEL
t
VPEL
t
t
t
t
t
WC
AS
AH
DS
DH
Write Cycle Time90120120ns
Address Setup Time000ns
Address Hold Time404040ns
Data Setup Time404040ns
Data Hold Time101010ns