Datasheet CAT28F010TR-70T, CAT28F010TR-12T, CAT28F010TI-90T, CAT28F010TI-70T, CAT28F010TI-12T Datasheet (CTLST)

CAT28F010

1 Megabit CMOS Flash Memory

FEATURES

Licensed Intel

second source

■ Fast Read Access Time: 70/90/120 ns

■ Low Power CMOS Dissipation:

–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)

■ High Speed Programming:

–10 µs per byte
–2 Sec Typ Chip Program

■ 0.5 Seconds Typical Chip-Erase

■ 12.0V ± 5% Programming and Erase Voltage

■ Stop Timer for Program/Erase

DESCRIPTION

The CAT28F010 is a high speed 128K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.

It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,

■ Commercial, Industrial and Automotive

Temperature Ranges

■ On-Chip Address and Data Latches

■ JEDEC Standard Pinouts:

–32-pin DIP
–32-pin PLCC
–32-pin TSOP (8 x 20)

■ 100,000 Program/Erase Cycles

■ 10 Year Data Retention

■ Electronic Signature

using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.

The CAT28F010 is manufactured using Catalyst’s ad­vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.

BLOCK DIAGRAM

WE

CE
OE

A0–A

16

VOLTAGE VERIFY

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

COMMAND
REGISTER

SWITCH

ERASE VOLTAGE

SWITCH

PROGRAM VOLTAGE

SWITCH

Y-DECODER

X-DECODER

ADDRESS LATCH

1

CE, OE LOGIC

I/O0–I/O

I/O BUFFERS

DATA

LATCH

Y-GATING

1,048,576 BIT

MEMORY

ARRAY

7

SENSE

AMP

5108 FHD F02

Doc. No. 25005-0A 2/98 F-1

CAT28F010

PIN CONFIGURATION

DIP Package (P)

1

V

PP

A

16

A

15

A

12

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

I/O

0

I/O

1

I/O

2

V

SS

32

V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

CC

31

WE

30

N/C

29

A

14

A

28

13

A

27

8

A

26

9

A

A

25
24

OE

23

A

22

CE

21

I/O

I/O

20

I/O

19

I/O

18

I/O

17

7

11

A

6

A

5

10

A

4

A

3

7

A

2

6

A

1

5

A

0

4

I/O

0

3

A

11

A

9

A

8

A

13

A

14

NC

WE

V

CC

V

PP

A

16

A

15

A

12

A

7

A

6

A

5

A

4

PIN FUNCTIONS

Pin Name Type Function

A0–A

16

PLCC Package (N)

A12A15A16VPPVCCWE

4321323130

5
6
7
8
9
10
11
12
13

14 15 16 17 18 19 20

2

SS

I/O1I/O

I/O3I/O4I/O5I/O

V

N/C

29

A

28

A

27

A

26

A

25

A

24

OE

23

A

22

CE

21

I/O

6

5108 FHD F01

I/O0–I/O
CE Input Chip Enable

14
13
8
9
11

10

7

OE Input Output Enable
WE Input Write Enable
V
V
V

7

CC
SS
PP

5108 FHD F01

TSOP Package (Standard Pinout 8mm x 20mm) (T)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Input Address Inputs for

memory addressing

I/O Data Input/Output

Voltage Supply
Ground
Program/Erase

Voltage Supply

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE
A
CE
I/O
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
A
A
A
A

10

7
6
5
4
3

SS

2
1

0
0
1
2
3

Doc. No. 25005-0A 2/98 F-1

A

I/O
I/O
I/O
I/O
I/O

V

I/O
I/O
I/O

OE

10

CE

SS

A
A
A
A

TSOP Package (Reverse Pinout) (TR)

1
2
3
4

7

5

6

6

5

7

4

8

3

9
10

2

11

1

12

0

13

0

14

1

15

2

16

3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

2

A
A
A
A
A
NC
WE
V
V
A
A
A
A
A
A
A

11
9
8
13
14

CC
PP
16
15
12
7
6
5
4

5108 FHD F14

CAT28F010

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................... –55°C to +95°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

Voltage on Pin A9 with

Respect to Ground

VPP with Respect to Ground

during Program/Erase

VCC with Respect to Ground

(1)

........... –2.0V to +VCC + 2.0V

(1)

................... –2.0V to +13.5V

(1)

.............. –2.0V to +14.0V

(1)

............ –2.0V to +7.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

Package Power Dissipation

Capability (TA = 25°C) .................................. 1.0 W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Test Method

(3)

N
T
V
I

LTH

END

DR
ZAP

(3)

(3)

(3)(4)

Endurance 100K Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 10 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

CAPACITANCE TA = 25°C, f = 1.0 MHz

Limits

Symbol Test Min Max. Units Conditions

(3)

C

IN

(3)

C

OUT

(3)

C

VPP

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Input Pin Capacitance 6 pF V
Output Pin Capacitance 10 pF V

IN
OUT

= 0V

= 0V

VPP Supply Capacitance 25 pF VPP = 0V

3

Doc. No. 25005-0A 2/98 F-1

CAT28F010

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified.

Limits

Symbol Parameter Min. Max. Unit Test Conditions

I

LI

I

LO

I

SB1

I

SB2

I

CC1

I

CC2

I

CC3

I

CC4

I

PPS

I

PP1

I

PP2

I

PP3

I

PP4

Input Leakage Current ±1 µAV

= VCC or V

IN

VCC = 5.5V, OE = V

Output Leakage Current ±1 µAV

= VCC or VSS,

OUT

VCC = 5.5V, OE = V

VCC Standby Current CMOS 100 µA CE = VCC ±0.5V,

VCC = 5.5V
VCC Standby Current TTL 1 mA CE = VIH, VCC = 5.5V
VCC Active Read Current 30 mA VCC = 5.5V, CE = VIL,

I

= 0mA, f = 6 MHz

OUT

(1)

VCC Programming Current 15 mA VCC = 5.5V,

Programming in Progress

(1)

VCC Erase Current 15 mA VCC = 5.5V,

Erasure in Progress

(1)

VCC Prog./Erase Verify Current 15 mA VCC = 5.5V, Program or

Erase Verify in Progress
VPP Standby Current ±10 µAV
VPP Read Current 200 µAV

(1)

VPP Programming Current 30 mA VPP = V

PP
PP

= V
= V

PPL
PPH
PPH

Programming in Progress

(1)

VPP Erase Current 30 mA VPP = V

PPH

Erasure in Progress

(1)

VPP Prog./Erase Verify Current 5 mA VPP = V

PPH

Erase Verify in Progress

SS

IH

IH

,

,

, Program or

V

IL

V

ILC

V

OL

V

IH

V

IHC

V

OH1

V

OH2

V

ID

(1)

I

ID

V

LO

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 25005-0A 2/98 F-1

Input Low Level TTL –0.5 0.8 V
Input Low Level CMOS –0.5 0.8 V
Output Low Level 0.45 V IOL = 5.8mA, VCC = 4.5V
Input High Level TTL 2 VCC+0.5 V
Input High Level CMOS VCC*0.7 VCC+0.5 V
Output High Level TTL 2.4 V IOH = –2.5mA, VCC = 4.5V
Output High Level CMOS VCC–0.4 V IOH = –400µA, VCC = 4.5V
A9 Signature Voltage 11.4 13 V A9 = V
A9 Signature Current 200 µAA
VCC Erase/Prog. Lockout Voltage 2.5 V

4

= V

9

ID
ID

SUPPLY CHARACTERISTICS

Limits

Symbol Parameter Min Max. Unit

V
V
V

CC
PPL
PPH

VCC Supply Voltage 4.5 5.5 V
VPP During Read Operations 0 6.5 V
VPP During Read/Erase/Program 11.4 12.6 V

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified.

CAT28F010

28F010-70

(8)

28F010-90

(7)

28F010-12

(7)

JEDEC Standard
Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

t

AVAV

t

ELQV

t

AVQV

t

GLQV

t

AXQX

t

RC

t

CE

t

ACC

t

OE

t

OH

Read Cycle Time 70 90 120 ns
CE Access Time 70 90 120 ns
Address Access Time 70 90 120 ns
OE Access Time 28 35 50 ns
Output Hold from Address 0 0 0 ns

OE/CE Change

t

GLQX

t

ELZX

t

GHQZ

t

EHQZ

t

WHGL

(1)

(1)(6)

t

OLZ

t

LZ

t

DF

t

DF

(1)(6)

(1)(2)
(1)(2)

OE to Output in Low-Z 0 0 0 ns
CE to Output in Low-Z 0 0 0 ns
OE High to Output High-Z 20 20 30 ns
CE High to Output High-Z 30 30 40 ns

- Write Recovery Time 6 6 6 µs
Before Read

Figure 1. A.C. Testing Input/Output Waveform

(3)(4)(5)

Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)

2.4 V

0.45 V

INPUT PULSE LEVELS REFERENCE POINTS

2.0 V

0.8 V

Testing Load Circuit (example)

5108 FHD F03

3.0 V

0.0 V

INPUT PULSE LEVELS REFERENCE POINTS

1.5 V

Testing Load Circuit (example)

5108 FHD F03A

1.3V

1N914

3.3K

DEVICE
UNDER

TEST

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2

CL = 100 pF

OUT

CL INCLUDES JIG CAPACITANCE

5108 FHD F04

DEVICE
UNDER

TEST

1.3V

1N914

3.3K

OUT

CL = 30 pF

CL INCLUDES JIG CAPACITANCE

5

5108 FHD F05

Doc. No. 25005-0A 2/98 F-1

CAT28F010

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified.

28F010-70 28F010-90 28F010-12

\JEDEC Standard

Symbol Symbol Parameter Min. Max Min. Max. Min. Max. Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WHGL

t

WC

t

AS

t

AH

t

DS

t

DH

t

CS

t

CH

t

WP

t

WPH

(2)

- Program Pulse Width 10 10 10 µs

(2)

- Erase Pulse Width 9.5 9.5 9.5 ms

Write Cycle Time 70 90 120 ns
Address Setup Time 0 0 0 ns
Address Hold Time 40 40 40 ns
Data Setup Time 40 40 40 ns
Data Hold Time 10 10 10 ns

CE Setup Time 0 0 0 ns
CE Hold Time 0 0 0 ns
WE Pulse Width 40 40 40 ns
WE High Pulse Width 20 20 20 ns

Write Recovery Time

- Before Read 6 6 6 µs

t

GHWL

Read Recovery Time

- Before Write 0 0 0 µs

t

VPEL

ERASE AND PROGRAMMING PERFORMANCE

-V

Setup Time to CE 100 100 100 ns

PP

(1)

28F010-55 28F010-70 28F010-90 28F010-12

Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max Min. Typ. Max. Unit

Chip Erase Time
Chip Program Time

Note:
(1) Please refer to Supply characteristics for the value of V

switched, V
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/

byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since

most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.

(3)(5)

(3)(4)

can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.

PPL

0.5 10 0.5 10 0.5 10 0.5 10 Sec
2 12.5 2 12.5 2 12.5 2 12.5 Sec

PPH

and V

. The VPP supply can be either hardwired or switched. If VPP is

PPL

Doc. No. 25005-0A 2/98 F-1

6

CAT28F010

FUNCTION TABLE

(1)

Pins

Mode CE OE WE V

Read V
Output Disable V
Standby V
Signature (MFG) V
Signature (Device) V
Program/Erase V
Write Cycle V
Read Cycle V

IL
IL

IH

IL
IL
IL
IL
IL

V

IL

V

IH

V

IH

V

IH

XXV

V

IL

V

IL

V

IH

V

IH

V

IL

V

IH

V

IH

V

IL

V

IL

V

IH

PP

V

PPL

X High-Z

PPL

X 31H A0 = VIL, A9 = 12V
X B4H A0 = VIH, A9 = 12V

V

PPH

V

PPH

V

PPH

I/O Notes

D

OUT

High-Z

D

D
D

OUT

IN
IN

See Command Table
During Write Cycle
During Write Cycle

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. The command register can be altered
only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.

Pins

First Bus Cycle Second Bus Cycle

Mode Operation Address D

IN

Set Read Write X 00H Read A

Operation Address D

IN

IN

D

D

OUT

OUT

Read Sig. (MFG) Write X 90H Read 00 31H
Read Sig. (Device) Write X 90H Read 01 B4H
Erase Write X 20H Write X 20H
Erase Verify Write A

IN

Program Write X 40H Write A

A0H Read X D

IN

D

IN

Program Verify Write X C0H Read X D
Reset Write X FFH Write X FFH

Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, V

PPL

, V

PPH

)

OUT

OUT

7

Doc. No. 25005-0A 2/98 F-1

CAT28F010

READ OPERATIONS

Read Mode

A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
the memory location corresponding to the state of the 17
address pins. The respective timing waveforms for the
read operation are shown in Figure 3. Refer to the AC
Read characteristics for specific timing parameters.

Signature Mode

The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).

The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
and applying the required high voltage on address pin A
while all other address lines are held at VIL.

A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O7:

CATALYST Code = 00110001 (31H)

A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.

28F010 Code = 1011 0100 (B4H)

Standby Mode

With CE at a logic-high level, the CAT28F010 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con­sumption. The outputs are placed in a high-impedance
state.

9

Figure 3. A.C. Timing for Read Operation

POWER UP

ADDRESSES

CE (E)

OE (G)

WE (W)

HIGH-Z

DATA (I/O)

STANDBY DEVICE AND

ADDRESS SELECTION

t

WHGL

t

GLQX

ADDRESS STABLE

t

AVAV

(t

)

OLZ

t

(tLZ)

ELQX

t

(t

AVQV

ACC

OUPUTS

ENABLED

(tRC)

t

GLQV

)

(tOE)

DATA VALID STANDBY

t

EHQZt(DF

t

GHQZ

t

(tCE)

ELQV

OUTPUT VALID

t

AXQXt(OH

POWER DOWN

)

(tDF)

)

HIGH-Z

28F010 F05

Doc. No. 25005-0A 2/98 F-1

8

CAT28F010

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

V

CC

V

PP

t

WC

t

WC

t

RC

t

CS

t

CH

t

CS

t

CH

t

CH

t

EHQZ

t

DF

t

GHWL

t

WPH

t

WHWH2

t

WHGL

t

WP

t

DS

HIGH-Z

DATA IN
= 20H

DATA IN
= A0H

VALID

DATA OUT

t

DH

t

WP

t

DH

t

DS

t

DS

t

WP

t

DH

t

OLZ

t

OE

t

OH

t

LZ

t

CE

t

VPEL

V

PPH

V

PPL

0V

5.0V

VCC POWER-UP

& STANDBY

SETUP ERASE

COMMAND

ERASE

COMMAND

ERASING ERASE VERIFY

COMMAND

ERASE

VERIFICATION

VCC POWER-DOWN/

STANDBY

t

AS

t

AH

DATA IN
= 20H

t

WC

WRITE OPERATIONS

The following operations are initiated by observing the
sequence specified in the Write Command Table.

Read Mode

The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.

Figure 4. A.C. Timing for Erase Operation

Signature Mode

An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register while keeping
VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.

CATALYST Code = 00110001 (31H)

A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.

28F010 Code = 1011 0100 (B4H)

9

28F010 F11

Doc. No. 25005-0A 2/98 F-1

CAT28F010

Figure 5. Chip Erase Algorithm

START ERASURE

APPLY V

PROGRAM ALL

BYTES TO 00H

WRITE ERASE

SETUP COMMAND

WRITE ERASE

PPH

INITIALIZE
ADDRESS

INITIALIZE

PLSCNT = 0

COMMAND

(1)

BUS

OPERATION

STANDBY

WRITE

WRITE

COMMAND COMMENTS

VPP RAMPS TO V

(OR VPP HARDWIRED)

ALL BYTES SHALL BE

PROGRAMMED TO 00

BEFORE AN ERASE

OPERATION

INITIALIZE ADDRESS

PLSCNT = PULSE COUNT

ERASE

ERASE

ACTUAL ERASE

NEEDS 10ms PULSE,

DATA = 20H

DATA = 20H

DATA = 20H

PPH

INCREMENT

ADDRESS

TIME OUT 10ms

WRITE ERASE

VERIFY COMMAND

TIME OUT 6µs

READ DATA

FROM DEVICE

DATA =

FFH?

NO

LAST

ADDRESS?

WRITE READ

COMMAND

APPLY V

YES

YES

PPL

NO

NO

INC PLSCNT

1000

= 3000 ?

YES

APPLY V

PPL

WRITE

READ

STANDBY

WRITE

STANDBY

ERASE

VERIFY

READ

WAIT

ADDRESS = BYTE TO VERIFY

STOPS ERASE OPERA TION

READ BYTE TO

VERIFY ERASURE

COMPARE OUTPUT TO FF

INCREMENT PULSE COUNT

RESETS THE REGISTER

FOR READ OPERATION

VPP RAMPS TO V

(OR VPP HARDWIRED)

40H;

DATA = 20H;

A0H

WAIT

DATA = 00H

PPL

ERASURE

COMPLETED

ERASE
ERROR

Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Doc. No. 25005-0A 2/98 F-1

10

5108 FHD F10

CAT28F010

Erase Mode

During the first Write cycle, the command 20H is written
into the command register. In order to commence the
erase operation, the identical command of 20H has to be
written again into the register. This two-step process
ensures against accidental erasure of the memory con­tents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H) is sent to the command register. During this cycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci­fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.

Figure 6. A.C. Timing for Programming Operation

VCC POWER-UP

& STANDBY

SETUP PROGRAM

COMMAND

LATCH ADDRESS

& DATA

PROGRAMMING

Erase-Verify Mode

The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.

Programming Mode

The programming operation is initiated using the pro­gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat­ing the need for a maximum program timing specifica­tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.

PROGRAM

VERIFY

COMMAND

PROGRAM

VERIFICATION

VCC POWER-DOWN/

STANDBY

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

V

CC

V

PP

5.0V
0V
V

PPH

V

PPL

t

GHWL

HIGH-Z

t

t

DS

t

VPEL

WC

t

t

t

CH

WP

t

AS

CS

t

WPH

DATA IN
= 40H

t

DH
t

DS

t

AH

t

WP

DATA IN

t

CH

t

CS

t

WHWH1

t

DH

t

WP

t

t

WC

DS

t

DH

DATA IN
= C0H

t

CH

t

WHGL

t

OE

t

OLZ

t
t

LZ
CE

t

RC

VALID

DATA OUT

t

EHQZ

t

DF

t

OH

28F010 F08

11

Doc. No. 25005-0A 2/98 F-1

CAT28F010

Figure 7. Programming Algorithm

START

PROGRAMMING

APPLY V

PLSCNT = 0

WRITE SETUP

PROG. COMMAND

WRITE PROG. CMD

ADDR AND DAT A

TIME OUT 10µs

PPH

INITIALIZE
ADDRESS

(1)

BUS

OPERATION

STANDBY

1ST WRITE

CYCLE

2ND WRITE

CYCLE

COMMAND COMMENTS

VPP RAMPS TO V

(OR VPP HARDWIRED)

INITIALIZE ADDRESS

INITIALIZE PULSE COUNT

PLSCNT = PULSE COUNT

WRITE

SETUP

PROGRAM

DATA = 40H

VALID ADDRESS AND DA T A

WAIT

PPH

INCREMENT

ADDRESS

WRITE PROGRAM

VERIFY COMMAND

TIME OUT 6µs

READ DATA

FROM DEVICE

VERIFY

DATA ?

NO

LAST

ADDRESS?

WRITE READ

COMMAND

APPLY V

YES

YES

PPL

NO

INC

PLSCNT

= 25 ?

APPLY V

NO

YES

PPL

1ST WRITE

CYCLE

READ

STANDBY

1ST WRITE

CYCLE

STANDBY

PROGRAM

VERIFY

READ

DATA = C0H

WAIT

READ BYTE TO VERIFY

PROGRAMMING

COMPARE DATA OUTPUT

TO DATA EXPECTED

DATA = 00H

SETS THE REGISTER FOR

READ OPERATION

VPP RAMPS TO V

(OR VPP HARDWIRED)

PPL

PROGRAMMING

COMPLETED

Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Doc. No. 25005-0A 2/98 F-1

PROGRAM

ERROR

12

5108 FHD F06

CAT28F010

ADDRESSES

WE (E)

OE (G)

CE (W)

DATA (I/O)

V

CC

V

PP

t

WC

t

WC

t

RC

t

AVEL

t

ELAX

t

WLEL

t

WLEL

t

EHQZ

t

DF

t

GHEL

t

EHEL

t

EHEH

t

EHGL

t

ELEH

HIGH-Z

DATA IN
= 40H

DATA IN

DATA IN
= C0H

VALID

DATA OUT

t

EHDX

t

OLZ

t

OE

t

OH

t

LZ

t

CE

t

VPEL

V

PPH

V

PPL

0V

5.0V

VCC POWER-UP

& STANDBY

SETUP PROGRAM

COMMAND

LATCH ADDRESS

& DATA

PROGRAMMING

PROGRAM

VERIFY

COMMAND

PROGRAM

VERIFICATION

VCC POWER-DOWN/

STANDBY

t

WLEL

t

EHWH

t

EHWH

t

EHWH

t

ELEH

t

DVEH

t

DVEH

t

DVEH

t

EHDX

t

EHDX

Program-Verify Mode

A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program­verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.

Abort/Reset

An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.

Figure 8. Alternate A.C. Timing for Program Operation

POWER UP/DOWN PROTECTION

The CAT28F010 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and V

CC

may power up in any order. Additionally VPP may be
hardwired to V

independent of the state of VCC and

PPH

any power up/down cycling. The internal command
register of the CAT28F010 is reset to the Read Mode on
power up.

POWER SUPPLY DECOUPLING

To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.

(W)

(E)

13

28F010 F10

Doc. No. 25005-0A 2/98 F-1

CAT28F010

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified.

28F010-70 28F010-90 28F010-12
JEDEC Standard
Symbol Symbol Parameter Min. Max Min. Max Min. Max. Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

EHGL

t
t
t
t
t

WC
AS
AH
DS
DH

Write Cycle Time 70 90 120 ns
Address Setup Time 0 0 0 ns
Address Hold Time 40 40 40 ns
Data Setup Time 40 40 40 ns
Data Hold Time 10 10 10 ns
Write Recovery Time

- Before Read 0 0 0 µs

t

GHEL

Read Recovery Time

- Before Write 0 0 0 µs

t

WLEL

t

EHWH -

t

ELEH

t

EHEL

t

VPEL

t

WS

WE Setup time Before CE 000ns
WE Hold Time After CE 0 00ns

t

CP

t

CPH

-V

Write Pulse Width 40 40 40 ns
Write Pulse Width High 20 20 20 ns

Setup Time to CE Low 100 100 100 ns

PP

ORDERING INFORMATION

Prefix Device # Suffix

28F010 N

Product
Number

Optional
Company ID

IT

Temperature Range

Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚C to +105˚C)*

Package

N: PLCC
P: PDIP
T: TSOP (8mmx20mm)
TR: TSOP (Reverse Pinout)

-90CAT

Tape & Reel

T: 500/Reel

Speed

70: 70ns
90: 90ns
12: 120ns

* -40˚ to +125˚ is available upon request.

Note:
(1) The device used in the above example is a CAT28F010NI-90T(PLCC, Industrial Temperature, 90 ns access time, Tape & Reel).

Doc. No. 25005-0A 2/98 F-1

14

28F010 F12