Datasheet CAT28C513N-12T, CAT28C513HNI-15T, CAT28C513HNA-15T, CAT28C513HNA-12T, CAT28C513HN-15T Datasheet (CTLST)
...
1
Advanced
CAT28C512/513
512K-Bit CMOS PARALLEL E2PROM
FEATURES
■ Fast Read Access Times: 120/150 ns
■ Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
■ Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
■ Fast Write Cycle Time:
–5ms Max
■ CMOS and TTL Compatible I/O
■ Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
■ End of Write Detection:
–Toggle Bit
–
DATADATA
DATADATA
DATA Polling
■ Hardware and Software Write Protection
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel E2PROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin
TSOP packages.
BLOCK DIAGRAM
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOL TAGE
GENERAT OR
A7–A
15
CE
OE
WE
A0–A
6
I/O0–I/O
7
I/O BUFFERS
65,536 x 8
E2PROM
ARRAY
128 BYTE PAGE
REGISTER
V
CC
DATA POLLING
AND
TOGGLE BIT
Doc. No. 25074-00 2/98
AdvancedCAT28C512/513
2
Doc. No. 25074-00 2/98
PIN CONFIGURATION
TSOP Package (10mm X 14mm) (T14)
PLCC Package (N)
DIP Package (P)
PIN FUNCTIONS
Pin Name Function
A0–A
15
Address Inputs
I/O0–I/O
7
Data Inputs/Outputs
CE Chip Enable
OE Output Enable
Pin Name Function
WE Write Enable
V
CC
5V Supply
V
SS
Ground
NC No Connect
PLCC Package (N)
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O
6
I/O
5
I/O
4
I/O
2
A
1
A
2
V
CC
WE
A
8
A
9
A
11
OE
A
7
A
6
A
5
A
4
A
3
A
10
I/O
7
A
12
16
15
CE
I/O
3
I/O
1
I/O
0
A
0
A
14
NC
NC
NC
NC
NC
NC
NC
A
15
NC
NC
V
SS
NC
NC
29
30
31
32
33
34
35
36
37
38
39
40
I/O
2
V
SS
I/O
6
I/O
5
131420
19
18
17
9
10
11
12
24
23
22
21
A
1
A
0
I/O
0
I/O
1
OE
A
10
CE
I/O
7
A
5
A
4
A
3
A
2
5
6
7
8
1
2
3
4
A
14
A
12
A
7
A
6
A
9
A
11
28
27
26
25
V
CC
WE
A
13
A
8
A
6
A
5
A
4
A
3
5
6
7
8
A
2
A
1
A
0
NC
9
10
11
12
I/O
0
13
A
8
A
9
A
11
29
28
27
26
OE
A
10
CE
25
24
23
22
I/O
7
21
I/O1I/O
2
V
SS
I/O3I/O4I/O
5
14 15 16 17 18 19 20
4321323130
A
7
A12A
15
NC
VCCWE
A
13
I/O
4
I/O
3
16
15
I/O
6
TOP VIEW
NC
A
14
CA T28C512
29
30
31
32
NC
NC
NC
A
15
A
6
A
5
A
4
A
3
5
6
7
8
A
2
A
1
A
0
NC
9
10
11
12
I/O
0
13
A
8
A
9
A
11
29
28
27
26
OE
A
10
CE
25
24
23
22
I/O
7
21
I/O1I/O
2
V
SS
I/O3I/O4I/O
5
14 15 16 17 18 19 20
4321323130
A7A
12
NC
V
CC
WE
A
13
I/O
6
TOP VIEW
NC
A
14
A
15
CA T28C513
TSOP Package (8mmx20mm) (T)
5096 FHD F01
CAT28C512
TOP VIEW
CAT28C512
TOP VIEW
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O
6
I/O
5
I/O
4
I/O
2
A
1
A
2
V
CC
WE
A
8
A
9
A
11
OE
A
7
A
6
A
5
A
4
A
3
A
10
I/O
7
A
12
16
15
CE
I/O
3
I/O
1
I/O
0
A
0
A
14
NC
NC
NC
A
15
29
30
31
32
V
ss
Advanced
CAT28C512/513
3
Doc. No. 25074-00 2/98
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
VCC Current (Operating, TTL) 50 mA CE = OE = VIL, f=6MH
z
All I/O’s Open
I
CCC
(5)
VCC Current (Operating, CMOS) 25 mA CE = OE = V
ILC
, f=6MH
z
All I/O’s Open
I
SB
VCC Current (Standby, TTL) 3 mA CE = VIH, All I/O’s Open
I
SBC
(6)
VCC Current (Standby, CMOS) 200 µA CE = V
IHC
,
All I/O’s Open
I
LI
Input Leakage Current -10 10 µAVIN = GND to V
CC
I
LO
Output Leakage Current -10 10 µAV
OUT
= GND to VCC,
CE = V
IH
V
IH
(6)
High Level Input Voltage 2 VCC +0.3 V
V
IL
(5)
Low Level Input Voltage -1 0.8 V
V
OH
High Level Output Voltage 2.4 V IOH = –400µA
V
OL
Low Level Output Voltage 0.4 V IOL = 2.1mA
V
WI
Write Inhibit Voltage 3.5 V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs)............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
N
END
(1)
Endurance 104 or 10
5
Cycles/Byte MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention 100 Years MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up 100 mA JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(5) V
ILC
= –0.3V to +0.3V.
(6) V
IHC
= VCC –0.3V to VCC +0.3V.
AdvancedCAT28C512/513
4
Doc. No. 25074-00 2/98
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
OUT
ACTIVE
Byte Write (WE Controlled) L H D
IN
ACTIVE
Byte Write (CE Controlled) L H D
IN
ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
C
I/O
(1)
Input/Output Capacitance 10 pF V
I/O
= 0V
C
IN
(1)
Input Capacitance 6 pF VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
28C512/513-12 28C512/513-15
Symbol Parameter Min. Max. Min. Max. Units
t
RC
Read Cycle Time 120 150 ns
t
CE
CE Access Time 120 150 ns
t
AA
Address Access Time 120 150 ns
t
OE
OE Access Time 50 70 ns
t
LZ
(1)
CE Low to Active Output 0 0 ns
t
OLZ
(1)
OE Low to Active Output 0 0 ns
t
HZ
(1)(2)
CE High to High-Z Output 50 50 ns
t
OHZ
(1)(2)
OE High to High-Z Output 50 50 ns
t
OH
(1)
Output Hold from Address Change 0 0 ns
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
Symbol Parameter Min. Max Units
t
PUR
(1)
Power-up to Read Operation 100 µs
t
PUW
(2)
Power-up to Write Operation 5 10 ms
Power-Up Timing
Advanced
CAT28C512/513
5
Doc. No. 25074-00 2/98
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
5096 FHD F04
Figure 1. A.C. Testing Input/Output Waveform(2)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
Figure 2. A.C. Testing Load Circuit (example)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5096 FHD F03
A.C. CHARACTERISTICS, Write Cycle
VCC=5V+10%, unless otherwise specified
28C512/513-12 28C512/513-15
Symbol Parameter Min. Max. Min. Max. Units
t
WC
Write Cycle Time 5 5 ms
t
AS
Address Setup Time 0 0 ns
t
AH
Address Hold Time 50 50 ns
t
CS
CE Setup Time 0 0 ns
t
CH
CE Hold Time 0 0 ns
t
CW
(3)
CE Pulse Time 100 100 ns
t
OES
OE Setup Time 0 0 ns
t
OEH
OE Hold Time 0 0 ns
t
WP
(3)
WE Pulse Width 100 100 ns
t
DS
Data Setup Time 50 50 ns
t
DH
Data Hold Time 0 0 ns
t
INIT
(1)
Write Inhibit Period After Power-up 5 10 5 10 ms
t
BLC
(1)(4)
Byte Load Cycle Time 0.1 100 0.1 100 µs
AdvancedCAT28C512/513
6
Doc. No. 25074-00 2/98
ADDRESS
CE
OE
WE
t
RC
DATA OUT DA TA V ALIDDA TA V ALID
t
CE
t
OE
t
OH
t
AA
t
OHZ
t
HZ
V
IH
HIGH-Z
t
LZ
t
OLZ
DEVICE OPERATION
Read
Data stored in the CAT28C512/513 is transferred to the
data bus when WE is held high, and both OE and CE
are held low. The data bus is set to a high impedance
state when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
OE
WE
DATA OUT
t
AS
DATA IN
DATA VALID
HIGH-Z
t
CS
t
AH
t
CH
t
WC
t
OEH
t
BLC
t
DH
t
DS
t
OES
t
WP
5096 FHD F06
28C512/513 F06
Advanced
CAT28C512/513
7
Doc. No. 25074-00 2/98
Page Write
The page write mode of the CAT28C512/513 (essentially an extended BYTE WRITE mode) allows from 1 to
128 bytes of data to be programmed within a single
E2PROM write cycle. This effectively reduces the bytewrite time by a factor of 128.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 128 byte temporary buffer. The
page address where data is to be written, specified by
bits A7 to A15, is latched on the last falling edge of WE.
Each byte within the page is defined by address bits A
0
to A6 (which can be loaded in any order) during the first
and subsequent write cycles. Each successive byte load
cycle must begin within t
BLC MAX
of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t
BLC MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of t
BLC MAX
for the internal automatic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [
CECE
CECE
CE Controlled]
5096 FHD F07
Figure 6. Page Mode Write Cycle
OE
CE
WE
ADDRESS
I/O
t
WP
t
BLC
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
t
WC
5096 FHD F10
ADDRESS
CE
OE
WE
DATA OUT
t
AS
DATA IN
DATA VALID
HIGH-Z
t
AH
t
WC
t
OEH
t
DH
t
DS
t
OES
t
BLC
t
CH
t
CS
t
CW
AdvancedCAT28C512/513
8
Doc. No. 25074-00 2/98
DATADATA
DATADATA
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O
6
are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature of the CAT28C512/
513, the device offers an additional method for determining the completion of a write cycle. While a write cycle is
in progress, reading data from the device will result in I/
O6 toggling between one and zero. However, once the
write is complete, I/O6 stops toggling and valid data can
be read from the device.
Figure 7. DATA Polling
Figure 8. Toggle Bit
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
ADDRESS
28C512-513 F10
CE
WE
OE
I/O
7
D
IN
= X D
OUT
= X D
OUT
= X
t
OE
t
OEH
t
WC
t
OES
28C512-513 F11
WE
CE
OE
I/O
6
t
OEH
t
OE
t
OES
t
WC
(1)
(1)
Advanced
CAT28C512/513
9
Doc. No. 25074-00 2/98
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
BLC
Max., after SDP activation.
HARDWARE DATA PROTECTION
The following is a list of hardware data protection features that are incorporated into the CAT28C512/513.
(1) VCC sense provides for write protection when V
CC
falls below 3.5V min.
(2) A power on delay mechanism, t
INIT
(see AC characteristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28C512/513 features a software controlled
data protection scheme which, once enabled, requires a
data algorithm to be issued to the device before a write
can be performed. The device is shipped from Catalyst
with the software protection NOT ENABLED (the
CAT28C512/513 is in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
5096 FHD F08 5096 FHD F09
SOFTWARE DATA
PROTECTION ACTIVATED
(12)
WRITE DATA: XX
WRITE LAST BYTE
TO
LAST ADDRESS
TO ANY ADDRESS
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: A0
ADDRESS: 5555
(1)
WRITE DATA:
AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 80
ADDRESS: 5555
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA:
20
ADDRESS: 5555
AdvancedCAT28C512/513
10
Doc. No. 25074-00 2/98
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided.
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
5096 FHD F13
CE
WE
t
WP
AA
5555
55
2AAA
A0
5555
DATA
ADDRESS
t
BLC
t
WC
BYTE OR
PAGE
WRITES
ENABLED
Figure 12. Resetting Software Data Protection Timing
CE
WE
AA
5555
55
2AAA
DATA
ADDRESS
t
WC80
5555
AA
5555
55
2AAA
20
5555
SDP
RESET
DEVICE
UNPROTECTED
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT28C512HNI-15T (100,000 Cycle Endurance, PLCC, Industrial temperature, 150 ns
Access Time, Tape & Reel).
(2) 28C513 is offered only in PLCC package.
28C512/513 F16
5096 FHD F14
Speed
12: 120ns
15: 150ns
Prefix Device # Suffix
28C512
Product
Number
28C512
28C513
CAT
Optional
Company
ID
NI T
Tape & Reel
T: 500/Reel
Package
P: PDIP
N: PLCC
T14: TSOP (10mmx14mm)
T: TSOP (8mmX20mm)
-15
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
H
Endurance
Blank = 10,000 Cycle
H = 100,000 Cycle
* -40˚C to +125˚C is available upon request
Loading...