CTLST CAT25C256U14I-1.8TE13, CAT25C256U14A-TE13, CAT25C256U14-TE13, CAT25C256U14-1.8TE13, CAT25C256SI-TE13 Datasheet
...
CAT25C128/256
128K/256K-Bit SPI Serial CMOS E2PROM
FEATURES
■ 5 MHz SPI Compatible
■ 1.8 to 6.0 Volt Operation
■ Hardware and Software Protection
■ Zero Standby Current
■ Low Power CMOS Technology
■ SPI Modes (0,0 &1,1)
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
■ Self-Timed Write Cycle
■ 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
■ 64-Byte Page Write Buffer
■ Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E2PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
PIN CONFIGURATION
SOIC Package (S, K)
1
8
V
CC
7
HOLD
6
SCK
5
SI
V
CS
SO
WP
SS
2
3
4
SOIC Package (S16)
CS
NC
NC
NC
WP
V
SS
1
2
3414
5
6
710
VCC
HOLDSO
15
NC
13
NC
12
NC
11
NCNC
SCK
98
SI
16
PIN FUNCTIONS
Pin Name Function
SO Serial Data Output
SCK Serial Clock
WP Write Protect
V
CC
V
SS
CS Chip Select
SI Serial Data Input
HOLD Suspends Serial Input
TSSOP Package (U14)
14
1
CS
SO
2
3
NC
NC
4
NC NC
5
WP
6
V
7
SS
13
12
11
10
VCC
HOLD
NC
NC
9
SCK
SI
8
TSSOP Package (U20)
1
NC
CS
2
SO
3
SO
4
5
NC
NC
6
7
WP
V
8
SS
NC
9
10 11
NC
+1.8V to +6.0V Power Supply
Ground
20
19
18
17
16
15
14
13
12
NC
VCC
HOLD
HOLD
NC
NC
SCK
SI
NC
NC
DIP Package (P)
CS
SO
WP
V
SS
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write protection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
BLOCK DIAGRAM
1
8
V
2
3
4
CC
7
HOLD
6
SCK
5
SI
SO
SI
CS
WP
HOLD
SCK
WORD ADDRESS
BUFFERS
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
STATUS
REGISTER
CONTROL LOGIC
XDEC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
E2PROM
ARRAY
DATA IN
STORAGE
HIGH VOL T A GE/
TIMING CONTROL
25C128 F02
NC No Connect
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Note: CAT25C256 not available in 8-Lead S or U packages.
1
Doc. No. 25088-00 1/01
CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
with Respect to V
V
CC
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(1)
.................. –2.0V to +VCC +2.0V
SS
................................ –2.0V to +7.0V
SS
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Lead Soldering Temperature (10 secs)............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
(3)
N
T
V
I
LTH
END
DR
ZAP
(3)
(3)
(3)(4)
Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC1
Power Supply Current 10 mA VCC = 5V @ 5MHz
(Operating Write) SO=open; CS=Vss
I
CC2
I
SB
I
LI
I
LO
Power Supply Current 2 mA VCC = 5.5V
(Operating Read) F
Power Supply Current 0 µA CS = V
= 5MHz
CLK
CC
(Standby) VIN = VSS or V
Input Leakage Current 2 µA
Output Leakage Current 3 µAV
= 0V to VCC,
OUT
CC
CS = 0V
(3)
V
V
V
V
V
V
IL
IH
OL1
OH1
OL2
OH2
(3)
Input Low Voltage -1 VCC x 0.3 V
Input High Voltage VCC x 0.7 V
Output Low Voltage 0.4 V
Output High Voltage VCC - 0.8 V
+ 0.5 V
CC
4.5V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
Output Low Voltage 0.2 V 1.8V≤VCC<2.7V
Output High Voltage VCC-0.2 V IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 25088-00 1/01
2
Figure 1. Sychronous Data Timing
V
IH
CS
V
IL
t
CSS
V
SCK
SO
IH
V
IL
V
IH
SI
V
IL
V
OH
HI-Z
V
OL
t
SU
VALID IN
Note: Dashed Line= mode (1, 1) — — — —
A.C. CHARACTERISTICS (CAT25C128)
t
WH
CAT25C128/256
t
CS
t
CSH
t
WL
t
H
t
RI
t
FI
t
V
t
HO
t
DIS
HI-Z
Limits
Vcc= V
=V
CC
CC
=
1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI
t
FI
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
(1)
(1)
Data Setup Time 100 70 35 ns
Data Hold Time 100 70 35 ns
SCK High Time 250 150 80 ns
SCK Low Time 250 150 80 ns
Clock Frequency DC 1 DC 3 DC 5 MHz
HOLD to Output Low Z 50 50 50 ns
Input Rise Time 2 2 2 µs
Input Fall Time 2 2 2 µs
HOLD Setup Time 250 250 40 ns
HOLD Hold Time 250 250 40 ns
Write Cycle Time 10 10 5 ms
Output Valid from Clock Low 250 250 80 ns
Output Hold Time 0 0 0 ns
Output Disable Time 250 250 100 ns
HOLD to Output High Z 150 150 50 ns
CS High Time 1000 250 100 ns
CS Setup Time 1000 250 100 ns
CL = 50pF
t
CSH
t
WPS
t
WPH
CS Hold Time 1000 250 100 ns
WP Setup Time 50 50 50 ns
WP Hold Time 50 50 50 ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 25088-00 1/01
CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256)
Limits
Vcc= VCC= VCC= VCC =
1.8V-6.0V 2.5V-6.0V 2.7V-6.0V 4.5V-5.5V
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. UNITS
Test
Conditions
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI
t
FI
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
(1)
(1)
Data Setup Time 500 100 70 35 ns
Data Hold Time 500 100 70 35 ns
SCK High Time 2500 250 200 80 ns
SCK Low Time 2500 250 200 80 ns
Clock Frequency DC 0.2 DC 2.0 DC 2.5 DC 5 MHz
HOLD to Output Low Z 100 50 50 50 ns
Input Rise Time 2 2 2 2 µs
Input Fall Time 2 2 2 2 µs
CL = 50pF
HOLD Setup Time 250 100 100 40 ns
HOLD Hold Time 250 100 100 40 ns
Write Cycle Time 10 10 10 5 ms
Output Valid from Clock Low 250 200 200 80 ns
Output Hold Time 0 0 0 0 ns
Output Disable Time 250 200 200 100 ns
HOLD to Output High Z 150 100 100 50 ns
CS High Time 100 100 100 100 ns
CS Setup Time 100 100 100 100 ns
CS Hold Time 100 100 100 100 ns
WP Setup Time 50 50 50 50 ns
WP Hold Time 50 50 50 50 ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25088-00 1/01
4
FUNCTIONAL DESCRIPTION
CSCS
CS: Chip Select
CSCS
CAT25C128/256
The CAT25C128/256 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction register. (The instruction set and the operation codes are
detailed in the instruction set table)
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C128/256. Input data is latched on the rising edge of
the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C128/256. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller
and the 25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
CS is the Chip select pin. CS low enables the CAT25C128/
256 and CS high disables the CAT25C128/256. CS high
takes the SO output pin to high impedance and forces
the device into a Standby Mode (unless an internal write
operation is underway) The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
WPWP
WP: Write Protect
WPWP
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0.
HOLDHOLD
HOLD: Hold
HOLDHOLD
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C128/256 while in the middle
of a serial sequence without having to re-transmit entire
sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
(HOLD should be held high any time this function is not
being used.) HOLD may be tied high directly to Vcc or tied
to Vcc through a resistor. Figure 9 illustrates hold timing
sequence.
INSTRUCTION SET
Instruction Opcode Operation
WREN 0000 0110 Enable Write Operations
WRDI 0000 0100 Disable Write Operations
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 0011 Read Data from Memory
WRITE 0000 0010 Write Data to Memory
5
Doc. No. 25088-00 1/01
CAT25C128/256
STATUS REGISTER
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.
The BPO and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
the user may only read from the protected portion of the
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect feature. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write protected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
STATUS REGISTER
76543210
WPEN X X X BP1 BP0 WEL RDY
BLOCK PROTECTION BITS
Status Register Bits Array Address Protection
BP1 BPO Protected
25C128 25C256
0 0 None None No Protection
0 1 3000-3FFF 6000-7FFF Quarter Array Protection
1 0 2000-3FFF 4000-7FFF Half Array Protection
1 1 0000-3FFF 0000-7FFF Full Array Protection
WRITE PROTECT ENABLE OPERATION
Protected Unprotected Status
WPEN
WPWP
WP WEL Blocks Blocks Register
WPWP
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
Doc. No. 25088-00 1/01
6
CAT25C128/256
DEVICE OPERATION
Write Enable and Disable
The CAT25C128/256 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C128/256, followed by the 16-bit address (the Most Significant Bit is
don’t care for 25C256 and the two most significant bits
are don't care for the 25C128).
Figure 2. WREN Instruction Timing
CS
SK
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (7FFFh for 25C256 and 3FFFh for 25C128) is
reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read
operation is terminated by pulling the CS high. To read
the status register, RDSR instruction should be sent.
The contents of the status register are shifted out on the
SO line. The status register may be read at any time
even during a write cycle.Read sequence is illustrated in
figure 4. Reading status register is illustrated in figure 5.
SI
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SK
SI
SO
Note: Dashed Line= mode (1, 1) — — — —
00000
HIGH IMPEDANCE
00000
HIGH IMPEDANCE
110
100
7
Doc. No. 25088-00 1/01
CAT25C128/256
WRITE Sequence
The CAT25C128/256 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruction must be sent to CAT25C128/256. The device goes
into Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C128/256.
The CS must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Figure 4. Read Instruction Timing
CS
012345678910 2021222324252627282930
SK
OPCODE
SI
00000011
BYTE ADDRESS*
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the most significant bit is don't care for
25C256 and the two most significant bits are don't care
for the 25C128), and then the data to be written. Programming will start after the CS is brought high. The low
to high transition of the CS pin must occur during the
SCK low time, immediately after clocking the least
significant bit of the data. Figure 6 illustrates byte write
sequence.
SO
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
HIGH IMPEDANCE
Figure 5. RDSR Timing
CS
012345678 10911121314
SCK
OPCODE
SI
SO
00
00 1 01
0
HIGH IMPEDANCE
7 6
MSB
DATA OUT
7 6 5 4 3 2 1 0
MSB
DATA OUT
5
4 3 2 1 0
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 25088-00 1/01
8
CAT25C128/256
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) instruction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C128/256 features page write capability.
After the initial byte the host may continue to write up to
64 bytes of data to the CAT25C128/256. After each byte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
Figure 6. Write Instruction Timing
CS
012345678 2122232425262728293031
SK
OPCODE
SI
0 0 0 0 0 0 1 0 ADDRESS
address will remain constant.The only restriction is that
the 64 bytes must reside on the same page. If the
address counter reaches the end of the page and clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written. The CAT25C128/256 is automatically returned
to the write disable state at the completion of the write
cycle. Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
SO
Note: Dashed Line= mode (1, 1) — — — —
HIGH IMPEDANCE
Figure 7. WRSR Timing
CS
012345678 10911121314
SCK
OPCODE
SI
SO
Note: Dashed Line= mode (1, 1) — — — —
00
0000 1
0
HIGH IMPEDANCE
Figure 8. Page Write Instruction Timing
CS
012345678 212223
SK
OPCODE
SI
0 0 0 0 0 0 1 0 ADDRESS
7 6
MSB
24-31
Data
Byte 1
DATA IN
4 3 2 10
5
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
32-39
DATA IN
Data
Byte 2
Data
Byte 3
Data Byte N
7..1
15
0
SO
Note: Dashed Line= mode (1, 1) — — — —
HIGH IMPEDANCE
9
Doc. No. 25088-00 1/01
CAT25C128/256
DESIGN CONSIDERATIONS
The CAT25C128/256 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C128/256 goes into a write disable mode. CS
must be set high after the proper number of clock cycles
to start an internal write cycle. Access to the array during
an internal write cycle is ignored and programming
is continued. On power up, SO is in a high impedance.
If an invalid op code is received, no data will be shifted
into the CAT25C128/256, and the serial output pin (SO)
will remain in a high impedance state until the falling
edge of CS is detected again.
Figure 9.
SCK
HOLD
Note: Dashed Line= mode (1, 1) — — — —
Figure 10.
HOLDHOLD
HOLD Timing
HOLDHOLD
CS
SO
WP WP
WP Timing
WP WP
t
HD
t
CD
t
HZ
t
WPS
t
HD
HIGH IMPEDANCE
t
WPH
t
CD
t
LZ
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 25088-00 1/01
10
t
CSH
ORDERING INFORMATION
Prefix Device # Suffix
CAT25C128/256
CAT
Optional
Company ID
25C256
Product
Number
25C128: 128K
25C256: 256K
Package
P = 8-Pin PDIP
S = 8-Pin SOIC (JEDEC)
S16 = 16-Pin SOIC (JEDEC)
K
I
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Operating V oltage
Blank (V
1.8 (Vcc=1.8 to 6.0V)
- 1.8
TE13
Tape & Reel
TE13: 2000/Reel
=2.5 to 6.0V)
cc
K = 8-Pin SOIC (EIAJ)
U14 = 14-Pin TSSOP
U20 = 20-Pin TSSOP
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 25C256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
11
Doc. No. 25088-00 1/01
Loading...