CTLST CAT25C256U14I-1.8TE13, CAT25C256U14A-TE13, CAT25C256U14-TE13, CAT25C256U14-1.8TE13, CAT25C256SI-TE13 Datasheet

CAT25C128/256

128K/256K-Bit SPI Serial CMOS E2PROM

FEATURES

■ 5 MHz SPI Compatible

■ 1.8 to 6.0 Volt Operation

■ Hardware and Software Protection

■ Zero Standby Current

■ Low Power CMOS Technology

■ SPI Modes (0,0 &1,1)

■ Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

■ 100,000 Program/Erase Cycles

■ 100 Year Data Retention

■ Self-Timed Write Cycle

■ 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP

and 20-Pin TSSOP

■ 64-Byte Page Write Buffer

■ Block Write Protection

– Protect 1/4, 1/2 or all of E2PROM Array

The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E2PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substan­tially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data

PIN CONFIGURATION

SOIC Package (S, K)

1

8

V

CC

7

HOLD

6

SCK

5

SI

V

CS
SO

WP

SS

2
3
4

SOIC Package (S16)

CS

NC
NC
NC

WP

V

SS

1
2
3414

5
6
710

VCC
HOLDSO

15

NC

13

NC

12

NC

11

NCNC
SCK

98

SI

16

PIN FUNCTIONS

Pin Name Function

SO Serial Data Output
SCK Serial Clock
WP Write Protect

V

CC

V

SS

CS Chip Select
SI Serial Data Input
HOLD Suspends Serial Input

TSSOP Package (U14)

14

1

CS

SO

2
3

NC

NC

4

NC NC

5

WP

6

V

7

SS

13
12
11
10

VCC

HOLD

NC
NC

9

SCK
SI

8

TSSOP Package (U20)

1

NC

CS

2

SO

3

SO

4

5

NC
NC

6
7

WP

V

8

SS

NC

9

10 11

NC

+1.8V to +6.0V Power Supply
Ground

20
19
18
17
16
15
14
13
12

NC
VCC

HOLD
HOLD

NC
NC
SCK
SI
NC
NC

DIP Package (P)

CS

SO

WP

V

SS

out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write pro­tection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.

BLOCK DIAGRAM

1

8

V
2
3
4

CC

7

HOLD

6

SCK

5

SI

SO

SI

CS

WP

HOLD

SCK

WORD ADDRESS

BUFFERS

I/O

CONTROL

SPI

CONTROL

LOGIC

BLOCK

PROTECT

LOGIC

STATUS

REGISTER

CONTROL LOGIC

XDEC

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

E2PROM

ARRAY

DATA IN

STORAGE

HIGH VOL T A GE/

TIMING CONTROL

25C128 F02

NC No Connect

© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

Note: CAT25C256 not available in 8-Lead S or U packages.

1

Doc. No. 25088-00 1/01

CAT25C128/256

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

with Respect to V

V

CC

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

(1)

.................. –2.0V to +VCC +2.0V

SS

................................ –2.0V to +7.0V

SS

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(3)

N
T
V
I

LTH

END

DR

ZAP

(3)

(3)

(3)(4)

Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC1

Power Supply Current 10 mA VCC = 5V @ 5MHz
(Operating Write) SO=open; CS=Vss

I

CC2

I

SB

I

LI

I

LO

Power Supply Current 2 mA VCC = 5.5V
(Operating Read) F

Power Supply Current 0 µA CS = V

= 5MHz

CLK

CC

(Standby) VIN = VSS or V
Input Leakage Current 2 µA
Output Leakage Current 3 µAV

= 0V to VCC,

OUT

CC

CS = 0V

(3)

V
V
V
V

V
V

IL
IH
OL1
OH1

OL2
OH2

(3)

Input Low Voltage -1 VCC x 0.3 V
Input High Voltage VCC x 0.7 V
Output Low Voltage 0.4 V
Output High Voltage VCC - 0.8 V

+ 0.5 V

CC

4.5V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA

Output Low Voltage 0.2 V 1.8V≤VCC<2.7V
Output High Voltage VCC-0.2 V IOL = 150µA

IOH = -100µA

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 25088-00 1/01

2

Figure 1. Sychronous Data Timing

V

IH

CS

V

IL

t

CSS

V

SCK

SO

IH

V

IL

V

IH

SI

V

IL

V

OH

HI-Z

V

OL

t

SU

VALID IN

Note: Dashed Line= mode (1, 1) — — — —

A.C. CHARACTERISTICS (CAT25C128)

t

WH

CAT25C128/256

t

CS

t

CSH

t

WL

t

H

t

RI

t

FI

t

V

t

HO

t

DIS

HI-Z

Limits

Vcc= V

=V

CC

CC

=

1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions

t

SU

t

H

t

WH

t

WL

f

SCK

t

LZ

t

RI

t

FI

t

HD

t

CD

t

WC

t

V

t

HO

t

DIS

t

HZ

t

CS

t

CSS

(1)

(1)

Data Setup Time 100 70 35 ns
Data Hold Time 100 70 35 ns
SCK High Time 250 150 80 ns
SCK Low Time 250 150 80 ns
Clock Frequency DC 1 DC 3 DC 5 MHz
HOLD to Output Low Z 50 50 50 ns
Input Rise Time 2 2 2 µs
Input Fall Time 2 2 2 µs

HOLD Setup Time 250 250 40 ns
HOLD Hold Time 250 250 40 ns

Write Cycle Time 10 10 5 ms
Output Valid from Clock Low 250 250 80 ns
Output Hold Time 0 0 0 ns
Output Disable Time 250 250 100 ns

HOLD to Output High Z 150 150 50 ns
CS High Time 1000 250 100 ns
CS Setup Time 1000 250 100 ns

CL = 50pF

t

CSH

t

WPS

t

WPH

CS Hold Time 1000 250 100 ns
WP Setup Time 50 50 50 ns
WP Hold Time 50 50 50 ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

3

Doc. No. 25088-00 1/01

CAT25C128/256

A.C. CHARACTERISTICS (CAT25C256)

Limits

Vcc= VCC= VCC= VCC =

1.8V-6.0V 2.5V-6.0V 2.7V-6.0V 4.5V-5.5V

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. UNITS

Test

Conditions

t

SU

t

H

t

WH

t

WL

f

SCK

t

LZ

t

RI

t

FI

t

HD

t

CD

t

WC

t

V

t

HO

t

DIS

t

HZ

t

CS

t

CSS

t

CSH

t

WPS

t

WPH

(1)
(1)

Data Setup Time 500 100 70 35 ns
Data Hold Time 500 100 70 35 ns
SCK High Time 2500 250 200 80 ns
SCK Low Time 2500 250 200 80 ns
Clock Frequency DC 0.2 DC 2.0 DC 2.5 DC 5 MHz
HOLD to Output Low Z 100 50 50 50 ns
Input Rise Time 2 2 2 2 µs
Input Fall Time 2 2 2 2 µs

CL = 50pF

HOLD Setup Time 250 100 100 40 ns
HOLD Hold Time 250 100 100 40 ns

Write Cycle Time 10 10 10 5 ms
Output Valid from Clock Low 250 200 200 80 ns
Output Hold Time 0 0 0 0 ns
Output Disable Time 250 200 200 100 ns

HOLD to Output High Z 150 100 100 50 ns
CS High Time 100 100 100 100 ns
CS Setup Time 100 100 100 100 ns
CS Hold Time 100 100 100 100 ns
WP Setup Time 50 50 50 50 ns
WP Hold Time 50 50 50 50 ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 25088-00 1/01

4