CTLST CAT24WC17PI-1.8TE13, CAT24WC17PA-TE13, CAT24WC17PA-1.8TE13, CAT24WC17P-TE13, CAT24WC17P-1.8TE13 Datasheet
...
Preliminary
D
OUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E2PROM
V
CC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOL TAGE/
TIMING CONTROL
V
SS
WP
SCL
A
0
A1
A2
SDA
CAT24WC03/05/09/17
2K/4K/8K/16K-Bit Serial E2PROM
FEATURES
■ 400 KHZ I
2
C Bus Compatible*
■ 1.8 to 6.0Volt Operation
■ Low Power CMOS Technology
■ Write Protect Feature
–Top 1/2 Array Protected When WP at V
IH
■ 16-Byte Page Write Buffer
DESCRIPTION
The CAT24WC03/05/09/17 is a 2K/4K/8K/16K-bit Serial
CMOS E2PROM internally organized as 256/512/1024/
2048 words of 8 bits each. Catalyst’s advanced CMOS
technology substantially reduces device power require-
PIN CONFIGURATION
DIP Package (P)
1
A
0
2
A
1
3
A
2
SS
4
V
8
V
CC
7
WP
6
SCL
5
SDA
SOIC Package (J)
A
A
A
V
SS
1
0
2
1
3
2
4
8
V
CC
7
WP
6
SCL
5
SDA
■ Self-Timed Write Cycle with Auto-Clear
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package
■ Commercial, Industrial and Automotive
Temperature Ranges
ments. The CAT24WC03/05/09/17 features a 16-byte
page write buffer. The device operates via the I2C bus
serial interface, has a special write protection feature,
and is available in 8-pin DIP or 8-pin SOIC
BLOCK DIAGRAM
TSSOP Package (U)
A
A
A
V
SS
PIN FUNCTIONS
(** Available for 24WC03 only)
1
0
2
1
3
2
4
SS
8
7
6
5
V
CC
WP
SCL
SDA
Pin Name Function
A0, A1, A2 Device Address Inputs
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V
CC
V
SS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
+1.8V to +6.0V Power Supply
Ground
1
24WCXX F03
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
(1)
........... –2.0V to +V
CC
+ 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
(3)
N
T
V
I
LTH
END
DR
ZAP
(3)
(3)
(3)(4)
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
(5)
I
S
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Power Supply Current 3 mA f
= 100 KHz
SCL
Standby Current (VCC = 5.0V) 0 µAVIN = GND or V
Input Leakage Current 10 µAVIN = GND to V
Output Leakage Current 10 µAV
= GND to V
OUT
Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage (VCC = 3.0V) 0.4 V IOL = 3 mA
Output Low Voltage (VCC = 1.8V) 0.5 V IOL = 1.5 mA
CC
CC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
(3)
C
I/O
C
IN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).
Input/Output Capacitance (SDA) 8 pF V
(3)
Input Capacitance (A0, A1, A2, SCL, WP) 6 pF V
I/O
IN
= 0V
= 0V
CC
Doc. No. 25063-00 2/98 S-1
2
Preliminary
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol Parameter 1.8V, 2.5V 4.5V-5.5V
Min. Max. Min. Max. Units
CAT24WC03/05/09/17
F
SCL
(1)
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
(1)
t
R
(1)
t
F
t
SU:STO
t
DH
(1)
Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns
Power-Up Timing
(1)(2)
Symbol Parameter Max. Units
t
PUR
t
PUW
Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms
Write Cycle Limits
Symbol Parameter Min. Typ. Max Units
t
WR
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
are the delays required from the time VCC is stable until the specified operation can be initiated.
PUW
Write Cycle Time 10 ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 25063-00 2/98 S-1
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