Datasheet CAT24C44SI-TE13, CAT24C44SA-TE13, CAT24C44S-TE13, CAT24C44PI-TE13, CAT24C44PA-TE13 Datasheet (CTLST)
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CAT24C44
256-Bit Serial Nonvolatile CMOS Static RAM
FEATURES
■ Single 5V Supply
■ Infinite E
■ CMOS and TTL Compatible I/O
■ Low CMOS Power Consumption:
2
PROM to RAM Recall
–Active: 3 mA Max.
–Standby: 30 µA Max.
■ Power Up/Down Protection
■ 10 Year Data Retention
DESCRIPTION
The CAT24C44 Serial NVRAM is a 256-bit nonvolatile
memory organized as 16 words x 16 bits. The high
speed Static RAM array is bit for bit backed up by a
nonvolatile E2PROM array which allows for easy transfer of data from RAM array to E2PROM (STORE) and
from E2PROM to RAM (RECALL). STORE operations
are completed in 10ms max. and RECALL operations
typically within 1.5µs. The CAT24C44 features unlimited
RAM write operations either through external RAM
writes or internal recalls from E2PROM. Internal false
■ JEDEC Standard Pinouts:
–8-pin DIP
–8-pin SOIC
■ 100,000 Program/Erase Cycles (E
■ Auto Recall on Power-up
■ Commercial, Industrial and Automotive
2
PROM)
Temperature Ranges
store protection circuitry prohibits STORE operations
when VCC is less than 3.5V (typical) ensuring E2PROM
data integrity.
The CAT24C44 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles (E2PROM) and
has a data retention of 10 years. The device is available
in JEDEC approved 8-pin plastic DIP and SOIC packages.
PIN CONFIGURATION
DIP Package (P)
SK
1
2
DI
3
4
8
7
6
5
V
CC
STORE
RECALL
V
SS
CE
DO
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SOIC Package (S)
1
CE
SK
DI
DO
8
2
7
3
6
4
5
V
CC
STORE
RECALL
V
SS
5157 FHD F01
PIN FUNCTIONS
Pin Name Function
SK Serial Clock
DI Serial Input
DO Serial Data Output
CE Chip Enable
RECALL Recall
STORE Store
V
CC
V
SS
1
+5V
Ground
Doc. No. 25019-0A 2/98 N-1
CAT24C44
BLOCK DIAGRAM
CE
DI
SK
ROW
DECODE
INSTRUCTION
REGISTER
E2PROM ARRAY
STATIC RAM
ARRAY
256-BIT
COLUMN
DECODE
RECALL
STORE
CONTROL
LOGIC
STORE
RECALL
DO
V
CC
V
SS
MODE SELECTION
INSTRUCTION
DECODE
(1)(2)
4-BIT
COUNTER
Software Write Enable Previous Recall
Mode
Hardware Recall
(3)
STORESTORE
STORE
STORESTORE
1 0 NOP X X
RECALLRECALL
RECALL Instruction Latch Latch
RECALLRECALL
Software Recall 1 1 RCL X X
Hardware Store
(3)
0 1 NOP SET TRUE
Software Store 1 1 STO SET TRUE
X = Don’t Care
POWER-UP TIMING
(4)
Symbol Parameter Min. Max. Units
VCCSR VCC Slew Rate 0.5 0.005 V/m
t
pur
Power-Up to Read Operations 200 µs
5157 FHD F09
t
puw
Note:
(1) The store operation has priority over all the other operations.
(2) The store operation is inhibited when VCC is below ≈ 3.5V.
(3) NOP designates that the device is not currently executing an instruction.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25019-0A 2/98 N-1
Power-Up to Write or Store Operation 5 ms
2
CAT24C44
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(2)
.............–2.0 to +VCC +2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Lead Soldering Temperature (10 secs)............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
(1)
N
T
V
I
LTH
END
DR
ZAP
(1)
(1)
(1)(4)
Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 10 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Unit Conditions
I
CCO
Current Consumption (Operating) 3 mA Inputs = 5.5V, TA = 0°C
All Outputs Unloaded
I
SB
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
Current Consumption (Standby) 30 µA CE = V
IL
Input Current 2 µA0 ≤ VIN ≤ 5.5V
Output Leakage Current 10 µA0 ≤ V
High Level Input Voltage 2 V
CC
V
OUT
≤ 5.5V
Low Level Input Voltage 0 0.8 V
High Level Output Voltage 2.4 V IOH = –2mA
Low Level Output Voltage 0.4 V IOL = 4.2mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Parameter Max. Unit Conditions
(1)
C
I/O
(1)
C
IN
Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V
I/O
IN
= 0V
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
3
Doc. No. 25019-0A 2/98 N-1
CAT24C44
A.C. CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Symbol Parameter Min. Max. Units Conditions
F
SK
SK Frequency DC 1 MHz
t
SKH
t
SKL
t
DS
t
DH
t
PD
t
Z
t
CES
t
CEH
t
CDS
SK Positive Pulse Width 400 ns
SK Negative Pulse Width 400 ns CL = 100pF + 1TTL gate
Data Setup Time 400 ns VOH = 2.2V, VOL = 0.65V
Data Hold Time 80 ns VIH = 2.2V, VIL = 0.65V
SK Data Valid Time 375 ns Input rise and fall times = 10ns
CE Disable Time 1 µs
CE Enable Setup Time 800 ns
CE Enable Hold Time 400 ns
CE De-Select Time 800 ns
A.C. CHARACTERISTICS, Store Cycle
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Max. Units Conditions
t
ST
t
STP
t
STZ
Store Time 10 ms CL = 100pF + 1TTL gate
Store Pulse Width 200 ns VOH = 2.2V, VOL = 0.65V
Store Disable Time 100 ns VIH = 2.2V, VIL = 0.65V
A.C. CHARACTERISTICS, Recall Cycle
VCC = 5V ±10%, unless otherwise specified.
Symbol Parameter Min. Max. Units Conditions
t
RCC
t
RCP
t
RCZ
t
ORC
t
ARC
Recall Cycle Time 2.5 µs
Recall Pulse Width 500 ns CL = 100pF + 1TTL gate
Recall Disable Time 500 ns VOH = 2.2V, VOL = 0.65V
Recall Enable Time 10 ns VIH = 2.2V, VIL = 0.65V
Recall Data Access Time 1.5 µs
INSTRUCTION SET
Format
Instruction Start Bit Address OP Code Operation
WRDS 1 XXXX 0 0 0 Reset Write Enable Latch (Disables, Writes and Stores)
STO 1 XXXX 0 0 1 Store RAM Data in E2PROM
WRITE 1 AAAA 0 1 1 Write Data into RAM Address AAAA
WREN 1 XXXX 1 0 0 Set Write Enable Latch (Enables, Writes and Stores)
RCL 1 XXXX 1 0 1 Recall E2PROM Data into RAM
READ 1 AAAA 1 1 X Read Data From RAM Address AAAA
X = Don’t care
A = Address bit
Doc. No. 25019-0A 2/98 N-1
4
CAT24C44
DEVICE OPERATION
The CAT24C44 is intended for use with standard microprocessors. The CAT24C44 is organized as 16 registers
by 16 bits. Seven 8-bit instructions control the device’s
operating modes, the RAM reading and writing, and the
E2PROM storing and recalling. It is also possible to
control the E2PROM store and recall functions in hardware with the STORE and RECALL pins. The CAT24C44
operates on a single 5V supply and will generate, on
chip, the high voltage required during a RAM to E2PROM
storing operation.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin remains in a high impedance state except when
outputting data from the device. The CE (Chip Enable)
pin must remain high during the entire data transfer.
The format for all instructions sent to the CAT24C44 is
a logical ‘1’ start bit, 4 address bits (data read or write
operations) or 4 “Don’t Care” bits (device mode operations), and a 3-bit op code (see Instruction Set). For data
write operations, the 8-bit instruction is followed by 16
bits of data. For data read instructions, DO will come out
of the high impedance state and enable 16 bits of data
to be clocked from the device. The 8th bit of the read
instruction is a “Don’t Care” bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and
from the device: If the CE pin is prematurely deselected
while shifting in an instruction, that instruction will not be
executed, and the shift register internal to the CAT24C44
will be cleared. If there are more than or less than 16
clocks during a memory data transfer, an improper data
transfer will result. The SK clock is completely static
allowing the user to stop the clock and restart it to
resume shifting of data.
Read
Upon receiving a start bit, 4 address bits, and the 3-bit
read command (clocked into the DI pin), the DO pin of
the CAT24C44 will come out of the high impedance state
and the 16 bits of data, located at the address specified
in the instructions, will be clocked out of the device.
When clocking data from the device, the first bit clocked
out (DO) is timed from the falling edge of the 8th clock,
all succeeding bits (D1–D15) are timed from the rising
edge of the clock.
Write
After receiving a start bit, 4 address bits, and the 3-bit
WRITE command, the 16-bit word is clocked into the
device for storage into the RAM memory location specified. The CE pin must remain high during the entire write
operation.
Figure 1. RAM Read Cycle Timing
CE
123456789101112 222324
SK
AX11AAA
DI
DO
1
HIGH-Z
Figure 2. RAM Write Cycle Timing
CE
123456789101112 222324
SK
1
DI
Note:
(1) Bit 8 of READ instruction is “Don’t Care”.
A11AAA 0
(8)
(1)
D
D
D
0
1
D
D
0
1
D
2
3
D
D
2
3
D
14D15
D
13D14D15
D
0
5157 FHD F02
5157 FHD F03
5
Doc. No. 25019-0A 2/98 N-1
CAT24C44
WREN/WRDS
The CAT24C44 powers up in the program disable state
(the “write enable latch” is reset). Any programming
after power-up or after a WRDS (RAM write/E2PROM
store disable) instruction must first be preceded by the
WREN (RAM write/E2PROM store enable) instruction.
Once writing/storing is enabled, it will remain enabled
until power to the device is removed, the WRDS instruction is sent, or an E2PROM store has been executed
Figure 3. Read Cycle Timing
SK CYCLE #
SK
CE
67891011
V
IH
(STO). The WRDS (write/store disable) can be used to
disable all CAT24C44 programming functions, and will
prevent any accidental writing to the RAM, or storing to
the E2PROM.
Data can be read normally from the CAT24C44 regardless of the “write enable latch” status.
t
PD
DI
DO D0 D1 Dn
Figure 4. Write Cycle Timing
SK
CE
DI
t
PD
HIGH-Z
1/F
SK
t
DH
t
SKL
t
CEH
t
SKH
x12n
t
CES
t
DS
t
CDS
t
Z
HIGH-Z
5157 FHD F04
5157 FHD F05
Doc. No. 25019-0A 2/98 N-1
6
RECALLRECALL
RCL/
RECALL
RECALLRECALL
Data is transferred from the E2PROM data memory to
RAM by either sending the RCL instruction or by pulling
the RECALL input pin low. A recall operation must be
performed before the E2PROM store, or RAM write
operations can be executed. Either a hardware or software recall operation will set the “previous recall” latch
internal to the CAT24C44.
POWER-ON RECALL
The CAT24C44 has a power-on recall function that
transfers the E2PROM data to the RAM. After Power-up,
all functions are inhibited for at least 200ns (T
pur
) from
stable Vcc.
STORESTORE
STO/
STORE
STORESTORE
Data in the RAM memory area is stored in the E2PROM
memory either by sending the STO instruction or by
pulling the STORE input pin low. As security against any
CAT24C44
inadvertent store operations, the following conditions
must each be met before data can be transferred into
nonvolatile storage:
• The “previous recall” latch must be set (either a
software or hardware recall operation).
• The “write enable” latch must be set (WREN
instruction issued).
• STO instruction issued or STORE input low.
During the store operation, all other CAT24C44 functions are inhibited. Upon completion of the store operation, the “write enable” latch is reset. The device also
provides false store protection whenever VCC falls below
a 3.5V level. If VCC falls below this level, the store
operation is disabled and the “write enable” latch is
reset.
Figure 5. Recall Cycle Timing
RECALL
DO
Figure 6. Hardware Store Cycle Timing
STORE
DO
t
RCZ
t
STZ
t
RCP
HIGH-Z
t
STP
t
RCC
t
ORC
t
ST
HIGH-Z
t
ARC
UNDEFINED DATA
VALID DATA
5157 FHD F06
5157 FHD F07
7
Doc. No. 25019-0A 2/98 N-1
CAT24C44
Figure 7. Non-Data Operations
CE
12345678
SK
DI
1
XXXX
OP-CODE
ORDERING INFORMATION
Prefix Device # Suffix
CAT
Optional
Company ID
* -40˚ to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 24C44SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
24C44 S I -TE13
Product
Number
Temperature Range
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Package
P: PDIP
S: SOIC (JEDEC)
5157 FHD F08
Tape & Reel
TE13: 2000/Reel
24C44 F11
Doc. No. 25019-0A 2/98 N-1
8
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