CTLST CAT24C642PI-45TE13, CAT24C642PI-42TE13, CAT24C642PI-30TE13, CAT24C642PI-28TE13, CAT24C642PI-25TE13 Datasheet
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9-1
24C1601 BLOCK
CAT24C321/322(32K), CAT24C641/642(64K)
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
DESCRIPTION
The CAT24CXXX is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C321/322(32K)
and 24C641/642(64K) feature a I2C Serial CMOS
EEPROM. Catalyst's advanced CMOS technology substantially reduces device power requirements. The
24CXXX features a 32-byte page and is available in 8-pin
DIP or 8-pin SOIC packages.
The reset function of the 24CXXX protects the system
during brown out and power up/down conditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. 24CXXX features
active low reset on pin 2 and active high reset on pin 7.
24C321/641 features watchdog timer on the SDA line.
24C322/642 does not feature the watchdog timer function.
Pin Name Function
SDA Serial Data/Address
RESET/RESET Reset I/O
SCL Clock Input
Vcc Power Supply
DC Do not Connect
V
SS
Ground
WP Write Protect
PIN FUNCITONS
PIN CONFIGURATION
24C321/322*
24C641/642*
BLOCK DIAGRAM
*All products offered in P and J packages
Advanced
FEATURES
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
■ Watchdog Timer on SDA for 24C321/641
■ Programmable Reset Threshold
■ 400 KHz I
2
C Bus Compatible
■ 2.7 to 6 Volt Operation
■ Low Power CMOS Technology
■ 32 - Byte Page Write Buffer
■ Built-in inadvertent write protection
— V
CC
Lock Out
■ Active High or Low Reset Outputs
— Precision Power Supply Voltage Monitoring
— 5V, 3.3V and 3V options
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 8-Pin DIP or 8-Pin SOIC
■ Commercial, Industrial and Automotive
Temperature Ranges
Doc. No. 25083-00 12/98
DC
V
CC
RESET
SCL
SDA
RESET
WP
V
SS
D
OUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/ST OP
LOGIC
E2PROM
V
CC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOL T A GE/
TIMING CONTROL
V
SS
WP
SDA
RESET Controller
High
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
Only for
24C321/641
RESET/RESET
WATCHDOG
CAT24C321/322/641/642
2
Advanced
Doc. No. 25083-00 12/98
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias....................–55°C to +125°C
Storage Temperature........................ –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
..............–2.0V to +V
CC
+ 2.0V
VCC with Respect to Ground..................–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)1.0W.................................1.0W
Lead Soldering Temperature (10 secs)...............300°C
Output Short Circuit Current
(2)
..........................100mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
N
END
(3)
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention 100 Years MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-up 100 mA JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
Power Supply Current 3 mA f
SCL
= 100 KHz
Isb Standby Current 40 µA Vcc=3.3V
50 µA Vcc=5
ILI Input Leakage Current 2 µA VIN=GND or V
CC
ILO Output Leakage Current 10 µA VIN=GND or V
CC
V
IL
Input Low Voltage –1 VCC x 0.3 V
V
IH
Input High Voltage VCC x 0.7 VCC + 0.5 V
V
OL
Output Low Voltage (SDA) 0.4 V IOL = 3 mA ,VCC=3.0V
Limits
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
C
I/O
(3)
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
(3)
Input Capacitance (SCL) 6 pF V
IN
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
CAT24C321/322/641/642
3
Advanced
Doc. No. 25083-00 12/98
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter VCC=2.7V - 6V VCC=4.5V - 5.5V
Min. Max. Min. Max. Units
F
SCL
Clock Frequency 100 400 kHz
T
I
(1)
Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time 4 0.6 µs
t
LOW
Clock Low Period 4.7 1.2 µs
t
HIGH
Clock High Period 4 0.6 µs
t
SU:STA
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time 0 0 ns
t
SU:DAT
Data In Setup Time 50 50 ns
t
R
(1)
SDA and SCL Rise Time 1 0.3 µs
t
F
(1)
SDA and SCL Fall Time 300 300 ns
t
SU:STO
Stop Condition Setup Time 4 0.6 µs
t
DH
Data Out Hold Time 100 100 ns
Power-Up Timing
(1)(2)
Symbol Parameter Max. Units
t
PUR
Power-up to Read Operation 1 ms
t
PUW
Power-up to Write Operation 1 ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol Parameter Min. Typ. Max Units
t
WR
Write Cycle Time 10 ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
CAT24C321/322/641/642
4
Advanced
Doc. No. 25083-00 12/98
Symbol Parameter Min. Max. Units
t
GLITCH
Glitch Reject Pulse Width 100 ns
V
RT
Reset Threshold Hystersis 15 mV
V
OLRS
Reset Output Low Voltage (I
OLRS
=1mA) 0.4 V
V
OHRS
Reset Output High Voltage Vcc-0.75 V
Reset Threshold (Vcc=5V) 4.50 4.75
(24CXXX-45)
Reset Threshold (Vcc=5V) 4.25 4.50
(24CXXX-42)
Reset Threshold (Vcc=3.3V) 3.00 3.15
(24CXXX-30)
Reset Threshold (Vcc=3.3V) 2.85 3.00
(24CXXX-28)
Reset Threshold (Vcc=3V) 2.55 2.70
(24CXXX-25)
t
PURST Power-Up Reset Timeout 130 270 ms
t
RPD V
TH
to RESET Output Delay 5 µs
V
RVALID
RESET Output Valid 1 V
RESET CIRCUIT CHARACTERISTICS
V
V
TH
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