CTLST CAT24C161JA-45TE13, CAT24C161JA-42TE13, CAT24C161JA-30TE13, CAT24C161JA-28TE13, CAT24C161JA-25TE13 Datasheet
...
Advanced
CA T24C161/162(16K), CA T24C081/082(8K)
CA T24C041/042(4K), CA T24C021/022(2K)
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
■ Watchdog Timer on SDA for 24CXX1
■ Programmable Reset Threshold
■ 400 KHz I
2
C Bus Compatible
■ 2.7 to 6 Volt Operation
■ Low Power CMOS Technology
■ 16 - Byte Page Write Buffer
■ Built-in inadvertent write protection
— V
Lock Out
CC
DESCRIPTION
The CAT24CXXX is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C161/162(16K),
24C081/082(8K), 24C041/042(4K) and 24C021/022(2K)
feature a I2C Serial CMOS EEPROM. Catalyst's advanced CMOS technology substantially reduces device
power requirements. The 24CXXX features a 16-byte
page and is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
24CXX1/XX2*
DC
RESET
WP
V
SS
V
CC
RESET
SCL
SDA
■ Active High or Low Reset Outputs
— Precision Power Supply Voltage Monitoring
— 5V, 3.3V and 3V options
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 8-Pin DIP or 8-Pin SOIC
■ Commercial, Industrial and Automotive
Temperature Ranges
The reset function of the 24CXXX protects the system
during brown out and power up/down conditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. 24CXXX features
active low reset on pin 2 and active high reset on pin 7.
24CXX1 features watchdog timer on the SDA line.
24CXX2 does not feature the watchdog timer function.
BLOCK DIAGRAM
EXTERNAL LOAD
D
OUT
ACK
V
CC
V
SS
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
*All products offered in P and J packages
PIN FUNCTIONS
Pin Name Function
SDA Serial Data/Address
RESET/RESET Reset I/O
SCL Clock Input
Vcc Power Supply
DC Do Not Connect
V
SS
WP Write Protect
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Ground
Only for
24C161
START/ST OP
LOGIC
CONTROL
LOGIC
RESET Controller
WATCHDOG
XDEC
High
Precision
Vcc Monitor
RESET/RESET
E2PROM
DATA IN STORAGE
HIGH VOL T A GE/
TIMING CONTROL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
Doc. No. 25079-00 1/98 M-1
SCL
24C1601 BLOCK
SDA
WP
1
CAT24CXX1/XX2
Advanced
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias....................–55°C to +125°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Storage Temperature........................ –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
..............–2.0V to +V
CC
+ 2.0V
VCC with Respect to Ground..................–2.0V to +7.0V
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Package Power Dissipation
Capability (Ta = 25°C)1.0W.................................1.0W
Lead Soldering Temperature (10 secs)...............300°C
Output Short Circuit Current
(2)
..........................100mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
(3)
N
END
(3)
T
DR
(3)
V
ZAP
(3)(4)
I
LTH
D.C. OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
Power Supply Current 3 mA f
= 100 KHz
SCL
Isb Standby Current 40 µA Vcc=3.3V
50 µA Vcc=5
ILI Input Leakage Current 2 µA VIN=GND or V
ILO Output Leakage Current 10 µA VIN=GND or V
V
V
V
IL
IH
OL
Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage (SDA) 0.4 V IOL = 3 mA ,VCC=3.0V
CC
CC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
(3)
C
I/O
(3)
C
IN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (SCL) 6 pF V
I/O
IN
= 0V
= 0V
Doc. No. 25079-00 1/98 M-1
2
Advanced
CAT24CXX1/XX2
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter VCC=2.7V - 6V VCC=4.5V - 5.5V
Min. Max. Min. Max. Units
F
SCL
(1)
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
(1)
t
R
(1)
t
F
t
SU:STO
t
DH
(1)
Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns
Power-Up Timing
(1)(2)
Symbol Parameter Max. Units
t
PUR
t
PUW
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
are the delays required from the time VCC is stable until the specified operation can be initiated.
PUW
Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms
Write Cycle Limits
Symbol Parameter Min. Typ. Max Units
t
WR
Write Cycle Time 10 ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
3
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
RESET CIRCUIT CHARACTERISTICS
Symbol Parameter Min. Max. Units
Advanced
t
GLITCH
V
RT
V
OLRS
V
OHRS
Glitch Reject Pulse Width 100 ns
Reset Threshold Hystersis 15 mV
Reset Output Low Voltage (I
=1mA) 0.4 V
OLRS
Reset Output High Voltage Vcc-0.75 V
Reset Threshold (Vcc=5V) 4.50 4.75
(24CXXX-45)
Reset Threshold (Vcc=5V) 4.25 4.50
(24CXXX-42)
V
TH
Reset Threshold (Vcc=3.3V) 3.00 3.15
(24CXXX-30)
Reset Threshold (Vcc=3.3V) 2.85 3.00
(24CXXX-28)
Reset Threshold (Vcc=3V) 2.55 2.70
(24CXXX-25)
t
PURST Power-Up Reset Timeout 130 270 ms
t
RPD V
V
RVALID
to RESET Output Delay 5 µs
TH
RESET Output Valid 1 V
V
Doc. No. 25079-00 1/98 M-1
4
Advanced
PIN DESCRIPTIONS
CAT24CXX1/XX2
WP: WRITE PROTECT
If the pin is tied to VCC the entire memory array becomes
Write Protected (READ only). When the pin is tied to V
SS
or left floating normal read/write operations are allowed
to the device.
SCL: SERIAL CLOCK
The serial clock input clocks all data transferred into or
out of the device.
RESET/
RESETRESET
RESET: RESET I/O
RESETRESET
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins the
device will initiate and maintain a reset condition for
approximately 200ms. RESET pin must be connected
through a pull-down and RESET pin must be connected
through a pull-up device.
SDA: SERIAL DATA/ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs. In the 24CXX1, the
SDA line is also used as the Watchdog Timer Monitor.
DEVICE OPERATION
Reset Controller Description
The CAT24CXXX provides a precision RESET controller that ensures correct system operation during brownout and power-up/down conditions. It is configured
with open drain RESET outputs. During power-up, the
RESET outputs remain active until VCC reaches the
V
threshold and will continue driving the outputs for
TH
approximately 200ms (t
the t
timeout interval, the device will cease to drive
PURST
) after reaching V
PURST
TH.
After
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/pull down
devices. During power-down, the RESET outputs will
begin driving active when VCC falls below V
TH.
The
RESET outputs will be valid so long as VCC is >1.0V
(V
RVALID
).
The RESET pins are I/Os; therefore, the CAT24CXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 24CXXX will initiate a reset timeout
after detecting a high and the RESET input in the
24CXXX will initiate a reset timeout after detecting a low.
Watchdog Timer
The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the
CAT24CXX1 will respond with a reset signal after a timeout interval of 1.6 seconds for lack of activity. 24CXX1
is designed with the Watchdog Timer feature on the SDA
input. For the 24CXX1, if the microcontroller does not
toggle the SDA input pin within 1.6 seconds the Watchdog Timer times out. This will generate a reset condition
on reset outputs. The Watchdog Timer is cleared by any
transition on SDA.
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared. 24CXX2 does
not feature the Watchdog Timer function.
Figure 1. RESET Output Timing
V
TH
V
RVALID
V
CC
RESET
RESET
t
PURST
t
GLITCH
t
RPD
5
t
PURST
t
RPD
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
Advanced
Hardware Data Protection
The 24CXXX is designed with the following hardware
data protection features to provide a high degree of data
integrity.
(1) The 24CXXX features a WP pin. When WP pin is tied
high the entire memory array becomes write protected
(read only).
(2) The VCC sense provides write protection when V
falls below the reset threshold value (VTH). The VCC lock
out inhibits writes to the serial EEPROM whenever V
falls below (power down) VTH or until VCC reaches the
reset threshold (power up) VTH.
Figure 2. Bus Timing
t
F
t
LOW
SCL
t
SU:STA
SDA IN
SDA OUT
t
HD:STA
t
AA
t
HIGH
t
HD:DAT
CC
CC
Reset Threshold Voltage
From the factory the 24CXXX is offered in five different
variations of reset threshold voltages. They are 4.50-
4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-
2.70V. To provide added flexibility to design engineers
using this product, the 24CXXX is designed with an
additional feature of programming the reset threshold
voltage. This allows the user to change the existing
reset threshold voltage to one of the other four reset
threshold voltages. Once the reset threshold voltage is
selected it will not change even after cycling the power,
unless the user uses the programmer to change the
reset threshold voltage. However, the programming
function is available only through third party programmer
manufacturers. Please call Catalyst for a list of programmer manufacturers who support this function.
t
R
t
LOW
t
SU:STO
t
BUF
t
DH
t
SU:DAT
Figure 3. Write Cycle Timing
SCL
SDA
BYTE n
Figure 4. Start/Stop Timing
SDA
SCL
ACK8TH BIT
START BIT
STOP
CONDITION
t
WR
START
CONDITION
STOP BIT
ADDRESS
Doc. No. 25079-00 1/98 M-1
6
Advanced
CAT24CXX1/XX2
FUNCTIONAL DESCRIPTION
The CAT24CXXX supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24CXXX
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver, but the Master device controls which mode is
activated.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24CXXX monitors the
SDA and SCL lines and will not respond until this
condition is met.
Figure 5. Acknowledge Timing
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular slave device it is requesting. The four most significant
bits of the 8-bit slave address are fixed as 1010.
The next three bits (Fig. 6) define memory addressing.
For the 24C021/022, the three bits are don't care. For
the 24C041/042, the next two bits are don't care and the
third bit is the high order address bit. For the 24C081/
082, the next bit is don't care and the successive bits
define the higher order address bits. For the 24C161/
162 the three bits define higher order bits.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24CXXX monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24CXXX then performs a Read or Write operation
depending on the state of the R/W bit.
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
1
Figure 6. Slave Address Bits
24C021/022
24C041/042
* 'X' Corresponds to Don't Care Bits (can be a zero or a one)
** a8, a9 and a10 correspond to the address of the memory array address word.
1 010XXXR/W
1 0 1 0 X X a8 R/W
7
24C081/082
24C161/162
89
ACKNOWLEDGE
1 010Xa9a8R/W
1 0 1 0 a10 a9 a8 R/W
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
ACKNOWLEDGE
Advanced
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24CXXX responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
When the CAT24CXXX begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this acknowledge, the CAT24CXXX will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
t he Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the CAT24CXXX. After receiving another
acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory
location. The CAT24CXXX acknowledges once more
and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle to
nonvolatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
Page Write
The 24CXXX writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, CAT24CXXX will respond with an
acknowledge, and internally increment the lower order
address bits by one. The high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condi
tion has been sent by the Master, the internal programming cycle begins. At this point, all received data is
written to the CAT24CXXX in a single write cycle.
Figure 7. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
Figure 8. Page Write Timing
S
T
BUS ACTIVITY :
MASTER
SDA LINE
A
R
T
S
SLAVE
ADDRESS
S
T
A
R
ADDRESS
T
S
ADDRESS (n)
A
C
K
SLAVE
BYTE
A
C
K
A
C
K
BYTE
ADDRESS
DATA n
A
C
K
A
C
K
DATA
DATA n+1
S
T
O
P
P
A
C
K
S
T
DATA n+15
A
C
K
O
P
P
A
C
K
Doc. No. 25079-00 1/98 M-1
8
Advanced
Acknowledge Polling
CAT24CXX1/XX2
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation,
CAT24CXXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24CXXX is still busy with the write
operation, no ACK will be returned. If
CAT24CXXX has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
Figure 9. Immediate Address Read Timing
protected and becomes read only. The CAT24CXXX
will accept both slave and byte addresses, but the
memory location accessed is protected from programming by the device's failure to send an acknowledge
after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24CXXX is initiated in
the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
S
T
BUS ACTIVITY:
MASTER
SDA LINE
SCL
SDA 8TH BIT
A
R
T
S
89
SLAVE
ADDRESS
S
T
O
P
P
A
C
K
DATA
N
O
A
C
K
STOPNO ACKDATA OUT
24C1601Fig.8
9
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
Immediate/Current Address Read
Advanced
The CAT24CXXX’s address counter contains the address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access data from address N+1. If N=E (where E= 255 for
24C021/022, E=511 for 24C041/042, E=1023 for
24C081/082 and E=2047 for 24C161/162) then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24CXXX receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it
wishes to read. After CAT24CXXX acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one.
The CAT24CXXX then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24CXXX sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24CXXX will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24CXXX is outputted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24CXXX address bits
so that the entire memory array can be read during one
operation. If more than E (where E= 255 for 24C021/
022, E=511 for 24C041/042, E=1023 for 24C081/082
and E=2047 for 24C161/162) bytes are read out, the
counter will ‘wrap around’ and continue to clock out data
bytes.
Figure 10. Selective Read Timing
S
T
A
BUS ACTIVITY:
MASTER
SDA LINE
R
T
S
SLAVE
ADDRESS
Figure 11. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
A
C
K
BYTE
ADDRESS (n)
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
DATA n+2
S
T
O
P
P
A
DATA n
C
K
A
C
K
N
O
A
C
K
24C1601Fig.9
S
T
DATA n+xDATA n
O
P
P
N
O
A
C
K
Doc. No. 25079-00 1/98 M-1
24C1601Fig.10
10
Advanced
Ordering Information
Prefix Device # Suffix
CAT24CXX1/XX2
CAT
Optional
Company ID
24C162
Product
Number
24C161: 16K
24C162: 16K
J
I TE13
Temperature Range
Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
A = Automotive (-40˚to +105˚C)*
-30
Tape & Reel
TE13: 2000/Reel
24C081: 8K
24C082: 8K
24C041: 4K
24C042: 4K
24C021: 2K
24C022: 2K
Package
P: PDIP
J: SOIC (JEDEC)
Reset Threshold
V oltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
* -40˚ to +125˚C is available upon request
Note:
(1) The device used in the above example is a CAT24C162JI-30TE13 (16K I2C Memory, SOIC, Industrial Temperature, 3.0-3.15V Reset
Threshold Voltage, Tape and Reel)
25: 2.55-2.7V
11
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
Advanced
Doc. No. 25079-00 1/98 M-1
12
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