CRYSTAL Logic CS5317 User Manual

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16-Bit, 20 kHz Oversampling A/D Converter

CS5317

Features

l Complete Voiceband DSP Front-E nd

- 16-Bit A/D Converter

- Internal Track & Hold Amplifier

- On-Chip Voltage Reference

- Linear-Phase Digital Filter

l On-Chip PLL for Simplified Output Phase

Locking in Modem Applications

l 84 dB Dynamic Range
l 80 dB Total Harmonic Distortion
l Output Word Rates up to 20 kHz
l DSP-Compatible Serial Interface
l Low Power Dissipation: 220 mW

Description

The CS5317 is an ideal anal og front-end for voice band
signal processing applications such as high-perfor­mance modems, passive sonar, and voice rec ognition
systems. It includes a 16-bit A/D converter with an inter­nal track & hold amplifier, a voltage reference, and a
linear-phase digital filter.

An on-chip phase-l ock loop (PLL) circuit simplifies th e
CS5317’s use in applications where the output word rate
must be locked to an external sampling signal.

The CS5317 uses delta-sigma modulation to achieve
16-bit output word rates up to 20 kHz. The delta-sigm a
technique utilizes oversampli ng followed by a digital fil­tering and decimation process. The combination of
oversampling and d igital fi ltering gr eatly ea ses anti alias
requirements. Thus, the CS531 7 offers 84 dB dynamic
range and 80 dB THD and signal bandwidths up to
10 kHz at a fraction of t he cost of hybrid and discrete
solutions.

The CS5317’s advanced CMOS construction provides
low power consumptio n of 220 mW and the inher en t re­liability of monolithic devices.

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Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com

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ORDERING INFORMATION

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DS27F4

1

CS5317

ANALOG CHARACTERISTICS

(TA = T

MIN

- T

; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%;

MAX

CLKIN = 4.9152 MHz in CLKOR mode; 1kHz Input Sinewave; with 1.2 kΩ, .01 µF antialiasing filter.)

Parameter* Min Typ Max Units

Specified Temperature Range 0 to 70 °C
Resolution 16 - - Bits

Dynamic Performance

Dynamic Rnage (Note 1) 78 84 - dB
Total Harmonic Distortion 72 80 - dB
Signal to Intermodulation Distorition - 84 - dB

dc Accuracy

Differential Nonlinearity (Note2) ­Positive Full-Scale Error ­Positive Full-Scale Drift ­Bipolar Offset Error ­Bipolar Offset Drift -

±
±
±

±
±

0.4
150
500

10
50

-LSB

-mV

-

µ

V/°C

-mV

-

µ

V/°C

Filter Characteristics

Absolute Group Delay (Note 3) 78.125 - -

µ

s

Passband Frequency (Note 4) - 5 - kHz

Input Characteristics

AC Input Impedance ( 1kHz) - 80 ­Analog Input Full Scale Signal Level

±

2.75

--V

Ω

k

Power Supplies

Power Dissipation (Note5) - 220 300 mW

Notes: 1. Measured over the full 0 to 9.6kHz band with a -20dB input and extrapolated to full-sc ale. Since this

includes energy in the stopband above 5kHz, additional post-filtering at the CS5317’s output can
typically achieve 88dB dynamic range by improving rejection above 5kHz. This can be increased to
90dB by bandlimiting the output to 2.5kHz.

2. No missing codes is guaranteed by design.

3. Group delay is constant with respect to input analog frequency; that is, the digital FIR filter has
linear phase. Group delay is determined by the formula D

= 384/CLKIN in CLKOR mode, or

grp

192/CLKOUT in any mode.

4. The digital filter’s frequency response sc ales with the master clock . Its -3dB point is deter mined by

= CLKIN/977.3 in CLKOR mode, or CLKOUT/488.65 in any mode.

f

-3dB

5. All outputs unloaded. All inputs CMOS levels .

* Refer to the

Parameter Definitions

section after the Pin Description section.

2 DS27F4

ANALOG CHARACTERISTICS (continued)

Parameter Min Typ Max Units

CS5317

Power Supply Rejection VA+ (Note 6)

VA­VD+
VD-

-

-

-

-

60
45
60
55

-

-

-

-

dB
dB
dB
dB

Specified Temperature Range 0 to 70 °C

Phase-Lock Loop Characteristics

VCO Gain Constant, Ko (Note 7) -4 -10 -30 Mrad/Vs
VCO Operating Frequency 1.28 - 5.12 MHz
Phase Detector Gain Control, Kd -3 -8 -12

µ

A/rad

Phase Detector Prop. Delay (Note 8) - 50 100 ns

Notes: 6. With 300mV p-p, 1kHz ripple applied to each supply separately.

7. Over 1.28 MHz to 5.12 MHz VCO output range, where VCO frequency = 2 * CLKOUT.

8. Delay from an input edge to the phase detector to a response at the PHDT output pin.

DIGITAL CHARACTERISTICS

(TA = T

MIN

- T

; VA+, VD+ = 5V±10%; VA-, VD- = -5V±10%)

MAX

All measurements performed under static conditions.

Parameter Symbol Min Typ Max Units

High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (Note 9) V
Low-Level Output Voltage I

= 1.6mA V

OUT

Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C

Note: 9. I

=-100µA. This specification guarantees the ability to drive one TTL load (VOH=2.4V @ I

out

IH

IL
OH
OL

in

OZ

out

2.0 - - V

--0.8V

(VD+)-1.0V - - V

--0.4V

--10

--

±10µ

µ

-9-pF
=-40µA.).

out

A
A

RECOMMENDED OPERATING CONDITIONS (DGND, AGND = 0V, see Note 10.)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital

Negative Digital
Positive Analog
Negative Analog

Master Clock Frequency f

Note: 10. All voltages with respect to ground.

Specifications are subject to change without notice.

DS27F4 3

VD+

VD-

VA+

VA-

clk

4.5

-4.5

4.5

-4.5

5.0

-5.0

5.0

-5.0

5.5

-5.5

5.5

-5.5

V
V
V
V

0.01 - 5.12 MHz

CS5317

SWITCHING CHARACTERISTICS

(TA = T

MIN-TMAX

Parameter Symbol Min Typ Max Units

Master Clock Frequency: CLKIN

CLKG1 Mode
CLKG2 Mode

CLKOR Mode
Output Word Rate: D OUT f
Rise Times: Any Digital Input

Any Digital Output
Fall Times: Any Digital Input

Any Digital Output
CLKIN Duty Cycle

CLKG1 and CKLG2 Modes Pulse Width Low

Pulse Width High

CLKOR Mode Pulse Width Low

Pulse Width High
RST Pulse Width Low t
Set Up Times: RST High to CLKIN High

CLKIN High to RST High

Propagation Delays:

DOE Falling to Data Valid
CLKIN Rising to DOUT Falling (Note 11)
DOE Rising to Hi-Z Output
CLKOUT Rising to DOUT Falling
CLKOUT Rising to DOUT Rising
CLKOUT Rising to Data Valid
CLKIN Rising to CLKOUT Falling (Note 12)
CLKIN Rising to CLKOUT Rising (Note 12)

Notes: 11. CLKIN only pertains to CLKG1 and CLKG2 modes.

12. Only valid in CLKOR mode.

; CL=50 pF; VD+ = 5V±10%; VD- = -5V±10%)

f

clkg1

f

clkg2

f

clkor
dout

t

risein

t

riseout

t

fallin

t

fallout

t

pwl1

t

pwh1

t

pwl1

t

pwh1

pwr

t

su1

t

su2

t

phl1

t

phl2

t

plh1

t

plh2

t

plh3

t

plh4

t

plh5

t

plh6

-

-

-

--20kHz

-

-

-

-

200
200

45
45

400 - - ns

40
40

-

-

-

-

-

-

-

-

20
15

20
15

1

-

-

-

20
10

5.12

1000

20

1000

20

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

150

­80
60
60

100
200
200

CLKOUT

cycles

kHz
kHz

MHz

ns
ns

ns
ns

ns
ns
ns
ns

ns
ns

ns

ns
ns
ns
ns
ns

ABSOLUTE MAXIMUM RATINGS (DGND, AGND = 0V, all voltages with repect to groung)

Parameter Symbol Min Max Units

DC Power Supplies: Positive Digital

Negative Digital
Positive Analog

Negative Analog
Input Current, Any Pin Except Supplies (Note 13) I
Analog Input Voltage (AIN and VREF pins) V
Digital Input Voltage V
Ambient Operating Temperature T

Storage Temperature T

Notes: 13. Transient currents up to 100mA will not cause SCR latch-up.
WARNING:Operating this device at or beyond thes e extremes may result in permanent damage to the device.

Normal operation of the part is not guaranteed at these extremes.

4 DS27F4

VD+

VD-

VA+

VA-

in
INA
IND

A

stg

-0.3

0.3

-0.3

0.3

-

(VA+) + 0.3

-6.0

6.0

-6.0
±10

mA

(VA-) - 0.3 (VA+) + 0.3 V

-0.3 (VD+) + 0.3 V

-55 125 °C

-65 150 °C

V
V
V
V

CS5317

CLKIN

CLKIN

(Note 14)

CLKOUT

DOUT

DATA

t

risein

t

phl1

t

fallin

t

pwh1

t

phl2

t

plh4

2.0 V

0.8 V

Rise and Fall Times

CLKIN Timing

t

plh2

(MSB)

14

1015

t

riseout

t

pwl1

t

plh3

t

t

plh1

fallout

2.4 V

0.4 V

DOE

(Note 15)

Serial Output Timing

CLKIN

t

plh6

CLKOUT

DOUT

RST

(Note 16)

t

su2

t

plh5

t

su1

Reset Timing

Notes: 14. CLKIN only pertains to CLKG1 and CLKG2 modes.

DOE is brought high during serial data transfer, CLKOUT, DOUT, and DATA will immediately

15. If
3-state and the rest of the serial data is lost.
RST must be held high except in the clock ov erride (CLKOR) mode where it can be used to align

16.
the phases of all internal clocks.

t

su2

t

pwr

t

t

su1

plh5

DS27F4 5

CS5317

GENERAL DESCRIPTION

The CS5317 functions as a complete data conver­sion subsystem for voiceband signal processing.
The A/D converter, sample/hold, voltage refer­ence, and much of the antialiasing filtering are

performed on-chip. The CS5317’s serial interface
offers its 16-bit, 2’s complement output in a for­mat which easily interfaces with
industry-standard micro’s and DSP’s.

The CS5317 also includes a phase-locked loop
that simplifies the converter’s application in sys­tems which require sampling to be locked to an
external signal source. The CS5317 continuously
samples its analog input at a rate set by an exter­nal clock source. On-chip digital filtering, an
integral part of the delta-sigma ADC, processes
the data and updates the 16-bit output register at
up to 20 kHz. The CS5317 can be read at any rate
up to 20 kHz.

The CS5317 is a CS5316 with an on-chip sam­pling clock generator. As such, it replaces the
CS5316 and should be considered for all new de­signs. In addition, a CS5316 look-alike mode is
included, allowing a CS5317 to be dropped into a
CS5316 socket.

modulator’s 1-bit output conveys information in
the form of duty cycle. The digital filter then
processes the 1-bit signal and extracts a high
resolution output at a much lower rate (that is,
16-bits at a 20 kHz word rate with a 5 kHz input
bandwidth).

An elementary example of a delta-sigma A/D
converter is a conventional voltage-to-frequency
converter and counter. The VFC’s 1-bit output
conveys information in the form of frequency (or
duty-cycle), which is then filtered (averaged) by
the counter for higher resolution. In comparison,
the CS5317 uses a more sophisticated multi-order
modulator and more powerful FIR filtering to ex­tract higher word rates, much lower noise, and
more useful system-level filtering.

Filtering

At the system level, the CS5317’s digital filter
can be modeled exactly like an analog filter with
a few minor differences. First, digital filtering re­sides behind the A/D conversion and can thus
reject noise injected during the conversion proc­ess (i.e. power supply ripple, voltage reference
noise, or noise in the ADC itself). Analog fil tering
cannot.

Also, since digital filtering resides behind the

THEORY OF OPERATION

A/D converter, noise riding unfiltered on a near-

full-scale input could potentially saturate the
The CS5317 utilizes the delta-sigma technique of
executing low-cost, high-resolution A/D conver­sions. A delta-sigma A/D converter consists of
two basic blocks: an analog modulator and a digi­tal filter.

ADC. In contrast, analog filtering removes the

noise before it ever reaches the converter. To ad-

dress this issue, the CS5317’s analog modulator

and digital filter reserve headroom such that the

device can process signals with 100mV "excur-

sions" above full-scale and still output accurately

Conversion

converted and filtered data. Filtered input signals

above full-scale still result in an output of all
The analog modulator consists of a 1-bit A/D

ones.
converter (that is, a comparator) embedded in an
analog negative feedback loop with high open­loop gain. The modulator samples and converts
the analog input at a rate well above the band-

An Application Note called "Delta Sigma Over-

view" contains more details on delta-sigma

conversion and digital filtering.
width of interest (2.5 MHz for the CS5317). The

6 DS27F4

CS5317

SYSTEM DESIGN WITH THE CS5317

Like a tracking ADC, the CS5317 continuously
samples and converts, always tracking the analog
input signal and updating its output register at a
20 kHz rate. The device can be read at any rate to
create any system-level sampling rate desired up
to 20kHz.

Clocking

Oversampling is a critical function in delta-sigma
A/D conversion. Although system-level output
sample rates typically remain between 7kHz and
20kHz in voiceband applications, the CS5317 ac­tually samples and converts the analog input at
rates up to 2.56 MHz. This internal sampling rate
is typically set by a master clock which is on the
order of several megahertz. See Table1 for a com­plete description of the clock relationships in the
various CS5317 operating modes.

Some systems such as echo-canceling modems,

though, require the output sampling rate to be

locked to a sampling signal which is 20 kHz or

below. For this reason the CS5317 includes an

on-chip phase-lock loop (PLL) which can gener-

ate its requisite 5.12 MHz master clock from a

20 kHz sampling signal.

The CS5317 features two modes of operation

which utilize the internal PLL. The first, termed

Clock Generation 1 (CLKG1), accepts a sam-

pling clock up to 20 kHz at the CLKIN pin and

internally generates the requisite 5.12 MHz clock.

The CS5317 then processes samples updating its

output register at the rate defined at CLKIN, typi-

cally 20 kHz. For a 20 kHz clock input the digital

filter’s 3 dB corner is set at 5.239 kHz, so CLKG1

provides a factor of 2X oversampling at the sys-

tem level (20 kHz is twice the minimum possible

sampling frequency needed to reconstruct a 5

kHz input). The CLKG1 mode is initiated by ty-

ing the MODE input to +5V.

+5V
Analog
Supply

Analog

Signal

Source

VA+

-5V
Analog
Supply

10

Ω

0.1

F

µ

10

µ

10

Conditioning

25 nF

10

µ

µ

Signal

F

0.1

µ

F

F

Ω

25 k

0.1

0.1

µ

µ

F

1 2

VA+ VD+

MODE

CS5317

11

AIN

± 2.75V

10

DOUT
DATA

CLKOUT

Ω

18

17

15

F

12

VCOIN

PHDT

AGND

REFBUF

VA-

14

CLKIN

RST

DOE

DGND

VD-

10

4

0.1

9

Clock

Source

7

16

3

8
6
5

VD- (clock override mode / CLKOR)

VD+ (clock gen. mode / CLKG1)

(clock gen. mode / CLKG2)

uP or DSP

Control

Serial

Data

Interface

10

µ

µ

F

F

Figure 1. System Connection Diagram with Example PLL Components

F

DS27F4 7

CS5317

Output Word

Rate Provides

Mode

Mode Symbol

Clock
Gen. 2

Clock
Gen. 1

Clock
Override

CS5316 CS5316 FSYNC LOW YES 5120.0 (max) 2.56 20.0 20.0 N/A

* t

dcD

CLKG2
CLKG2
CLKG2

CLKG1
CLKG1
CLKG1

CLKOR
CLKOR
CLKOR

- Delay from CLKIN rising to DOUT falling = 1 CLKOUT cycle

Pin RESET

0V HIGH NO 7.2

+5V HIGH YES 14.4

-5V SYNC YES 3686.4

System-level 2X

Oversampling

Table 1. Mode Comparisons

CLKIN

(kHz)

9.6

10.0 (max)

19.2

20.0 (max)

4915.2

5120.0 (max)

CLKOUT

f

sin

(MHz)

1.8432

2.4576

2.56

1.8432

2.4576

2.56

1.8432

2.4576

2.56

DOUT

f

sout

(kHz)F(kHz)

7.2

9.6

10.0

14.4

19.2

20.0

14.4

19.2

20.0

14.4

19.2

20.0

14.4

19.2

20.0

14.4

19.2

20.0

t

dcD

(ns)

542.5

406.9

390.6

542.5

406.9

390.6
N/A

N/A
N/A

*

The second PLL mode is termed Clock Genera­tion 2 (CLKG2) which generates its 5.12 MHz

clock from a 10 kHz external sampling signal.
Again, output samples are available at the system
sampling rate set by CLKIN, typically 10 kHz.
For the full-rated 10 kHz clock CLKG2 still sets

the filter’s 3 dB point at 5 kHz. Therefore,
CLKG2 provides no oversampling beyond the
Nyquist requirement at the system level
(10 kHz : 5 kHz) and its internal digital filter pro­vides little anti-aliasing value. The CLKG2 mode
is initiated by grounding the MODE pin.

The CS5317 features a third operating mode
called Clock Override (CLKOR). Initiated by ty-
ing the MODE pin to -5V, CLKOR allows the

5.12 MHz master clock to be driven directly into
the CLKIN pin. The CS5317 then processes sam­ples updating its output register at f

clkin

/256.
Since all clocking is generated internally, the
CLKOR mode includes a Reset capability which
allows the output samples of multiple CS5317’s
to be synchronized.

Analog Design Considerations

DC Characteristics

The CS5317 was designed for signal processing.
Its analog modulator uses CMOS amplifiers re­sulting in offset and gain errors which drift over
temperature. If the CS5317 is being considered
for low-frequency (< 10 Hz) measurement appli­cations, Crystal Semiconductor recommends the
CS5501, a low-cost, d.c. accurate, delta-sigma
ADC featuring excellent 60 Hz rejection and a
system-level calibration capability.

The Analog Input Range and Coding Format

The input range of the CS5317 is nominally ± 3V,
with ± 250 mV possible gain error. Because of

this gain error, analog input levels should be kept
below ± 2.75V. The converter’s serial output ap-

pears MSB-first in 2’s complement format.

Antialiasing Considerations

The CS5317 also has a CS5316 compatible
mode, selected by tying RST low, and using
MODE (pin 7) as the FSYNC pin. See the
CS5316 data sheet for detailed timing informa­tion.

8 DS27F4

In applying the CS5317, aliasing occurs during
both the initial sampling of the analog input at f

s

(~2.5 MHz) and during the digital decimation
process to the 16-bit output sample rate, f

.

s

out

in

CS5317

Initial Sampling

The CS5317 samples the analog input, AIN, at
one-half the master clock frequency (~2.5 MHz
max). The input sampling frequency, f

, appears

s

in

at CLKOUT regardless of whether the master
clock is generated on-chip (CLKG1 and CLKG2
modes) or driven directly into the CS5317
(CLKOR mode). The digital filter then processes
the input signal at the input sample rate.

Like any sampled-data filter, though, the digital

filter’s passband spectrum repeats around integer
multiples of the sample rate, f

. That is, when

s

in

the CS5317 is operating at its full-rated speed any

Mag H(e

jω

) (dB)

-2.74 dB

0

noise within ± 5 kHz bands around 2.5 MHz, 5
MHz, 7.5 MHz, etc. will pass unfiltered and alias
into the baseband. Such noise can only be filtered
by analog filtering before the signal is sampled.
Since the signal is heavily oversampled (2.5
MHz : 5 kHz, or 500 : 1), a single-pole passive
RC filter can be used as shown in Figure 2.

Input
Signal

1.2 K

AIN

0.01µF

Note: Any nonlinearities contributed by this filter
will be encoded as distortion by the CS5317.
Therefore a low distortion, high frequency ca­pacitor such as COG-ceramic is recommended.

Figure 2. Anti-alias Filter





sin





128sin





128πƒ

(

T

(πƒT)

-40

-80
0 F 2F 3F

.25 F .5 F

dc

3

)





= Magnitude where: T = 1/









ƒ

sout

ƒ

sout

f

5 kHz

10 kHz

ƒ

= input sampling frequency = CLKOUT frequency for all modes

sin

= CLKIN/2 in CLKOR mode
= CLKIN*128 in CLKG1 mode

= CLKIN*256 in CLKG2 mode
F = ƒ
ƒ = input frequency

= ƒ

= ƒ

20 kHz

ƒ

sin

/128 for all modes

sin

/128 = output data rate for CLKOR & CLKG1 = F

sin

/256 = output data rate for CLKG2 = F/2

sin

40 kHz

60 kHz

Examples: For ƒ

For ƒ

DS27F4 9

= 2.56 MHz at ƒ = 5 kHz: Magnitude is -2.74 dB

sin

= 2.56 MHz at ƒ = 10 kHz: Magnitude is -11.8 dB

sin

Figure 3. CS5317 Low-Pass Filter Response

CS5317

Decimation

Aliasing effects due to decimation are identical in
the CLKOR and CLKG1 modes. Aliasing is dif­ferent in the CLKG2 mode due to the difference
in output sample rates (10 kHz vs. 20 kHz) and
thus will be discussed separately.

Aliasing in the CLKOR and CLKG1 Modes

The delta-sigma modulator output is fed into the
digital low-pass filter at the input sampling rate,
f

. The filter’s frequency response is shown in

s

in

Figure 3. In the process of filtering the digitized
signal the filter decimates the sampling rate by
128 (that is, f

= f

s

out

/128). In its most elemen-

s

in

tary form, decimation simply involves ignoring ­or selectively reading - a fraction of the available
samples.

In the process of decimation the output of the
digital filter is effectively resa mp led at f

s

out

, the
output word rate, which has aliasing implications.
Residual signals after filtering at multiples of f

s

out

will alias into the baseband. For example, an in­put tone at 28 kHz will be attenuated by 39.9 dB.
If f

= 20 kHz, the residual tone will alias into

s

out

the baseband and appear at 8 kHz in the output
spectrum.

If the input signal contains a large amount of out­of-band energy, additional analog and/or digital
antialias filtering may be required. If digital post­filtering is used to augment the CS5317’s
rejection above f

/4 (that is, above 5 kHz), the

s

out

filtering will also reject residual quantization

noise from the modulator. This will typically in­crease the converter’s dynamic range to 88 dB.
Further bandlimiting the digital output to f

/8

s

out

(2.5 kHz at full speed) will typically increase dy­namic range to 90 dB.

Aliasing in the CLKG2 Mode

Aliasing effects in the CLKG2 mode can be mod­eled exactly as those in the CLKG1 mode with
the output decimated by two (from 20 kHz to 10
kHz). This is most easily achieved by ignoring
every other sample. In the CLKG2 mode the ratio
of the output sampling rate to the filter’s -3 dB
point is two, with no oversampling beyond the
demands of the Nyquist criterion. Without the
ability to roll-off substantially before f

s

out

/2, the
on-chip digital filter’s anti aliasing value is dimin­ished.

The CLKG2 mode should therefore be used only
when the output data rate must be minimized due
to communication and/or storage reasons. In ad­dition, adequate analog filtering must be provided
prior to the A/D converter .

Digital Design Considerations

The CS5317 presents its 16-bit serial output
MSB-first in 2’s complement format. The con­verter’s serial interface was designed to easily
interface to a wide variety of micro’s and DSP ’s.
Appendix A offers several hardware interfaces to
industry-standard processors.

f

out

DOUT

CLKOUT

DATA

10 DS27F4

15 14 15 14

MSB

(sign bit)

131211109876543210

LSB

Figure 4. Data O utput