CRYSTAL Logic CS5101A, CS5102A User Manual

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16-Bit, 100 kHz / 20 kHz A/D Converters

CS5101A CS5102A

Features

l Monolithic CMOS A/D Converters

- Inherent Sampling Architecture

- 2-Channel Input Multiplexer

- Flexible Serial Output Port

l Ultra-Low Distortion

- S/(N+D): 92 dB

- THD: 0.001%

l Conversion Time

- CS5101A: 8 µs

- CS5102A: 40 µs

l Linearity Error: ±0.001% FS

- Guaranteed No Missing Codes

l Self-Calibration Maintains Accuracy

- Over Time and Temperature

l Low Power Consumption

- CS5101A: 320 mW

- CS5102A: 44 mW

- Power-down Mode: <1 mW

l Evaluation Board Available

Description

The CS5101A and CS5102A are 16-bit monolithic CMOS analog-to-digita l converters capable of 1 00 kHz (5101A) and 20 kHz (5102A) throughput. The CS5102A’s low power consumption of 44 mW, couple d with a power down m ode, makes it particularl y suitable for battery powered operation.

On-chip self-calibration circuitry achieves nonlinearity of

±0.001% of FS and guarantees 16-bit no miss in g co des over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with harmonics below

-100 dB. Offse t and fu ll-scale errors are m inimized during the calibration cycle, eliminating the need for external trimming.

The CS5101A and CS5102A ea ch consist of a 2-channel input multiplexer, DAC, conversion and calibration microcontroller, cloc k generator, comp arator, and ser ial communications port. The inherent sampling architecture of the device eliminates the need for an external track and hold amplifier.

The converters' 16-bit data is output in serial form with either binary or 2's complement coding. Three output timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar input ranges are digitally selectable.

I

HOLD SLEEPRST CODEBP/UP

12 28 2 5 16 17 8 9 11 15

3

CLKIN

4

XOUT

REFBUF

VREF

AIN1

AIN2

CH1/2

AGND

Generator

21

20

19

24 13

22

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

STBY

Clock

-

+

-

+

-

+

25 23

ORDERING INFORMATION

See page 36.

TRK1

CRS/FIN

10

Control

Calibration

SRAM

16-Bit Ch arge Redistribution

DAC

DGND VD- VD+VA-VA+

Copyright  Cirrus Logic, Inc. 1997

TRK2

Microcontroller

-

+

Comparator

SSH/SDL

716

SDATA

14

26

27

18

SCLK

TEST

SCKMOD

OUTMOD

MAR ‘95

DS45F2

1

CS5101A

ANALOG CHARACTERISTICS (T

VREF = 4.5V; Full-Scale Input Si newave, 1 kHz; CLKIN = 4 MHz for -16, 8 MHz for -8; f

A

= T

MIN

to T

; VA+, VD+ = 5V; VA-, VD- = -5V;

MAX

= 50 kHz for -16,

s

100 kHz for -8; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each c hannel tested separately; A nalog Source Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified)

CS5101A-J,KCS5101A-A,B

Parameter*MinTypMaxMinTypMax Units

Specified Temperature Range0 to +70-40 to +85

°

C

Accuracy

Linearity Error -J,A,S (Note 1)

-K,B,T Drift (Note 2)

-

0.002

-

0.001

-

±

1/4

0.003

0.002

-

0.002

-

0.001

-

±

1/4

0.003

0.002

-

%FS %FS

∆

LSB Differential Linearity(Notes 3, 4)16--16-- Bits Full Scale Error -J,A, S ( No te 1 )

-K,B,T Drift (Note 2)

Unipolar Offset -J,A,S (Note 1)

-K,B,T Drift (Note 2)

Bipolar Offset -J,A,S (Note 1)

-K,B,T Drift (Note 2)

-

±

-

±

-

±

-

±

-

±

-

±

-

±

-

±

-

±

1 1 1

1

±

4

±

3

-

±

2

5

±

2

4

-

±

2

5

±

2

3

-

±

-

±

-

±

-

±

-

±

-

±

-

±

-

±

-

±

1

±

1

4

±

1

3

-

1

±

2

5

±

2

4

-

±

2

5

±

2

3

-

2

LSB LSB

∆

LSB

LSB LSB

∆

LSB

LSB LSB

∆

LSB Bipolar Negative Ful l- S ca l e E rr o r

-J,A,S (Note 1)

-K,B,T Drift (Note 2)

Dynamic Performance

(Bipolar Mode)

-

±

-

±

-

±

1 1 1

±

4

±

3

-

±

-

±

-

±

1 1 1

±

4

±

3

-

LSB LSB

∆

LSB

Peak Harmonic or Spurious Noise (Note 1) 1 kHz Input -J,A,S

-K,B,T

12 kHz Input -J,A,S

-K,B,T

Total Harmoni c Dist ort ion -J,A, S

-K,B,T

100

98

102 85 85

88 91

--0.002

0.001--

-

96

100

-

98

102

-

85

-

85

88 91

--0.002

0.001--

-

dB dB dB dB

% %

96

Signal-to-Noise Ratio (Note 1) 0dB Input -J,A,S

-K,B,T

-60 dB Input -J,A,S

-K,B,T

87 90

90 92

-

30

-

32

-

87

-

90

-

90 92

-

30

-

32

-

dB dB dB dB

Noise (Note 5)

Unipolar Mode

Bipolar Mode

-

35

-

70

-

35

-

70

-

µV µV

rms rms

Notes: 1. Applies after calibration at any temperature within the specified temperature range. At temp

2. Total drift over specified temperature range after calibration at power-up at 25 °C.

3. Minimum resolution for which no mis sing codes is guaranteed ov er the specified temperature range.

4. Clock speeds of less than 1.0 MHz, at temperatures >100°C will degrade DNL performance.

5. Wideband noise aliased into the baseband. Referred to the input.

*Refer to

Parameter Definitions

(immediately following the pin descriptions at the end of this data sheet).

Specifications are subject to change without notice.

2 DS45F2

CS5101A

ANALOG CHARACTERISTICS (continued)

CS5101A -J,KCS5101A -A,B

Parameter*SymbolMinTypMaxMinTypMax Units

Specified Temperature Range-0 to +7040 to +85

Analog In put

Aperture Time--25--25- ns Aperture Jitter--100--100- ps Input Capacitance (Note 6)

Unipolar Mode Bipolar Mode

-

--320 200

425 265--

320 200

425 265

Conversi on & Th roughput

Conversion Time (Note 7)

-8

-16

-

--8.12

16.25--

t

c

tc

--8.12

16.25

-

Acquisition Time (Note 8)

-8

-16

t

a

ta

-

--2.6

1.88

3.75---2.6

1.88

3.75

Throughput (Note 9)

-8

-16

tp tp

10050-

f f

-

--10050-

-

Power Supplies

Power Supply Current (Note 10)

Positive Analog Negative Analog

(SLEEP High) Positi ve Digital

Negative Digital

+

I

A

-

I

A

+

I

D

-

I

D

-

21

28

-

-21

-28

-

11

15

-

-11

-15

-

21

28

-

-21

-28

-

11

15

-

-11

-15

Power Consumption (Notes 10, 11)

(SLEEP High) (SLEEP Low)

P

do

P

ds

--3201430---3201430

Power Supply Rejection: (Note 12)

Positive Supplies

Negative Supplies

PSR PSR

--8484-

-

°

-

pF pF

µ µ

kHz kHz

mA mA mA mA

mW mW

dB dB

C

s s

Notes : 6. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.

7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loop back ( FRN mode ) with 8 .0 MHz CLKIN . In PD T, RBT, and SSC m odes, as ynchro nous d elay between the falling edge of

HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the

HOLD sample rate is 100 kHz max.

8. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 1.125 µs with an 8 MHz

clock, however; in PDT, RBT, or SSC modes, at clock frequencies of 8 MHz or less, fine charge may be less than 9 clock cycles. This reflects the typ. specification (6 clock cycles + 1.125 µs).

9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times, as described above.

10. All outputs unloaded. All inputs at VD+ or DGND.

11. Power co nsump tion i n the sl eep mo de appl ies with no m aster cloc k appli ed (C LKIN h eld hi gh or l ow).

12. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the uni polar mode to 90 dB. Figure 2 3 show s a pl ot of ty pical power supp ly rejection ve rsus f reque ncy.

DS45F2 3

CS5101A

SWITCHING CHARACTERISTICS (T

VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logi c 1 = VD+; C

= T

A

MIN

to T

L

; VA+, VD+ = 5V ± 10%;

MAX

= 50 pF)

Parameter Symbol Min Typ Max Units

CLKIN Period (Note 4)

-8

-16 CLKIN Low Time t CLKIN High Time t

t

clk

t

clk

clkl

clkh

108 250

-

10,000 10,000

ns ns

37.5 - - ns

Crystal Frequency (Note 13)

-8

-16

f

xtal

f

xtal

2.0

-

9.216

4.0

MHz

MHz SLEEP Rising to Oscillator Stable (Note 14) - - 2 - ms RST Pulse Width t RST to STBY Falling t RST Rising to STBY Rising t CH1/2 Edge to TRK1, TRK2 Rising (Note 15) t CH1/2 Edge to TRK1, TRK2 Falling (Note 15) t HOLD to SSH Falling (Note 16) t HOLD to TRK1, TRK2, Falling (Note 16) t HOLD to TRK1, TRK2, SSH Rising (Note 16) t HOLD Pulse Width (Note 17) t HOLD to CH1/2 Edge (Note 16) t HOLD Falling to CLKIN Falling (Note 17) t

rst

drrs

cal drsh1 dfsh4 dfsh2 dfsh1

drsh

hold dhlri

hcf

150 - - ns

- 100 - ns

- 11,528,160 - t

-80-ns

- - 68t

+260 ns

clk

-60 ns

66t

clk

- 68t

+260 ns

clk

- 120 - ns

1t

+20 - 63t

clk

15 - 64t

clk clk

ns ns

95 - 1tc lk+10 ns

clk

Notes: 13. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency

is 8.0 MHz in FRN mode (100 kHz sample rate).

14. With a 8 MHz crystal, two 10 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 8).

15. These times are for FRN mode.

16. SSH only works correctly if occurs after

17. When

HOLD rises to 64 t

HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must

HOLD falling edge is within +15 to +30 ns of CH1/ 2 edge or if CH1/2 edge

after HOLD has fallen. These times are for P DT and RBT modes.

clk

be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies if CLKIN falls 95 ns after ensures that the

HOLD pulse will meet the minimum specification for t

HOLD falls. This

.

hcf

4 DS45F2

CS5102A

ANALOG CHARACTERISTICS (T

VREF = 4.5V; Full-Scale Input Si newave, 200 Hz; CLKIN = 1.6 MHz; f

A

= T

MIN

to T

; VA+, VD+ = 5V; VA-, VD- = -5V;

MAX

= 20 kHz; Bipolar Mode; FRN Mode;

s

AIN1 and AIN2 tied together, each channel tested separately; Anal og Source Impedance = 50 Ω with 1000pF to AGND unless otherwise specified)

CS5102A-J,KCS5102A-A,B

Parameter*MinTypMaxMinTypMax Units

Specified Temperature Range0 to +70-40 to +85

°

C

Accuracy

Linearity Error -J,A,S (Note 1)

-K,B,T Drift (Note 2)

-

0.002

-

0.001

-

±

1/4

0.003

0.0015

-

0.002

-

0.001

-

±

1/4

0.003

0.0015

-

%FS %FS

∆

LSB Differential Linearity(Notes 3, 18)16--16-- Bits Full Scale Error -J,A,S (Note 1)

-K,B,T Drift (Note 2)

Unipolar Offset -J,A,S (Note 1)

-K,B,T Drift (Note 2)

Bipolar Offset -J,A,S (Note 1)

-K,B,T Drift (Note 2)

Bipolar Negative -J,A,S (No te 1 ) Full-Scale Error -K,B,T

Drift (Note 2)

Dynamic Performance

(Bipolar Mode)

Peak Harmonic or -J,A,S (Note 1) Spurious Noise -K,B,T

Total Harmoni c Dist ort ion -J,A, S

-K,B,T

-

±

2

-

±

-

2

±

1

± ± ±

1

± ± ±

1

±

2

±

2

±

1

9698100

102

--0.002

0.001--

±

4

±

3

-

±

1

4

±

1

3

-

±

1

4

±

1

3

-

±

4

±

3

-

±

-

±

-

±

-

±

-

±

-

±

1

-

±

-

±

-

±

-

±

2

-

±

-

2

±

2

9698100

102

±

2

4

±

2

3

-

1

±

1

4

±

1

3

-

±

1

4

±

1

3

-

2

±

4

±

3

-

--0.002

0.001--

LSB LSB

∆

LSB

LSB LSB

∆

LSB

LSB LSB

∆

LSB

LSB LSB

∆

LSB

dB

% %

Signal-to-Noise Ratio (Note 1) 0dB Input -J,A,S

-K,B,T

-60 dB Input -J,A,S

-K,B,T

87 90

90 92

-

30

-

32

-

87

-

90

-

90 92

-

30

-

32

-

dB

dB Noise (Note 5)

Unipolar Mode

Bipolar Mode

-

35

-

70

-

35

-

70

-

µV µV

rms rms

Note: 18. Clock speeds of less than 1.6 MHz, at temperatures >100°C will degrade DNL performance.

*Refer to

Parameter Definitions

(immediately following the pin descriptions at the end of this data sheet).

Specifications are subject to change without notice.

DS45F2 5

ANALOG CHARACTERISTICS (continued)

CS5102A -J,KCS5102A -A,B

Parameter*SymbolMinTypMaxMinTypMax Units

CS5102A

Specified Temperature Range-0 to +7040 to +85

°

C

Analog In put

Aperture Time--30--30- ns Aperture Jitter--100--100- ps Input Capacitance (Note 6)

Unipolar Mode

-

--320 200

425 265--

320 200

425 265

pF pF

Bipolar Mode

Conversi on & Th roughput

Conversion Time(Note 19)t Acquisition Time(Note 20)t Throughput(Note 21)f

a

tp

--40.625--40.625

c

--9.375--9.375

µ µ

20--20-- kHz

Power Supplies

Power Supply Current (Note 22)

+

Positive Analog Negative Analog

(SLEEP High) Positi ve Digital

Negative Digital

I

A

I

A

I

D

I

D

-

2.4

3.5

-

-2.4

-3.5

+

-

2.5

3.5

-

-1.5

-2.5

-

2.4

3.5

-

-2.4

-3.5

-

2.5

3.5

-

-1.5

-2.5

mA mA mA mA

Power Consumption (Notes 11, 22)

(SLEEP High) (SLEEP Low)

P

do

P

ds

--44165

-

--44165

mW

-

mW

Power Supply Rejection: (Note 23)

Positive Supplies Negative Supplies

PSR PSR--8484

-

--84

-

84

-

dB dB

s

Notes : 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,

internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of

HOLD and the start of conversion may add to the apparent conversion time. This delay will

not exceed 1 master clock cycle + 140 ns.

20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with an 1. 6 MHz

clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles.

21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times, as described above.

22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.

23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the uni polar mode to 90 dB. Figure 2 3 show s a pl ot of ty pical power supp ly rejection ve rsus f reque ncy.

Typ. Power (mW) CLKIN (MHz)

34 0.8 37 1.0 39 1.2 41 1.4 44 1.6

6 DS45F2

CS5102A

SWITCHING CHARACTERISTICS (T

VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C

= T

A

MIN

to T

MAX

;

= 50 pF)

L

Parameter Symbol Min Typ Max Units

CLKIN Period (Note 18,24) t CLKIN Low Time t

CLKIN High Time t Crystal Frequency (Note 24, 25) f

clk

clkl

clkh

xtal

0.5 - 10

µ

200 - - ns 200 - - ns

0.9 1.6 2.0 MHz SLEEP Rising to Oscillator Stable (Note 26) - - 20 - ms RST Pulse Width t RST to STBY Falling t RST Rising to STBY Rising t CH1/2 Edge to TRK1, TRK2 Rising (Note 27) t CH1/2 Edge to TRK1, TRK2 Falling (Note 27) t HOLD to SSH Falling (Note 28) t HOLD to TRK1, TRK2, Falling (Note 28) t HOLD to TRK1, TRK2, SSH Rising (Note 28) t HOLD Pulse Width (Note 29) t HOLD to CH1/2 Edge (Note 28) t HOLD Falling to CLKIN Falling (Note 29) t

rst

drrs

cal drsh1 dfsh4 dfsh2 dfsh1

drsh

hold dhlri

hcf

150 - - ns

- 100 - ns

- 2,882,040 - t

-80-ns

- - 68t

+260 ns

clk

-60 ns

66t

clk

- 68t

+260 ns

clk

- 120 - ns

1t

+20 - 63t

clk

15 - 64t

clk clk

ns ns

55 - 1tc lk+10 ns

s

clk

Note: 24. Minimum CLKIN period is 0.625 µs in FRN mode (20 kHz sample rate). A t temperatures >+85 °C,

and with clock frequencies <1.6 MHz, anal og performance may be degraded.

25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kHz sample rate).

26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 8).

27. These times are for FRN mode.

28. SSH only works correctly if occurs after

29. When

HOLD rises to 64 t

HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must

HOLD falling edge is within +15 to +30 ns of CH1/ 2 edge or if CH1/2 edge

after HOLD has fallen. These times are for P DT and RBT modes.

clk

be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN

HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as

after narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after ensures that the

HOLD pulse will meet the minimum specification for t

HOLD falls. This

.

hcf

DS45F2 7

t

rst

RST

STBY

t

drrs

Reset and Calibration Timing

CS5101A CS5102A

t

cal

CH1/2

TRK1,TRK2

HOLD

SSH/SDL

t

drsh1

t

dfsh4

SSH,TRK1,TRK2

TRK1,TRK2

t

dfsh2

t

drsh

t

dfsh1

a. FRN Mode b. PDT, RBT Mode

Control Output Timing

t

hcf

CH1/2

CLKIN HOLD

Start Conversion Timing

HOLD

t

dhlri

t

hold

Channel Selection Timing

8 DS45F2

SWITCHING CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Units

PDT and RBT Modes

SCLK Input Pulse Period t SCLK Input Pulse Width Low t SCLK Input Pulse Width High t SCLK Input Falling to SDATA Vali d t HOLD Falling to SDATA Valid PDT Mode t TRK1, TRK2 Falling to SDATA Valid (Note 30) t

FRN and SSC Modes

SCLK Output Pulse Width Low t SCLK Output Pulse Width High t SDATA Valid Before Rising SCLK t SDATA Valid After Rising SCLK t SDL Falling to 1st Rising SCLK t Last Rising SCLK to SDL Rising CS5101A

CS5102A

HOLD Falling to 1st Falling SCLK CS5101A

CS5102A

CH1/2 Edge to 1st Falling SCLK t

sclk

sclkl

sclkh

dss dhs

dts

slkl

slkh

ss sh

rsclk

t

rsdl

t

rsdl

t

hfs

thfs

chfs

CS5101A CS5102A

200 - - ns

50 - - ns 50 - - ns

- 100 150 ns

- 140 230 ns

- 65 125 ns

-2t

2t

-100 - - ns

clk

2t

-100 - - ns

clk

-2t

-

6tclk

6t

clk

2t

2tclk

clk clk

-

-7tclk-t

-t

-ns

2tclk+165

+200nsns

2t

clk

8t

+165

clk

+200nsns

8t

clk

clk clk

clk

Note: 30. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then

SDATA is valid t

DIGITAL CHARACTERISTICS (T

VD- =

5V ± 10%)

time after the next falling SCLK .

dss

= T

A

min

to T

; VA+, VD+ = 5V ± 10%; VA-,

max

Parameter Symbol Min Typ Max Units

Calibration Memory Retention (Note 31)

V

MR

2.0 - - V

Power Supply Voltage VA+ and VD+ High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage (Note 32) V Low-Level Output Voltage I

= 1.6 mA V

OUT

Input Leakage Current I Digital Output Pin Capacitance C

IH IL

OH

OL in

out

2.0 - - V

--0.8V

(VD+)-1.0 - - V

--0.4V

--10

µA

-9-pF

Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be

allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization.

32. I

= -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA).

OUT

DS45F2 9

CS5101A CS5102A

t

HOLD

CH1/2

SSH/SDL

t

sclkltsclkh

SCLK

t

SCLK

SDATA

t

dss

sclk

SDATA

a. SCLK input (RBT and PDT mode) b. SCLK output (SSC and FRN modes)

Serial Data Timing

hfs

t

chfs

t

rsclk

slkl

t

slkh

t

dss

t

sh

t

ss

MSB

LSB

t

rsdl

HOLD

SDATA

SCLK

t

dhs

MSB

TRK1, TRK2

SDATA

SCLK

t

dts

MSB

t

dss

a. Pipelined Data Transmission (PDT) b. Register Burst Transmission (RBT) Mode

Data Transmission Timing

MSB-1

10 DS45F2

CS5101A CS5102A

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 33)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital

Negative Digital Positive Analog Negative Analog

VD+

VD-

VA+

VA-

4.5

-4.5

4.5

-4.5

5.0

-5.0

5.0

-5.0

VA+

-5.5

5.5

-5.5

V V V

V Analog Reference Voltage VREF 2.5 4.5 (VA+)-0.5 V Analog Input Voltage: (Note 34)

Unipolar Bipolar

V

AIN

V

AIN

AGND

-VREF

-

VREF VREF

V

Notes: 33. All voltages with respect to ground.

34. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They

will produce an output of all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode and -VREF in bipolar mode, with binar y coding (CODE = low).

ABSOLUTE MAXIMUM RATINGS* (AGND, DGND = 0V, all voltages with respect to ground)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital (Note 35)

Negative Digital Positive Analog Negative Analog

Input Current, Any Pin Except Supplies (Note 36) I Analog Input Voltage (AIN and VREF pins) V

Digital Input Voltage V Ambient Operating Temperature T

Storage Temperature T Ambient Operating Temperature T Storage Temperature T

VD+

VD-

VA+

VA-

in

INA

IND

A

stg

A

stg

-0.3

0.3

-0.3

0.3

--

-

6.0

-6.0

6.0

-6.0

±

10

mA

(VA-)-0.3 - (VA+)+ 0.3 V

-0.3 - (VA+)+0.3 V

-55 - 125

-65 - 150

-55 - 125

-65 - 150

° ° ° °

V

C C C C

Notes: 35. In addition, VD+ must not be greater than ( VA+) +0.3V

36. Transient currents of up to 100 mA will not cause SCR latch-up.

*WARNING: Operation beyond these limits may result in permanent damage to the devi ce.

DS45F2 11

CS5101A CS5102A

GENERAL DESCRIPTION

The CS5101A and CS5102A are 2-channel, 16bit A/D converters. The devices include an inherent sample/hold and an on-chip analog switch for 2-channel operation. Both channels can thus be sampled and converted at rates up to 50 kHz each (CS5101A) or 10 kHz each (CS5102A). Alternatively, each of the devices can be operate d as a single channel ADC operating at 100 kHz (CS5101A) or 20 kHz (CS5102A).

Both the CS5101A and CS5102A can be configured to accept either unipolar or bipolar input ranges, and data is output serially in either binary

or 2’s complement coding. The devices can be configured in 3 different output modes, as w ell as an internal, synchronous loopback mode. The CS5101A and CS5102A provide coarse charge/fine charge control, to allow accurate tracking of high-slew sign als.

THEORY OF OPERATION

The CS5101A and CS5102A implement the successive approximation algorithm using a charge redistribution architecture. Instead of the traditional resistor network, the DAC is an array of binary-weighted capacitors. All capacitors in the

array share a common node at the comparator’s input. As shown in Figure 1, their other terminals are capable of being connected to AGND, VRE F, or AIN (1 or 2). When the device is not calibrating or converting, all capacitors are tied to AIN. Switch S1 is closed and the charge on the array, tracks the input signal.

When the conversion command is issued, switch S1 opens. This traps the charge on the comparator side of the capacitor array and creates a floating node at the comparator ’s input. The co nversion algorithm operates on this fixed charge, and the signal at the analog input pin is ignored. In effect, the entire DAC capacitor array serves as analog memory during conversion much like a hold capacitor in a sample/hold amplifier.

The conversion consists of manipulating the free plates of th e capacitor array to VREF and AGND to form a capacitive divider. Since the charge at the floating node remains fixed, the voltage at that point depends on the proportion of capacitance tied to VREF versus AGND. The successive-approximation algorithm is used to find the proportion of capacitance, which when connected to the reference will drive the voltage at the floating node to zero. That binary fraction of capacitance represents the converter’s digital output.

AIN

Fine

+

-

VREF

+

-

AGND

+

-

12 DS45F2

Coarse Fine

Coarse

Figure 1. Coarse Charge Input Buffers and Charge Redistribution DAC

C

Bit 15 Bit 14 Bit 13 Bit 0 MSB LSB

C/2 C/32,768

C = C + C/2 + C/4 + C/8 + ... C/32,768

tot

C/4

C/32,768

Dummy

S1

-

+