K
CS5521
CS5523
2- or 4-Channel 16-Bit Buffered
Features
l Delta-Sigma A/D Converter
— Linearity Error: 0.0015%FS
l Buffered Bipolar/Unipolar Input Ranges
— 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
l Chopper Stabilized Instrumentation Amplifier
l On-Chip Charge Pump Drive Circuitry
l Differential Multiplexer
l Conversion Data FIFO
l Programmable/Auto Channel Sequencer
l 2-Bit Output Latch
l Simple three-wire serial interface
— SPI™ and Microwire™ Compatible
— Schmitt Trigger on Serial Clock (SCLK)
l Output Settles in One Conversion Cycle
l 50/60 Hz ±3 Hz Simultaneous Rejection
l Buffered V
l System and Self-Calibration with R/W
Registers per Chan nel
l Single +5 V Analog Supply
+3.0 V or +5 V Digital Supply
l Power Consumption: 5.5 mW
- 1.8 mW in 1 V, 2.5 V and 5 V input ranges
with +5 V Input Capability
REF
∆Σ
Multi-Range ADC
General Description
The 16-bit CS5521/23 are highly integrated ∆Σ A/D converters which include an instrumentation amplifier, a PGA
(programmable gain amplifie r), a multi-channel multiplexe r,
digital filters, and sel f and syst em cali bration circu itry.
The chips are designed to provide their own negative
supply which enables their on-chi p instrumentati on amplifiers to measure bipolar ground-referenced signals
less-than or equal to ±100 mV.
The digital filters p rovide programmable output update
rates of 1.88 Hz, 3.76 Hz, 7.51 Hz, 15 Hz, 30 Hz,
61.6 Hz, 84.5 Hz, and 101.1 Hz when operating from a
32 kHz crystal. The CS5521/23 are capable of producing
output update rates up t o 303 Hz with a 100kHz clock .
The filters are desi gned to s ettle to fu ll accurac y for the
selected output update rate within one conversion cycle.
When operated at word rates of 15 Hz or less, the digital
filters reject both 50 and 60 Hz line interference
simultaneously.
Low power, single conversion settling time, programmable output rates, and the ability to handle ne gative inpu t
signals make these single supply products ideal solutions for isolated and non-isolated applications.
ORDERING INFORMATION
See page 33.
±3Hz
VA+
+
X20
-
Latch
A0 A1
X1
X1
AIN1+
AIN1AIN2+
AIN2-
AIN3+
AIN3AIN4+
AIN4-
NBV
MUX
CS5523
Shown
CPD
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
AGND
Programmable
Gain
Calibration
Memory
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
VREF+
VREF-
X1
Differential
4th order
delta-sigma
modulator
Calibra tion
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
µ
C
Digital Filter
Clock
Gen.
XIN XOUT
VD+DGND
Calibra tion
Register
Control
Register
Output
Register
CS
SCL
SDI
SDO
MAR ‘99
DS317PP2
1
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ................................................ ............4
ANALOG CHARACTERISTICS................................................................... 4
RMS NOISE.................................................................................................4
5 V DIGITAL CHARACTERISTICS ............................................................. 6
3 V DIGITAL CHARACTERISTICS ............................................................. 6
DYNAMIC CHARACTERISTICS ................................................................. 7
RECOMMENDED OPERATING CONDITIONS.......................................... 7
ABSOLUTE MAXIMUM RATINGS.............................................................. 7
SWITCHING CHARACTERISTICS .................................... ....... ...... ....... ..... 8
GENERAL DESCRIPTION ................................................................................ 10
Theory of Operation .................................................................................. 10
System Initialization ........................... ....... ...... ...... ....... ...... .......................12
Serial Port Overview ................................................................................. 12
Serial Port Interface .................................................................................. 13
Serial Port Initialization ............................................................................. 13
Channel-Setup Registers ...... ....... ...... ....... ...... ....................................... ... 13
Conversion Protocol ................................................................................. 13
Calibration Protocol ..................................................................................19
Use of Pointers in Command Byte ............................................................20
Analog Input ............................................................................................. 21
Charge Pump Drive ..................................................................................23
Voltage Reference .................................................................................... 24
Calibration .................................................................................................24
Self Calibration .........................................................................................25
System Calibration ................ ....... ...... ....... ...... ...... ....... ............................. 25
Calibration Tips ......................................................................................... 27
Limitations in Calibration Range ............................................................... 27
Analog Output Latch Pins ......................................................................... 28
Output Word Rate Selection ..................................................................... 28
Clock Generator ........................................................................................28
Digital Filter ...............................................................................................28
Output Coding .......................................................................................... 28
Power Consumption .................................................................................29
PCB Layout .............................................................................................. 30
PIN DESCRIPTIONS ......................................................................................... 31
Clock Generator ........................................................................................31
Control Pins and Serial Data I/O ...............................................................31
Measurement and Reference Inputs ........................................................32
Power Supply Connections .......................................................................32
SPECIFICATION DEFINITIONS ........................................................................ 33
ORDERING GUIDE ............................................................................................ 33
PACKAGE DESCRIPTIONS ............................................................................. 34
CS5521 CS5523
SPI™ is a trademark of Motorola Inc., Microwire™ is a trademark of National Semiconductor Corp.
Prelimina ry pro du ct i nfo rma tion desc ri bes prod ucts wh ich are i n pr oduc ti on, bu t f or w hich ful l c har act eri za tion d ata is not yet available. Advance
product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts
to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this
information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no
license unde r patents, copyri g ht s , trademarks, or t r ade secrets. No p art of this publication may be copied, reproduc e d , s tored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publicat ion
may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of
Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners
which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS317PP2
TABLE OF FIGURES
CS5521/23 Configured to use on-chip charge pump to supply NBV. ................ 10
Charge Pump Drive Circuit for VD+ = 3 V. ......................................................... 11
Alternate NBV Circuits. ...................................................................................... 11
CS5521/23 Configured for ground-referenced Unipolar Signals. ....................... 11
CS5521/23 Configured for Single Supply Bridge Measurement. ....................... 12
Command and Data Word Timing. ..................................................................... 15
Multiplexer Configuration ................................... ...... ...... ....... ...... ....... ...... ....... ... 22
Input models for AIN+ and AIN- pins for each range. ........................................ 24
Input model for VREF+ and VREF- pins. ........................................................... 24
Self Calibration of Offset (Low Ranges). ............................................................ 26
Self Calibration of Offset (High Ranges). ........................................................... 26
Self Calibration of Gain (All Ranges). ................................................................ 26
System Calibration of Offset (Low Ranges). ...................................................... 26
System Calibration of Offset (High Ranges). ..................................................... 26
System Calibration of Gain (Low Ranges) ......................................................... 26
System Calibration of Gain (High Ranges). ....................................................... 26
Filter Response (Normalized to Output Word Rate = 1) .................................... 28
CS5521 CS5523
DS317PP2 3
CHARACTERISTICS/SPECIFICATIONS
CS5521 CS5523
ANALOG CHARACTERISTICS (T
NBV = -2.1 V, FCLK =32.768 kHz, OWR (Output Word Rate) = 15.0 Hz, Bipolar Mode, Input Range = ±100 mV;
See Notes 1 and 2.)
Parameter Min Typ Max Unit
= 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,
A
Accuracy
Resolution - - 16 Bits
Linearity Error Bipolar Offset (Note 3) Unipolar Offset (Note 3) Offset Drift (Notes 3 and 4) - 20 - nV/°C
Bipolar Gain Error Unipolar Gain Error Gain Drift (Note 4) - 1 3 ppm/°C
±
0.0015±0.003 %FS
±
1±2LSB
±
2
±
8
±
16
±
4LSB
±
31 ppm
±
62 ppm
Voltage Reference Input
Range (VREF+) - (VREF-) 1 2.5 VA+ V
VREF+
VREF- NBV Common Mode Rejection dc
50, 60 Hz
Input Capacitance - 16 - pF
CVF Current (Note 5) - 5.0 - nA
(VREF-)+1
-
-
-VA+V
110
130
(VREF+)-1
-
-
V
dB
dB
16
16
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specifications guaranteed by design, characterization, and/or test.
3.
Specification applies to the device only and does not include any effects by external parasitic thermocouples.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
5. See the section of the data sheet which discusses input models.
RMS NOISE (Notes 6 and 7)
Output Rate
(Hz)
1.88 1.64 90 nV 148 nV 220 nV 1.8 µV 3.9 µV 7.8 µV
3.76 3.27 122 nV 182 nV 310 nV 2.6 µV 5.7 µV 11.3 µV
7.51 6.55 180 nV 267 nV 435 nV 3.7 µV 8.5 µV 18.1 µV
15.0 12.7 280 nV 440 nV 810 nV 5.7 µV 14 µV 28 µV
30.0 25.4 580 nV 1.1 µV 2.1 µV 18.2 µV 48 µV 96 µV
61.6 50.4 2.6 µV 4.9 µV 8.5 µV 92 µV 238 µV 390 µV
84.5 (Note 8) 70.7 11 µV 27 µV 43 µV 458 µV 1.1 mV 2.4 mV
101.1 (Note 8) 84.6 41 µV 72 µV 130 µV 1.2 mV 3.4 mV 6.7 mV
Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.
7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.
8. For input ranges <100 mV and output rates >61.6 Hz 16.384 kHz chopping frequency is used.
-3 dB Filter
Frequency
25 mV 55 mV 100 mV 1 V 2.5 V 5 V
Input Range, (Bipolar/Unipolar Mode)
4 DS317PP2
CS5521 CS5523
ANALOG CHARACTERISTICS (Continued)
Parameter Min Typ Max Unit
Analog Input
Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode
NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV
Range = 1 V , 2.5 V, or 5 V
NBV = AGND Range = 25 mV, 55 mV, or 100 mV
Range = 1 V , 2.5 V, or 5 V
Common Mode Rejection dc
50, 60 Hz
-0.150
NBV
1.85
0.0
-
-
-
-
-
-
120
120
Input Capacitance - 10 - pF
CVF Current on AIN+ or AIN- (Note 5)
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V , 2.5 V, or 5 V
-
-
100
10
System Calibration Specifications
Full Scale Calibration Range Bipolar/Unipolar Mode
25 mV
55 mV
100 mV
1 V
2.5 V
5 V
10
25
40
0.40
1.0
2.0
-
-
-
-
-
-
Offset Calibration Range Bipolar/Unipolar Mode
25 mV
55 mV
100 mV (Note 9)
1 V
2.5 V
5 V
-
-
-
-
-
-
-
-
-
-
-
-
Power Supplies
DC Power Supply Currents (Normal Mode) I
(Note 10) I
I
NBV
A+
D+
Power Consumption Normal Mode (Note 11)
Standby
Sleep
Power Supply Rejection dc Positive Supplies
dc NBV
-
-
-
-
-
-
-
-
0.9
90
260
5.5
1.2
500
120
110
0.950
VA+
2.65
VA+
-
-
300
-
32.5
71.5
105
mV
mV
mV
1.30
3.25
VA+
±12.5
±27.5
±50
mV
mV
mV
±0.5
±1.25
±2.50
1.2
mA
135
375
7.5
-
-
mW
mW
µW
-
-
V
V
V
V
dB
dB
pA
nA
V
V
V
V
V
V
µA
µA
dB
dB
Notes: 9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path.
10. Measured with Charge Pump Drive off.
11. All outputs unloaded. All input CMOS levels.
DS317PP2 5
CS5521 CS5523
5 V DIGITAL CHARACTERISTICS (T
= 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;
A
See Notes 2 and 12.)
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCL K
XIN
SCLK
Low-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
High-Level Output Voltage
All Pins Except CPD and SDO (Note 13)
CPD, I
SDO, I
= -4.0 mA
out
= -5.0 mA
out
Low-Level Output Voltage
All Pins Except CPD and SDO, I
CPD, I
SDO, I
= 1.6 mA
out
= 2 mA
out
= 5.0 mA
out
Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C
Notes: 12. All measurements performed under static conditions.
13. I
= -100 µA unless stated otherwise. (VOH = 2.4 V @ I
out
V
IH
V
IL
V
OH
V
OL
in
OZ
out
out
0.6 VD+
(VD+)-0.5
(VD+) - 0.45
(VA+) - 1.0
(VD+) - 1.0
(VD+) - 1.0
= -40 µA.)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
1.5
0.6
-
-
-
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
V
-±1±10µA
--±10µA
-9-pF
3 V DIGITAL CHARACTERISTICS (T
= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;
A
See Notes 2 and 12.)
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCL K
XIN
SCLK
Low-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
High-Level Output Voltage
All Pins Except CPD and SDO, I
CPD, I
SDO, I
= -400 µA
out
= -4.0 mA
out
= -5.0 mA
out
Low-Level Output Voltage
All Pins Except CPD and SDO, I
CPD, I
SDO, I
= 400 µA
out
= 2 mA
out
= 5.0 mA
out
Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C
V
IH
V
IL
V
OH
V
OL
in
OZ
out
0.6 VD+
(VD+)-0.5
(VD+) - 0.45
-
-
-
(VA+) - 0.3
(VD+) - 1.0
(VD+) - 1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.16 VD+
0.3
0.6
-
-
-
0.3
0.4
0.4
-±1±10µA
--±10µA
-9-pF
V
V
V
V
V
V
V
V
V
V
V
V
6 DS317PP2
DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Unit
Modulator Sampling Frequency f
Filter Settling Time to 1/2 LSB (Full Scale Step) t
CS5521 CS5523
s
s
XIN/4 Hz
1/f
out
s
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V; See Note 14.)
Parameter Symbol Min Typ Max Unit
DC Power Supplies Positive Digital
Positive Analog
Analog Reference Voltage (VREF+) - (VREF-) VRef
VD+
VA+
diff
2.7
4.75
5.0
5.0
5.25
5.25
1.0 2.5 VA+ V
V
V
Negative Bias Voltage NBV -1.8 -2.1 -2.5 V
Notes: 14. All voltages with respect to ground.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.)
Parameter Symbol Min Typ Max Unit
DC Power Supplies (Note 15)
Positive Digital
Positive Analog
Negative Bias Voltage Negative Potential NBV +0.3 -2.1 -3.0 V
Input Current, Any Pin Except Supplies (Note 16 and 17) I
Output Current I
Power Dissipation (Note 18) PDN - - 500 mW
Analog Input Voltage VREF pins
AIN Pins
Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T
VD+
VA+
IN
OUT
V
INR
V
INA
IND
stg
-0.3
-0.3
-
-
+6.0
+6.0
V
V
--±10mA
--±25mA
NBV -0.3
NBV -0.3
--(VA+) + 0.3
(VA+) + 0.3VV
-0.3 - (VD+) + 0.3 V
A
-40 - 85 °C
-65 - 150 °C
Notes: 15. No pin should go more negative than NBV - 0.3 V.
16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
18. Total power dissipation, including all input currents and output currents.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS317PP2 7
CS5521 CS5523
SWITCHING CHARACTERISTICS (T
Levels: Logic 0 = 0 V, Logic 1 = VD+; C
= 50 pF.)
L
= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;
A
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 19)
External Clock or Internal Oscillator
XIN
30 32.768 100 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
Fall Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
t
rise
t
fall
-
-
-
-
-
-
50
50
-
-
-
-
1.0
100
-
1.0
100
-
µs
µs
ns
µs
µs
ns
Start-up
Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) t
Power-on Reset Period t
ost
por
-500-ms
- 2006 - XIN
cycles
Serial Port Timing
Serial Clock Frequency SCLK 0 - 2 MHz
SCLK Falling to CS
Falling for continuous running SCLK
t
0
100 - - ns
(Note 22)
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
250
250
-
-
-
-
ns
ns
SDI Write Timing
CS Enable to Valid Latch Clock t
Data Set-up Time prior to SCLK rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS
Disable t
3
4
5
6
50 - - ns
50 - - ns
100 - - ns
100 - - ns
SDO Read Timing
CS to Data Valid t
SCLK Falling to New Data Bit t
Rising to SDO Hi-Z t
CS
7
8
9
--150ns
--150ns
--150ns
Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used
for increased throughput.
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
22. Applicable when SCLK is continuously running.
Specifications are subject to change without notice.
8 DS317PP2
CS
CS
SCLK
CS5521 CS5523
t
0
t
t
t
3
1
t
2
Continuous Running SCLK Timing (Not to Scale)
t
3
6
CS
SDO
SCLK
SCLK
t
7
MSB
MSB
MSB-1 LSBSDI
t
4
t
5
t
1
t
2
t
6
SDI Write Timing (Not to Scale)
t
9
MSB-1 LSB
t
8
t
2
t
1
SDO Read Timing (Not to Scale)
DS317PP2 9
CS5521 CS5523
GENERAL DESCRIPTION
The CS5521/23 are 16-bit converters which include a chopper-stabilized instrumentation amplifier, and an on-chip programmable gain amplifier.
They are optimized for measuring low-level unipolar or bipolar signals in process control and medical
applications.
The CS5521/23 also include a fourth order deltasigma modulator, a calibration microcontroller,
eight digital filters used to select between eight output update rates, a 2-bit analog latch, a multiplexer,
and a serial port.
The CS5521/23 include a CPD (Charge Pump
Drive) output (shown in Figure 1) which provides
a negative bias voltage to the on-chip instrumentation amplifier when used with a combination of external diodes and capacitors. This makes the
converters ideal for thermocouple temperature
measurements because the biasing scheme enables
the CS5521/23 to measure negative voltages with
respect to ground without the need for a negative
supply.
Theory of Operation
The CS5521/23 A/D converters are designed to operate from a single +5 V analog supply with several
different input ranges. See the Analog Character-
istics section on page 3 for details.
Figure 1 illustrates the CS5521/23 connected to
generate their own negative bias supply using the
on-chip CPD (Charge Pump Drive). This e nables
the CS5521/23 to measure ground referenced signals with magnitudes down to -100mV. Figure 2 illustrates a charge pump circuit when the converters
are powered from a +3.0 V digital supply. Alternatively, the negative bias supply can be generated
from a negative supply voltage or a resistive divider as illustrated in Figure 3.
+5V
Analog
Supply
Cold Junction
LM334
Absolute
Current
Reference
2.5V
Up to ± 100 mV Input
Ω
10 k
BAV199
0.1 µF
10 k
Ω
+5V
V+
R
Ω
499
V-
301
Ω
10
Ω
0.1 µF0.1
20
19
3
4
1
18
17
16
6
BAT85
VA+
VREF+
VREF-
AIN1+
AIN1AGND
AIN2+
AIN2-
A1
A0
2
CS5521
5
1N4148
10 µF
+
CPD
14
VD+
XOUT
SCLK
SDO
DGNDNBV
7
0.03 µF
1N4148
XIN
CS
SDI
11
32.768 ~ 100 kHz
10
9
15
8
12
Logic Outputs:
A0 - A1 Switc h from
13
VA+ to AGND.
Charge-pump network
for VD+ = 5V only and
XIN = 32.768 kHz.
Optional
Interface
Clock
Source
Serial
Data
F
µ
Figure 1. CS5521/23 Configured to use on-chip charge pump to supply NBV.
10 DS317PP2
CS5521 CS5523
S
0.1
µF
SerialDataInterface732.768 ~ 100 kH
z
Figure 4 illustrates the CS5521/23 connected to
measure ground referenced unipolar signals of a
positive polarity using the 1 V, 2.5 V, and 5 V ranges on the converter. For the 25 mV, 55 mV, and 100
mV ranges the signal must have a common mode
for the measurement of ratiometric bridge transducer outputs. Figure 5 illustrates the CS5521/23
connected to measure the output of a ratiometric
differential bridge transducer while operating from
a single +5 V supply.
near +2.5 V (NBV = 0V).
The CS5521/23 are optimized for the measurement
of thermocouple outputs, but are also well suited
2N5087
BAT85
or similar
10µF
+
NBV
Figure 2. Charge Pump Drive Circuit for VD+ = 3 V. Figure 3. Alternate NBV Circuits.
-5V
34.8K
30.1K
Ω
NBV
Ω
2.0K
BAT85
+
Ω
-5V
2.1K
10 µF
Ω
10
+5V
Analog
Supply
0 to +5V Input
CM = 0 to V A +
0.1
+
-
F
µ
20
VREF+
19
VREF-
3
AIN1+
4
AIN1-
1
AGND
18
AIN2+
17
AIN2-
16
A1
6
A0
Ω
214
VD+VA+
CS55 1
CPD
XOUT
SCLK
SDO
DGNDNBV
135
XIN
C
SDI
11
10
9
15
8
12
Optional
Clock
Source
Figure 4. CS5521/23 Configured for ground-referenced Unipolar Signals.
DS317PP2 11
SCLKSDOSD
I
C
S
10
0.1
µF
l
SerialDataInterface732.768 ~ 100kHz
configuration registe r: 000040(H)
offset registers: 000000(H)
gain registers: 400000(H)
channel setup regist ers: 000000(H)
+5V
Analog
Supply
-
Figure 5. CS5521/23 Configured for Single Supply Bridge Measurement.
+
0.1
F
µ
VA+
20
VREF+
19
VREF-
AIN1+
3
4
AIN1-
1
AGND
18
AIN2+
17
AIN2-
16
A1
6
A0
Ω
214
CS5521
CPD
VD+
XOUT
DGNDNBV
XIN
135
11
10
9
15
8
12
CS5521 CS5523
Optiona
Clock
Source
System Initialization
When power to the CS5521/23 are applied, the
chips are held in a reset condition until the 32.768
kHz oscillator has started and a counter-timer
elapses. Due to the high Q of the 32.768 kHz crystal, the oscillator takes 400-600 ms to start. The
counter-timer counts 2006 oscillator clock cycles
to make sure the oscillator is fully stable. During
this time-out period the serial port logic is re set and
the RV (Reset Valid) bit in the configuration register is set to indicate that a valid reset occurred. After a reset, the on-chip registers are initialized to the
following states and the converter is placed in the
command mode where it waits for a valid command.
Note: A system reset can be initiated at any time by writing a
logic 1 to the RS (Reset System) bit in the conf iguration register. After a reset, the RV bit is set until t he configuration
register is read. The user must then write a logic 0 to the RS
bit to take the part out of reset mode.
12 DS317PP2
Serial Port Overview
The CS5521/23’s serial port includes a microcontroller which contains a command register, a configuration register, and a gain and offset register for
each input channel. The serial port also includes a
programmable channel sequencer which can sequence up to 8 channels to be converted. The sequencer consists of channel-setup registers (CSRs)
which contain information about the modes used
when conversions are performed. To complement
the sequencer a conversion data FIFO (CDF, read
only) is included to store up to sixteen data conversions. All registers except the 8-bit command register are 24-bits in length. The conversion data
FIFO is just an array of 24-bit conversion data registers used to store conversion words until the FIFO
is read.
The serial port has two modes of operation: the
command mode and the data mode. After a system
initialization or reset, the serial port is initialized
into command mode where it waits to receiv e a valid command (the first 8-bits into the serial port).
Tables 1 and 2 can be used to decode all valid commands. Once a valid command is received, the byte
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