Crystal CS4392 Advance Product Data

CS4392

24-Bit, 192 kHz Stereo DAC with Volume Control

Features

l Complete Stereo DAC System: Inte rpolation,

D/A, Output Analog Filtering

l 114 dB Dynamic Range
l 100 dB THD+N
l Up to 192kHz Sample Rates
l Direct Stream Digital Mode
l Low Clock Jitter Sensitivity
l Single +5 V Power Supply
l Selectable Digital Filters

– Fast and Slow roll-off

l Volume Co ntrol with Sof t Ramp

– 1 dB Step Size
– Zero Crossing Click-Free Transitions

l Direct Interface with 5 V to 1.8 V Logic
l ATAPI mixing functions
l Pin compatible with the CS4391

I

Description

The CS4392 is a comple te stereo digita l-to-analog s ys­tem including digital interpolation, fifth-order delta-sigma
digital-to-analog conversion, digital de-emphasis, vol­ume control, channel mixing and analog filtering. The
advantages of this archi tec ture i nc lud e: id eal di fferent ial
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera­ture, and a high tolerance to clock jitter.

The CS4392 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, has selectable digital
filters, and co nsumes very little power . These features
are ideal for DVD, SACD players, A/V receivers, CD and
set-top box systems. The CS4392 is pin and register
compatible with the CS4 391, m aking ea sy p erforma nce
upgrades possible.

ORDERING INFORMATION

CS4392-KS -10 to 70 °C 20-pin SOIC
CS4392-KZ -10 to 70 °C 20-pin TSSOP
CDB4392 Evaluation Board

M1

(SDA/CDIN)

RST

SCLK

LRCK

SDATA

SERIAL

PORT

Advance Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

M2

(SCL/CCLK) (AD0/CS)

M3

MODE SELECT

(CONTROL PORT)

VOLUME

CONTROL

MIXER

VOLUME

CONTROL

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

M0

AMUTEC

EXTERNAL

MUTE CONTROL

INTERPOLATION

FILTER

INTERPOLATOR

FILTER

MCLK

Copyright  Cirrus Logic, Inc. 2000

(All Rights Reserved)

∆Σ

DAC

∆Σ

DAC

CMOUT

REFERENCE

FILT+BMUTEC

ANALOG

FILTER

ANALOG

FILTER

AOUTA+

AOUTA-

AOUTB+

AOUTB-

OCT ‘00

DS459PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS .................................................................................5

ANALOG CHARACTERISTICS................................................................................................ 5

POWER AND THERMAL CHARACTERISTICS . ....... ............................................. ..................7

DIGITAL CHARACTERISTICS................................................................................................. 8

ABSOLUTE MAXIMUM RATINGS ...........................................................................................8

RECOMMENDED OPERATING CONDITIONS.......................................................................8

SWITCHING CHARACTERISTICS - PCM MODES................................................................. 9

SWITCHING CHARACTERISTICS - DSD..............................................................................10

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE.......................11

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE....................................12

2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 13

3. REGISTER QUICK REFERENCE .......................................................................................... 15

4. REGISTER DESCRIPTION .................................................................................................... 16

4.1 Mode Control 1 - Address 01h ......................................................................................... 16

4.1.1 Auto-Mute (Bit 7) .................................................................................................16

4.1.2 Digital Interface Formats (Bits 6:4) ......................................................................16

4.1.3 De-Emphasis Control (Bits 3:2) ...........................................................................17

4.1.4 Functional Mode (Bits 1:0) .................................................................................. 17

4.2 Volume and Mixing Control (Address 02h) ...................................................................... 18

4.2.1 Channel A Volume = Channel B Volume (Bit 7) ................................................. 18

4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) .........................................................18

4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ......................................................18

4.3 Channel A Volume Control - Address 03h ....................................................................... 20

4.4 Channel B Volume Control - Address 04h........................................................................ 20

4.4.1 Mute (Bit 7) ......................... ....... ...... ....... ...... ...... ....... .......................................... 20

4.4.2 Volume Control (Bits 6:0) ....................................................................................20

4.5 Mode Control 2 - Address 05h ......................................................................................... 20

4.5.1 Invert Signal Polarity (Bits 7:6) ............................................................................20

4.5.2 Control Port Enable (Bit 5) .................................................................................. 21

4.5.3 Power Down (Bit 4) .............................................................................................21

4.5.4 AMUTEC = BMUTEC (Bit 3) ...............................................................................21

4.5.5 Freeze (Bit 2) ......................................... ...... ...... ....... ...... ....... ...... .......................21

4.5.6 Master Clock Divide (Bit 1) ..................................................................................21

CS4392

Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

I2C is a registered trademark of Ph ilips Semiconductors.
Preliminary product inf o rmation describes products whi ch are in production, b ut f or whi c h ful l char act er iza t i on da ta i s not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s
of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be pri nted for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.

2 DS459PP1

CS4392

4.6 Mode Control 3 - Address 06h ......................................................................................... 21

4.6.1 Interpolation Filter Select (Bit 4) .......................................................................... 21

4.6.2 Soft Volume Ramp-up after Reset (Bit 3) ........................................................... 22

4.6.3 Soft Ramp-down before Reset (Bit 2) .......................................... ....... ...... ....... ... 22

4.7 Chip ID - Register 07h .....................................................................................................22

5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 23

6. PIN DESCRIPTION - DSD MODE .......................................................................................... 27

7. APPLICATIONS ..................................................................................................................... 31

7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 31

7.2 Recommended Power-up Sequence and Access to Control Port Mode ......................... 31

7.3 Analog Output and Filtering ............................................................................................. 31

7.4 Interpolation Filter ............................................................................................................ 31

8. CONTROL PORT INTERFACE ............................................. ................................................. 33

8.1 SPI Mode ......................................................................................................................... 33

8.2 Two-Wire Mode ............................................................................................................... 33

9. PARAMETER DEFINITIONS .................................................................................................. 35

Total Harmonic Distortion + Noise (THD+N) ................................................................... 35

Dynamic Range ............................................................................................................... 35

Interchannel Isolation ...................................................................................................... 35

Interchannel Gain Mismatch ........................................................................................... 35

Gain Error........................................................................................................................ 35

Gain Drift ......................................................................................................................... 35

10. REFERENCES ...................................................................................................................... 35

11. PACKAGE DIMENSIONS ................................................................................................. 36

DS459PP1 3

LIST OF TABLES

Table 1. Digital Interface Formats - PCM Modes .......................................................................... 16

Table 2. Digital Interface Formats - DSD Mode ............................................................................17

Table 3. De-Emphasis Mode Selection........................................................................................17

Table 4. Functional Mode Selection..............................................................................................17

Table 5. Soft Cross or Zero Cross Mode Selection......................................................................18

Table 6. ATAPI Decode.................................................................................................................19

Table 7. Digital Volume Control Example Settings........................................................................20

Table 8. Common Clock Frequencies...........................................................................................24

Table 9. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options..........25

Table 10. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ...............25

Table 11. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options ..25
Table 12. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ... 25

Table 13. Direct Stream Digital (DSD), Stand-Alone Mode Options .............................................28

Table 14. Memory Address Pointer (MAP).................................................................................... 34

LIST OF FIGURES

Figure 1. Serial Mode Input Timing .............................................. ....... ...... ...................................... 9

Figure 2. Direct Stream Digital - Serial Audio Input Timing...........................................................10

Figure 3. Two-Wire Mode Control Port Timing..............................................................................11

Figure 4. SPI Control Port Timing ............................. ............................................. ....................... 1 2

Figure 5. Typical Connection Diagram - PCM Mode.....................................................................13

Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 14

Figure 7. De-Emphasis Curve............................. ...... .................................................................... 1 7

Figure 8. ATAPI Block Diagram .................................................................................................... 19

Figure 9. Format 0, Left Justified up to 24-Bit Data....................................................................... 29

Figure 10. Format 1, I2S up to 24-Bit Data ...................................................................................29

Figure 11. Format 2, Right Justified 16-Bit Data ........................................................................... 29

Figure 12. Format 3, Right Justified 24-Bit Data ........................................................................... 29

Figure 13. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 30

Figure 14. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 30

Figure 15. CS4392 Output Filter ................................................................................................... 32

Figure 16. Control Port Timing, SPI mode ....................................................................................34

Figure 17. Control Port Timing, Two-Wire Mode...........................................................................34

CS4392

4 DS459PP1

1. CHARACTERISTICS/SPECIFICATIONS

CS4392

ANALOG CHARACTERISTICS (T

put Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Sample Rate = 48, 96, or 192 kHz, 24-bit data,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

Parameter

= 25° C; Logic "1" = VL = VA; Logic "0" = AG ND; Full -Scale Ou t-

A

= 3 kΩ, CL = 10 pF)

L

VA = 5 V

Symbol Min Typ Max Unit

Dynamic Performance - Single Speed Mode (48kHz)

Dynamic Range (Note 1) unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1) 0 dB

-20 dB

-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N -

TBD
TBD

-

-

111
114

-100

-91

-51

-

-

TBD

-

TBD

dB
dB

dB
dB
dB

Dynamic Performance - Double Speed Mode (96kHz)

Dynamic Range (Note 1) unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1) 0 dB

-20 dB

-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N -

TBD
TBD

-

-

111
114

-100

-91

-51

-

-

TBD

-

TBD

dB
dB

dB
dB
dB

Dynamic Performance - Quad Speed Mode (192kHz)

Dynamic Range (Note 1) unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1) 0 dB

-20 dB

-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N -

TBD
TBD

-

-

111
114

-100

-91

-51

-

-

TBD

-

TBD

dB
dB

dB
dB
dB

Parameter Symbol Min Typ Max Units

Analog Output

Full Scale Differential Output Voltage TBD 1.0xVA TBD Vpp
Common Mode Voltage CMOUT - 0.5xVA - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
AC-Load Resistance R
Load Capacitance C

DS459PP1 5

L
L

3--kΩ

--100pF

CS4392

ANALOG CHARACTERISTICS (continued)

Fast Roll-Off Slow Roll-Off

Parameter Symbol

Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note2)

Passband (Note 3) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 -0.01 - +0.01 dB
StopBand .5465 - - .5834 - - Fs
StopBand Attenuation (Note 5) 90 - - 64 - - dB
Group Delay tgd - TBD - - TBD - s
Passband Group Delay Deviation 0 - 20 kHz - - TBD - TBD s
De-emphasis Error Fs = 32 kHz

(Relative to 1kHz) Fs = 44.1 kHz

Fs = 48 kHz

0
0

-

-

-

-

-

-

-

-

.4535
.499800

±0.23
±0.14
±0.09

--0.4166

0.4998FsFs

-

-

-

-

±0.23

-

±0.14

-

±0.09

Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 2)

Passband (Note 4) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .5834 - - .7917 - - Fs
StopBand Attenuation (Note 5) 80 - - 70 - - dB
Group Delay tgd - TBD - - TBD - s
Passband Group Delay Deviation 0 - 20 kHz - - TBD - - TBD s

0
0

-

-

.4166
.499800

-

-

.2083
.4998FsFs

Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 2)

Passband (Note 4) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .6355 - - .8683 - - Fs
StopBand Attenuation (Note 5) 75 - - 75 - - dB
Group Delay tgd - TBD - - TBD - s
Passband Group Delay Deviation 0 - 20 kHz - - TBD - - TBD s

0
0

-

-

.1046
.489700

-

-

.1042
.4813FsFs

Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 2)

Passband (Note 4) to -3 dB corner TBD - TBD TBD - TBD Fs
Frequency Response 10 Hz to 20 kHz TBD - TBD TBD - TBD dB

Notes: 1. Triangular PDF dit h er e d dat a.

2. Filter response is not tested but is guaranteed by design.

3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 5. Increasing
the capacitance will also increase the PSRR.

4. Response is clock dependent and will scale with Fs.

5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.

UnitMin Typ Max Min Typ Max

dB
dB
dB

6 DS459PP1

CS4392

POWER AND THERMAL CHARACTERISTICS GND = 0 V ( All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Base-rate Mode

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA=5V
Normal Operation VL=3V

Power Supply Current- VA=5V
Power Down Mode (Note 6) VL=3V

Power Supply Current- VA=5V
Normal Operation VL=5V

Power Supply Current- VA=5V
Power Down Mode (Note 6) VL=5V

Total Power Dissipation- All Supplies=5V
Normal Operation VA=5V, VL=1.8V

Package Thermal Resistance θ
Power Supply Rejection Ratio (Note 7) 1 kHz

60 Hz

I

A

I

D_L

I

A

I

D_L

I

A

I

D_L

I

A

I

D_L

JA

PSRR -

-

--

-

-

-

-

-

-

-

-

TBD
TBD

TBD
TBD

25

TBD

60

TBD

125

TBD

-

-

-

-

-

-

-

-

-

-

mA

µA
µA

µA

mA

µA
µA

µA

mW
mW

-TBD-°C/Watt
60

-

40

-

-

dB
dB

Notes: 6.

7. Valid with the recommended capacitor values on FILT+ as shown in Figure 5. Increasing the

GND = 0 V ( All voltages with respect to ground. All measurements taken with all zeros input and open

outputs, unless otherwise specified.) Power Down Mode is defined as RST
data lines held static.

capacitance will also increase the PSRR. NOTE: Care should be taken when selecting capacitor type,
as any leakage current in excess of 1.0 µA will cause degradation in analog performance.

= LO with all clocks and

DS459PP1 7

CS4392

DIGITAL CHARACTERISTICS (T

Parameters Symbol Min Typ Max Units

High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current I
Input Capacitance - 8 - pF

Maximum MUTEC Drive Current - 3 - mA

= 25° C)

A

V

IH

V

IL

in

70% - - VL

- 20% VL

--±10µA

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply VA

VL
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

in

IND

A

stg

-0.3

-0.3

- ±10 mA

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

6.0
VA

V
V

RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply VA

VL

4.75

1.8

5.0

-

5.5
VA

V
V

8 DS459PP1

CS4392

SWITCHING CHARACTERISTICS - PCM MODES (T

= -10 to 70° C; VL = 5.5 to 1.8 Volts;

A

Inputs: Logic 0 = 0 V, Logic 1 = VL, CL = 20 pF)

Parameters Symbol Min Typ Max Units

Input Sample Rate Fs 4 - 200 kHz
LRCK Duty Cycle 45 50 55 %
MCLK Duty Cycle 405060%
SCLK Frequency

SCLK Frequency Note 8
SCLK rising to LRCK edge delay t

SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t

slrd
slrs

sdlrs

sdh

-

­20 - - ns
20 - - ns
20 - - ns
20 - - ns

-MCLK/2Hz

-MCLK/4Hz

Notes: 8. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

LRCK

SCLK

SDATA

t

t

slrd

t

sdlrs

slrs

t

sdh

Figure 1. Serial Mode Input Timing

DS459PP1 9

CS4392

SWITCHING CHARACTERISTICS - DSD (T

Logic 1 = VL = 5.5 to 1.8 Volts; C

=20pF)

L

= -10 to 70° C; Logic 0 = AGND = DGND;

A

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 405060%
DSD_SCLK Pulse Width Low t

DSD_SCLK Pulse Width High t
DSD_SCLK Period t

DSD_L or DSD_R valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_L or DSD_R hold time t

DSD_SCLK

t

sdlrstsdh

sclkl

sclkh

sclkw

sdlrs

sdh

t

TBD - - ns
TBD - - ns
TBD

--ns

TBD - - ns
TBD - - ns

t

sclkh

sclkl

DSD_L, DSD_R

Figure 2. Direct Stream Digital - Serial Audio Input Timing

10 DS459PP1

CS4392

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE

(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)

Parameter Symbol Min Max Unit

Two-Wire Mode

SCL Clock Frequency f

Rising Edge to Start t

RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 10) t
SDA Setup time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t

scl

irs

buf

hdst

low

high

sust
hdd

sud

r
f

susp

-100KHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

-300ns

4.7 - µs

Notes: 9. The Two-Wire mode is compatible with the I

10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

RST

t

irs

Stop Start

SDA

SCL

t

buf

t

t

hdst

low

t

hdd

t

high

2

C protocol.

t

sud

Repeated

Start

t

sust

t

hdst

Stop

t

f

t

r

t

susp

Figure 3. Two-Wire Mode Control Port Timing

DS459PP1 11

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST
CCLK Edge to CS

High Time Between Transmissions t

CS

Falling to CCLK Edge t

CS

Falling (Note 11) t

CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 12) t
Rise Time of CCLK and CDIN (Note 13) t
Fall Time of CCLK and CDIN (Note 13) t

sclk

srs

spi
csh
css

scl
sch
dsu

dh

r2
f2

-6MHz
500 - ns
500 - ns

1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns

-100ns

-100ns

CS4392

Notes: 11. t

12. Data must be held for sufficient time to bridge the transition time of CCLK.

13. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz

SCK

RST

CS

CCLK

CDIN

t

srs

t

t

css

spi

tr2t

t

t

sch

scl

f2

t

t

dsu

dh

= 0 at all other times.

spi

t

csh

Figure 4. SPI Control Port Timing

12 DS459PP1

2. TYPICAL CONNECTION DIAGRAMS

CS4392

Logic Power

+5V to 1.8V

Mode

Select

(Control Port)
*

0.1 µf

Audio

Data

Processor

*

10

M0 (AD0/CS)

9

M1 (SDA/ CDIN)

8

M2 (SCL/CCLK)

7

M3

2

VL

5

LRCK

4

SCLK

3

SDATA

1

RST

17

VA

CS4392

0.1 µf

FILT+

AOUTA-

AMUTEC

AOUTA+

AOUTB-

BMUTEC

AOUTB+

11

19

20

18

14

13

15

+

1.0µf

0.1 µf 1.0 µf

Analog

Conditioning

&

Mute

Analog

Conditioning

&

Mute

+5V Analog

+

6

MCLK

CMOUT

AGND

12

+

1.0 µf

16

External Clock

Figure 5. Typical Connection Diagram - PCM Mode

* A high logic level for all digital inputs should not exceed VL.

DS459PP1 13

CS4392

Logic Power

+5V to 1.8V

Mode

Select

(Control Port)

0.1 µf

Audio

Data

Processor

*

10

M0 (AD0/CS)

9

M1 (SDA/ CDIN)

8

M2 (SCL/CCLK)

2

VL

5

DSD_MODE

7

DSD_CLK

4

DSD_B

3

DSD_A

1

RST

17

CS4392

VA

FILT+

AOUTA-

AMUTEC

AOUTA+

AOUTB-

BMUTEC

AOUTB+

0.1 µf

19

20

18

14

13

15

11

+

1.0µf

0.1 µf 1.0 µf

+5V Analog

Analog

Conditioning

&

Mute

Analog

Conditioning

&

Mute

+

6

MCLK

CMOUT

AGND

12

+

1.0 µf

16

External Clock

Figure 6. Typical Connection Diagram - DSD Mode

* A high logic level for all digital inputs should not exceed VL.

14 DS459PP1

CS4392

3. REGISTER QUICK REFERENCE

This table shows the register names and their associated default values.

Addr Function 7 6 5 4 3 2 1 0

01h Mode Control 1 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

1000 0 0 00

02h Volume and

MIxing Control

03h Channel A Vol-

ume Control

04h Channel B Vol-

ume Control

05h Mode Control 2

06h Mode Control 3 Reserved Reserved Reserved Filt_rolloff rst_rmp_up rst_rmp_dwn Reserved Reserved

07h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

A = B Soft

0100 1 0 01

MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

0000 0 0 00

MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

0000 0 0 00

INVERT_A INVERT_B CPEN PDN MUTEC A = B FREEZE

0001 0 0 00

0000 0 0 00

1000 - - --

Zero

Cross

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

MCLK
Divide

Reserved

DS459PP1 15

CS4392

4. REGISTER DESCRIPTION

** All registers are read/write in Two-Wire mode and write only in SPI mode, unless otherwise noted**

4.1 Mode Control 1 - Address 01h

76543210

AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

4.1.1 Auto-Mute (Bit 7)

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. (However, Auto-Mute detection and muting can be­come dependent on either channel if the Mute A = B function is enabled.) The common mode on the
output will be retained and the Mute Control pin for that channel will go active during the mute period.
The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in
the Volume and Mixing Control register.

4.1.2 Digital Interface Formats (Bits 6:4)

Function:

PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is
defined by the Digital Interface Format and the options are detailed in Table 1 and Figures 9-14.

DIF2 DIF1 DIFO DESCRIPTION Format Figure

0 0 0 Left Justified, up to 24-bit data (default) 0 9
001

0 1 0 Right Justified, 16-bit Data 2 11
0 1 1 Right Justified, 24-bit Data 3 12
1 0 0 Right Justified, 20-bit Data 4 13
1 0 1 Right Justified, 18-bit Data 5 14
110 Reserved
111 Reserved

Table 1. Digital Interface Formats - PCM Modes

2

I

S, up to 24-bit data

110

16 DS459PP1

DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional
Mode registers must be set to DSD Mode. See Table 2 for register options.

DIF2 DIF1 DIFO DESCRIPTION

0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate (default)
0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate
0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate
0 1 1 64x oversampled DSD data with a 12x MCLK to DSD data rate
1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate
1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate
1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate
1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 2. Digital Interface Formats - DSD Mode

4.1.3 De-Emphasis Control (Bits 3:2)

Function:

Implementation of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 7, requires re­configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is available only in Single-Speed Mode. See Table 3 below.

DEM1 DEMO DESCRIPTION

0 0 Disabled (default)
0 1 44.1 kHz de-emphasis
1 0 48 kHz de-emphasis
1 1 32 kHz de-emphasis

Table 3. De-Emphasis Mode Selection

Gain

dB

T1=50 µs

0dB

-10dB

CS4392

T2 = 15 µs

F1 F2

3.183 kHz 10.61 kHz

Frequency

Figure 7. De-Emphasis Curve

4.1.4 Functional Mode (Bits 1:0)

Function:

Selects the required range of input sample rates or DSD Mode. See Table 4

FM1 FM0 MODE

0 0 Single-Speed Mode: 4 to 50 kHz sample rates (default)
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
1 1 Direct Stream Digital Mode

Table 4. Functional Mode Selection

DS459PP1 17

CS4392

4.2 Volume and Mixing Control (Address 02h)

76543210

A = B Soft Zero Cross ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

4.2.1 Channel A Volume = Channel B Volume (Bit 7)

Function:

The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol­ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de­termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function
is enabled.

4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock
periods.

Zero Cross Enable

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon­itored and implemented for each channel.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 5

SOFT ZERO Mode

0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled (default)
1 1 Soft Ramp and Zero Cross enabled

Table 5. Soft Cross or Zero Cross Mode Selection

4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0)

Function:

The CS4392 implements the channel mixing functions of the ATAPI CD-ROM specification. See
Table 6 on page 19

18 DS459PP1

CS4392

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

00000 MUTE MUTE
00001 MUTE bR
00010 MUTE bL
00011 MUTE b[(L+R)/2]
00100 aR MUTE
00101 aR bR
00110 aR bL
00111 aR b[(L+R)/2]
01000 aL MUTE
01001 aL bR
01010 aL bL
01011 aL b[(L+R)/2]
01100 a[(L+R)/2] MUTE
01101 a[(L+R)/2] bR
0 1 1 1 0 a[(L+R)/2] bL
0 1 1 1 1 a[(L+R)/2] b[(L+R)/2]
10000 MUTE MUTE
10001 MUTE bR
10010 MUTE bL
10011 MUTE [(bL+aR)/2]
10100 aR MUTE
10101 aR bR
10110 aR bL
10111 aR [(aL+bR)/2]
11000 aL MUTE
11001 aL bR
11010 aL bL
11011 aL [(aL+bR)/2]
11100 [(aL+bR)/2] MUTE
11101 [(aL+bR)/2] bR
11110 [(bL+aR)/2] bL
1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

Table 6. ATAPI Decode

Left Channel

Audio Data

A Channel

Volume
Control

MUTE

AoutA

ΣΣ

Right Channel

Audio Data

Figure 8. ATAPI Block Diagram

DS459PP1 19

B Channel

Volume
Control

MUTE

AoutB

4.3 Channel A Volume Control - Address 03h

CS4392

See 4.4

Channel B Volume Control - Address 04h

4.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H

76543210

MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

4.4.1 Mute (Bit 7)

Function:

The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the
output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft
and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will
go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC
will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled.

4.4.2 Volume Control (Bits 6:0)

Function:

The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -127 dB.
Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by
the Soft and Zero Cross bits in the Volume and Mixing Control register (see section 4.2.2).

Binary Code Decimal Value Volume Setting

0000000 0 0 dB
0010100 20 -20 dB
0101000 40 -40 dB

0111100 60 -60 dB

1011010 90 -90 dB

Table 7. Digital Volume Control Example Settings

4.5 Mode Control 2 - Address 05h

76543210

INVERT_A INVERT_B CPEN PDN MUTEC A = B FREEZE MCLK Divide Reserved

4.5.1 Invert Signal Polarity (Bits 7:6)

Function:

When set to 1, this bit inverts the signal polarity for the appropriate channel. This is useful if a board
layout error has occurred, or an other situations where a 180 degree phase shift is desirable. Default
is 0.

20 DS459PP1

4.5.2 Control Port Enable (Bit 5)

Function:

This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power­up, the user should write 30h to register 5 within 10 ms following the release of Reset.

4.5.3 Power Down (Bit 4)

Function:

The device will enter a low-power state whenever this function is activated (set to 1). The power-down

bit defaults to ‘enabled’ (1) on power-up and must be disabled before normal operation will begin. The
contents of the control registers are retained when the device is in power-down.

4.5.4 AMUTEC = BMUTEC (Bit 3)

Function:

When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con­nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.

CS4392

4.5.5 Freeze (Bit 2)

Function:

This function allows modifications to the control port registers without the changes taking effect until
Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously,
set the Freeze Bit, make all register changes, then Disable the Freeze bit.

4.5.6 Master Clock Divide (Bit 1)

Function:

This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in 8.

4.6 Mode Control 3 - Address 06h

B7 B6 B5 B4 B3 B2 B1 B0

Reserved Reserved Reserved Filt_rolloff rst_rmp_up rst_rmp_dwn Reserved Reserved

4.6.1 Interpolation Filter Select (Bit 4)

Function:

This Function allows the user to select whether the Interpolation Filter has a fast (set to 0 - default) or
slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of
the roll of is greater for the ‘fast’ roll off filter.

DS459PP1 21

4.6.2 Soft Volume Ramp-up after Reset (Bit 3)

Function:

This function allows the user to control whether a soft ramp up in volume is applied when reset is re­leased either by the reset pin or internal to the chip. The modes are as follows:

0 - An instantaneous change is made from max attenuation to the control port volume setting on re­lease of reset (default setting).
1 - Volume is ramped up using the soft-ramp settings in Bits 6:5 of register 02h (see 4.2.2) from max
attenuation to the control port volume setting on release of reset.

4.6.3 Soft Ramp-down before Reset (Bit 2)

Function:

This function allows the user to control if a soft ramp-down in volume is applied before a known reset
condition. The modes are as follows:

0 - An instantaneous change is made from the control port volume setting to max attenuation when
chip resets (default setting).
1 - Volume is ramped down using the soft-ramp settings in Bits 6:5 of register 02h (see 4.2.2) from
the control port volume setting to max attenuation when chip resets.

CS4392

4.7 Chip ID - Register 07h

B7 B6 B5 B4 B3 B2 B1 B0

PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

Function:

This register is Read-Only. Bits 7 through 4 are the part number ID which is 1000b (8h) and the re­maining Bits (3 through 0) are for the chip revision.

22 DS459PP1

5. PIN DESCRIPTION - PCM DATA MODE

CS4392

Reset RST AMUTEC Channel A Mute Control

Logic Voltage V L AOUTA- Differential Output

Serial Data SDATA AOUTA+ Differential Output

Serial Clock SCLK VA Analog Power

Left/Right Clock LRCK AGND Analog Ground

Master Clock M CLK AOUTB+ Differential Output
See Description M3 AOUTB- Differential Output
See Description (SCL/CCLK) M2 BMUTEC Channel B Mute Control
See Description (SDA/CDIN) M1 CMOUT Common Mode Voltage
See Description (AD0/CS

RST 1

VL

SDATA

SCLK 4
LRCK 5

1
2
3
4
5
6
7
8
9

) M0 FILT+ Positive Voltage Reference

Reset (

nal state machine is reset to the default setting when low (0). When high (1), the
device becomes operational.
Control Port Mode: The device enters a low power mode and all internal registers
are reset to the default settings, including the control port, when low. When high, the
control port becomes operational and the PDN bit must be cleared before normal
operation will occur. The control port can not be accessed when reset is low. The
Control Port Enable Bit must also be enabled after a device reset.
RST
stable.

2

Interface Power (
The voltage on this pin determines the logic level high threshold for the digital inputs.
The voltage on VL is the maximum allowable input level for all digital inputs.

3

Serial Audio Data (
pin. The data is clocked into SDATA via the serial clock and the channel is deter­mined by the Left/Right clock.

Serial Clock (
Left / Right Clock (

rently being input on the serial audio data input, SDATA. The frequency of the
Left/Right clock must be at the input sample rate. Audio samples in Left/Right sam­ple pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference.

Input

) - Hardware Mode: The device enters a low power mode and the inter-

is required to remain low until the power supplies and clocks are applied and

PCM Data Mode Pin Descriptions

10

Input

Input

Input

) - Clocks the individual bits of the serial data into the SDATA pin.

Input

20
19
18
17
16
15
14
13

12
11

) - Digital interface power supply. Typically 1.8 to 5.0 VDC.

) - Two’s complement MSB-first serial data is input on this

) - The Left / Right clock determines which channel is cur-

DS459PP1 23

CS4392

MCLK

Mode

(sample-rate range)

MCLK Ratio 256x 384x 512x 786x 1024x*

Single Speed

(4 to 50 kHz)

MCLK Ratio 128x 192x 256x 384x 512x*

Double Speed

(50 to 100 kHz)

MCLK Ratio 64x 96x 128x 192x 256x*

Quad Speed

(100 to 200 kHz)

14. *Note: these modes are only available in control port mode.

6

Master Clock (

Input

) - the master clock frequency must be either 256x, 384x, 512x,
768x or 1024x the input sample rate in Single Speed Mode; either 128x, 192x 256x,
384x or 512x the input sample rate in Double Speed Mode; or 64x, 96x 128x, 192x
or 256 x the input sample rate in Quad Speed Mode. Table 8 illustrates the standard
audio sample rates and the required master clock frequencies.

Sample

Rate

MCLK (MHz)

Control port
only modes

(kHz)

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 2 2.57 92 33.8688 45.1584
96 12.2880 18. 432 0 24.5760 36.8640 49.15 20

176.4 11.2896 16.9344 22.5792 33.8688 45.1584
192 12.2880 18.4320 24.5760 36.8640 49.1520

Table 8. Common Clock Frequencies

M3
(Control Port Mode)

SDA/CDIN
(Control Port Mode)

SCL/CCLK
(Control Port Mode)

AD0 / CS
(Control Port Mode)

7

Mode Select (

Inputs

) - The Mode Select Pin, M3, is not used in PCM Control Port

mode and should be terminated to ground.

8

Serial Control Data I/O (

Input/Output

) - In Two-Wire mode, SDA is a data I/O line.

CDIN is the input data line for the control port interface in SPI mode.

9

Serial Control Interface Clock (

Input

) - Clocks the serial control data into or from

SDA/CDIN.

10

Address Bit / Chip Select (

Input

) - In Two-Wire mode, AD0 is a chip address bit. CS
is used to enable the control port interface in SPI mode. The device will enter the
SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain in SPI mode until either the part is reset or
undergoes a power-down cycle.

PCM Data Mode Pin Descriptions

24 DS459PP1

CS4392

M3, M2, M1 and M0
(Stand-alone Mode)

M3 M1

(DIF1)

00 0
00 1

01 0
01 1

Table 9. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options

M3 M2

7, 8, 9,
and 10

(DIF0)

Mode Select (

Inputs

) - The Mode Select Pins, M0-M3, select the operational mode

of the device while in stand-alone mode.

M0

DESCRIPTION FORMAT FIGURE

Left Justified, up to 24-bit data

2

S, up to 24-bit data

I
Right Justified, 16-bit Data
Right Justified, 24-bit Data

DESCRIPTION FIGURE

09
110

211
312

(DEM)

00
01

No De-Emphasis
De-Emphasis Enabled

7
7

Table 10. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options

M3 M2 M1 M0 DESCRIPTION FORMAT FIGURE

1000
1001

1010
1011

Table 11. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options

Left Justified up to 24-bit data

2

I

S up to 24-bit data
Right Justified 16-bit data
Right Justified 24-bit data

09
110

211
312

M3 M2 M1 M0 DESCRIPTION FORMAT FIGURE

1100
1101

1110
1111

Left Justified up to 24-bit data

2

I

S up to 24-bit data
Right Justified 16-bit data
Right Justified 24-bit data

09
110

211
312

Table 12. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options

FILT+

11

Positive Voltage Reference (

Output

) - Positive reference for internal sampling cir­cuits. External capacitors are required from FILT+ to analog ground, as shown in
Figure 5. The recommended values will typically provide 60 dB of PSRR at 1 kHz
and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FIL T+
has a typical source impedance of 250 kΩ and any current drawn from this pin will
alter device performance.

CMOUT

12

Common Mode Voltage (

Output

) - Filter connection for internal common mode refer­ence voltage, typically 50% of VA. Capacitors must be connected from CMOUT to
analog ground, as shown in Figure 5. CMOUT is not intended to supply external
current. CMOUT has a typical source impedance of 250 kΩ and any current drawn
from this pin will alter device performance.

PCM Data Mode Pin Descriptions

DS459PP1 25

CS4392

AMUTEC and
BMUTEC

AOUTB+, AOUTB­and AOUTA+,
AOUTA

AGND 16

VA

13 and

20

14, 15,
18, and

19

17

Channel A and Channel B Mute Control (
during power-up initialization, reset, muting, when master clock to left/right clock fre­quency ratio is incorrect, or power-down. These pins are intended to be used as a
control for an external mute circuit to prevent the clicks and pops that can occur in
any single supply system. Use of Mute Control is not mandatory but recommended
for designs requiring the absolute minimum in extraneous clicks and pops.

Differential Analog Audio Output (
specified in the Analog Charact er is tic s specifi c atio n table .

Analog Ground (
ground.

Analog Power (

Input

) Analog ground reference. Should be connected to analog

Input

) - Analog power supply. Typically 5 VDC.

PCM Data Mode Pin Descriptions

Output

Output

) - The Mute Control pins go high

) - The fullscale differential output level is

26 DS459PP1

6. PIN DESCRIPTION - DSD MODE

CS4392

Reset RST AMUTEC Refer to PCM Mode

Logic Voltage VL AOUTA- Refer to PCM Mode
Channel A Data DSD_A AOUTA+ Refer to PCM Mode
Channel B Data DSD_B VA Refer to PCM Mode

DSD Mode Select DSD_MODE AGND Refer to PCM Mode

Master Clock M CLK AOUTB+ Refer to PCM Mode

DSD Serial Clock DSD_SCLK AOUTB- Refer to PCM Mode
Refer to PCM Mode (SCL/CCLK) M2 BMUTEC Refer to PCM Mode
Refer to PCM Mode (SDA/CDIN) M1 CMOUT Refer to PCM Mode
Refer to PCM Mode (AD0/CS

RST 1

VL

DSD_A and DSD_B

DSD_Mode

MCLK

DSD_SCLK

2

3 and 4

5

6

7

Reset (

state machine is reset to the default setting when low (0). When high (1), the device
becomes operational.
Control Port Mode: The device enters a low power mode and all internal registers
are reset to the default settings, including the control port, when low. When high, the
control port becomes operational and the PDN bit must be cleared before normal
operation will occur. The control port can not be accessed when reset is low. The
Control Port Enable Bit must also be enabled after a device reset.
RST
stable.

Interface Power (
The voltage on this pin determines the logic level high threshold for the digital inputs.
The voltage on VL is the maximum allowable input level for all digital inputs.

DSD Audio Data

and DSD_B via the DSD serial clock.

DSD Mode

set to access the DSD Mode in Stand-Alone Mode. Refer to Table 13.In Control Port
Mode, this pin must be set to a logic ‘1’ and the Control Registers must be properly
set to access the DSD Mode. Refer to register descriptions in Section 4.

Master Clock

the DSD data rate for 64x oversampled DSD data or 2x, 3x, 4x or 6x the DSD data
rate for 128x oversampled DSD data.

DSD Serial Clock

DSD_A and DSD_B pins.

) M0 FILT+ Refer to PCM Mode

Input

) - Hardware Mode: The device enters a low power mode and the internal

is required to remain low until the power supplies and clocks are applied and

(Input) -

1
2
3
4
5
6
7
8
9
10

Input

(Inputs) -

This pin must be set to a logic ‘1’ and M0-M2 must be properly

(Input) -

(Input) -

DSD Mode Pin Descriptions

20
19
18
17

16
15
14
13

12
11

) - Digital interface power supply. Typically 1.8 to 5.0 VDC.

Direct Stream Digital audio data is clocked into DSD_A

The master clock frequency must be either 4x, 6x, 8x or 12x

Clocks the individual bits of the DSD audio data into the

DS459PP1 27

CS4392

M2, M1 and M0
(Stand-alone Mode)

8, 9,

and 10

Mode Select (

Inputs

) - The Mode Select Pins, M0-M2, select the operational mode of

the device while in stand-alone mode.

DSD_Mode M2 M1 M0 DESCRIPTION

1000
1001
1010
1011
1100
1101
1110
1111

64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 13. Direct Stream Digital (DSD), Stand-Alone Mode Options

SDA/CDIN
(Control Port Mode)

SCL/CCLK
(Control Port Mode)

AD0 / CS
(Control Port Mode)

8

Serial Control Data I/O (

Input/Output

) - In Two-Wire mode, SDA is a data I/O line.

CDIN is the input data line for the control port interface in SPI mode.

9

Serial Control Interface Clock (

Input

) - Clocks the serial control data into or from

SDA/CDIN.

10

Address Bit / Chip Select (

Input

) - In Two-Wire mode, AD0 is a chip address bit. CS is
used to enable the control port interface in SPI mode. The device will enter the SPI
mode at anytime a high to low transition is detected on this pin. Once the device has
entered the SPI mode, it will remain in SPI mode until either the part is reset or under­goes a power-down cycle.

FILT+

Positive Voltage Reference (

Output

) - Positive reference for internal sampling cir-

11

cuits. External capacitors are required from FILT+ to analog ground, as shown in Fig­ure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40
dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FIL T+ has a
typical source impedance of 250 kΩ and any current drawn from this pin will alter
device performance.

CMOUT

12

Common Mode Voltage (

Output

) - Filter connection for internal common mode refer­ence voltage, typically 50% of VA. Capacitors must be connected from CMOUT to
analog ground, as shown in Figure 6. CMOUT is not intended to supply external cur­rent. CMOUT has a typical source impedance of 250 kΩ and any current drawn from
this pin will alter device performance.

AMUTEC and
BMUTEC

13 and

Channel A and Channel B Mute Control (

20

ing power-up initialization, reset, muting, when master clock to left/right clock fre-

Output

) - The Mute Control pins go high dur-

quency ratio is incorrect, or power-down. These pins are intended to be used as a
control for an external mute circuit to prevent the clicks and pops that can occur in
any single supply system. Use of Mute Control is not mandatory but recommended
for designs requiring the absolute minimum in extraneous clicks and pops.

AOUTB+, AOUTB­and AOUTA+,
AOUTA

AGND 16

14, 15,

18, and

19

Differential Analog Audio Output (

Output

) - The fullscale differential output level is

specified in the Analog Charact er is tic s specifi c atio n table .

Analog Ground (

Input

) Analog ground reference. Should be connected to analog

ground.

VA

Analog Power (

Input

) - Analog power supply. Typically 5 VDC.

17

DSD Mode Pin Descriptions

28 DS459PP1

CS4392

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Figure 9. Format 0, Left Justified up to 24-Bit Data

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Figure 10. Format 1, I2S up to 24-Bit Data

LSB

LSB

MSB

-1 -2 -3 -4

MSB

-1 -2 -3 -4

Right Channel

+3 +2 +1

+5 +4

Right Channel

+3 +2 +1

+5 +4

LSB

LSB

LRCK

SCLK

SDATA

LRCK

SCLK

SDATA

Left Channel

15 14 13 12 11 10

32 clocks

6543210987

15 14 13 12 11 10

Right Channel

6543210987

Figure 11. Format 2, Right Justified 16-Bit Data

Left Channel

0

23 22 21 20 19 18

32 clocks

65432107

23 22 21 20 19 18

Right Channel

65432107

Figure 12. Format 3, Right Justified 24-Bit Data

DS459PP1 29

CS4392

LRCK

SCLK

DATA

LRCK

SCLK

SDATA

Left Channel

10

10 6543210987

17 16 17 16

19 18 19 18

Figure 13. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)

Figure 14. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)

15 14 13 12 11 10

32 clocks

Left Channel

17 16 17 16

15 14 13 12 11 10

32 clocks

6543210987

6543210987

15 14 13 12 11 10

15 14 13 12 11 10

Right Channel

Right Channel

6543210987

30 DS459PP1

CS4392

7. APPLICATIONS

7.1 Recommended Power-up Sequence
for Hardware Mode

1) Hold RST low until the power s upplies, master,

and left/right clocks are stable.

2) Bring RST high.

7.2 Recommended Power-up Sequence
and Access to Control Port Mode

1) Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the
control port is reset to its default settings and
CMOUT will remain low.

2) Bring RST high. The device will remain in a

low power state with CMOUT low and the con­trol port is accessible.

3) Write 30h to register 05h within 10 ms follow-

ing the release of RST.

4) The desired register settings can be loaded

while keeping the PDN bit set to 1.

5) Set the PDN bit to 0 which will i nitiate the pow-

er-up sequence which requires approximately

10 µ S.

7.3 Analog Output and Filtering

The application note “Design Notes for a 2-Pole
Filter with Differential Input” discusses the sec­ond-order Butterworth filter and differential to sin­gle-ended converter which was implemented on the
CS4392 evaluation board, CDB4392, as seen in
Figure 15. The CS4392 filter is a linear phase de­sign and does not include phase or amplitude com­pensation for an external filter. Therefore, the
DAC system phase and amplitude response will be
dependent on the external analog circuitry.

7.4 Interpolation Filter

To accommodate the increasingly complex re­quirements of digital audio systems, the CS4392
incorporates selectable interpolation filters for each
mode of operation. A “fast” and a “slow” r oll-off
filter is available in each of Single, Double, and
Quad Speed modes. These filters have been de­signed to accommodate a variety of musical tastes
and styles. Bit 5 of the Mode Control 3 register
(06h) is used to select which filter is used. When
the part is used without the control port, the “fast”
roll-off filter is selected.

DS459PP1 31

2700 pF

u

CS4392

3.32k

680 pF

Aout -

Aout +

10 uF 560

10 uF

3.01k 1.58k

3.01k

2700 pF

R17

3.32k

1.58k

C10

680 pF

-

2

3

1

+

10 uF

Figure 15. CS4392 Output Filter

Analog_O

47k

32 DS459PP1

CS4392

8. CONTROL PORT INTERFACE

The control port is used to load all the internal set­tings of the CS4392. The operation of the control
port may be completely asynchronous to the audio
sample rate. However, to avoid potential interfer­ence problems, the control port pins should remain
static if no operation is required.

The control port has 2 modes: SPI and Two-Wire,
with the CS4392 operating as a slave device in both
modes. If Two-Wire operation is desired, AD0/CS
should be tied to VA or AGND. If the CS4392 ever
detects a high to low transition on AD0/CS after
power-up, SPI mode will be selected. The control
port registers are write-only in SPI mode.

Upon release of the /RST pin, the CS4392 will wait
approximately 100 ms before it begins its power­up sequence. The part defaults to Stand-Alone
Mode, in which all operational modes are con­trolled as described in tables 9 through 12. The con­trol port is active at all times, and if bit 5 of register
05h is set, the part enters Control-Port Mode and all
operational modes are controlled by the control
port registers. This bit can be set at any time, b ut to
avoid unpredictable output noises, bit 5 and bit 4 of
register 05h should be set before the end of the
100 ms power-up wait period. All registers can
then be set as desired before releasing bit 4 of reg­ister 05h to begin the power-up sequence. If system
requirements do not allow writing to the control
port immediately following the release of /R ST, the

SDATA line should be held at logic “0” until the
proper serial mode can be selected.

8.1 SPI Mode

In SPI mode, CS is the CS4392 chip select signal,
CCLK is the control port bit cl ock, C DIN i s the in­put data line from the microcontroller and the chip
address is 0010000. All signals are inputs and data
is clocked in on the rising edge of CCLK.

Figure 16 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and

must be 0010000. The eighth bit is a read/write in­dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into the register designated by
the MAP. See Table 14 on page 34.

The CS4392 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc­cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.

8.2 Two-Wire Mode

In Two-Wire mode, SDA is a bi-directional data
line. Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
shown in Figure 3. There is no CS pin. Pin AD0
forms the partial chip address and should be tied to
VA or AGND as required. The upper 6 bits of the 7­bit address field must be 001000. To communicate
with the CS4392 the LSB of the chip address field,
which is the first byte sent to the CS4392, should
match the setting of the AD0 pin. The eighth bit of
the address byte is the R/W bit (high for a read, low
for a write). If the operation is a write, the next byte
is the Memory Address Pointer, MAP, which selects
the register to be read or written. The MAP is then
followed by the data to be written. If the operation
is a read, then the contents of the register pointed to
by the MAP will be output after the chip address.

The CS4392 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc­cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.

Two-Wire mode is compatible with I2C. For more
information on I2C, please see “The I2C-Bus
Specification: Version 2.0”, listed in the Referenc­es section.

DS459PP1 33

CS4392

76543210

INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP0

00000000

INCR (Auto MAP Increment Enable)

Default = ‘0’.
0 - Disabled
1 - Enabled

MAP0-2 (Memory Address Pointer)

Default = ‘000’.

Table 14. Memory Address Pointer (MAP)

CS

CCLK

CDIN

CHIP

ADDRESS

0010000

R/W

MAP

MSB

byte 1

DATA

LSB

byte n

MAP = Memory Address Pointer

Figure 16. Control Port Timing, SPI mode

Note 1

SDA

SCL

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

001000

Start

ADDR
AD0

R/W

ACK

DATA
1-8

ACK

DATA
1-8

ACK

Figure 17. Control Port Timing, Two-Wire Mode

Stop

34 DS459PP1

9. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So­ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS4392

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

10.REFERENCES

1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2. CDB4392 Evaluation Board Datasheet

3. “The I

2

C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.

http://www.semiconducto rs.philips.com

DS459PP1 35

11.PACKAGE DIMENSIONS

20L TSSOP (4.4 mm BODY) PACKAGE DRAWING

N

CS4392

1

23

TOP VIEW

D

E

e

b

SIDE VIEW

A2

A1

A

SEATING

PLANE

INCHES MILLIMETERS

L

E1

END VIEW

NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.252 0.256 0.259 6.40 6.50 6.60 1

E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- -- 0.026 -- -- 0.65

L 0.020 0.024 0.028 0.50 0.60 0.70

∝

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips

36 DS459PP1

CS4392

.

20L SOIC (300 MIL BODY) PACKAGE DRAWING

HE

1

b

c

D

SEATING

PLANE

A

e

A1

L

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A 0.093 0.098 0.104 2.35 2.50 2.65

A1 0.004 0.008 0.012 0.10 0.20 0.30

b 0.013 0.017 0.020 0.33 0.43 0.51
C 0.009 0.011 0.013 0.23 0.28 0.32
D 0.496 0.504 0.512 12.60 12.80 13.00

E 0.291 0.295 0.299 7.40 7.50 7.60

e 0.040 0.050 0.060 1.02 1.27 1.52
H 0.394 0.407 0.419 10.00 10.34 10.65

L 0.016 0.025 0.050 0.40 0.64 1.27

∝ 0° 4° 8° 0° 4° 8°

JEDEC #: MS-013

Controlling Dimension is Millimeters

∝

DS459PP1 37