Crystal CS4392 Advance Product Data

CS4392

24-Bit, 192 kHz Stereo DAC with Volume Control

Features

l Complete Stereo DAC System: Inte rpolation,

D/A, Output Analog Filtering

l 114 dB Dynamic Range
l 100 dB THD+N
l Up to 192kHz Sample Rates
l Direct Stream Digital Mode
l Low Clock Jitter Sensitivity
l Single +5 V Power Supply
l Selectable Digital Filters

– Fast and Slow roll-off

l Volume Co ntrol with Sof t Ramp

– 1 dB Step Size
– Zero Crossing Click-Free Transitions

l Direct Interface with 5 V to 1.8 V Logic
l ATAPI mixing functions
l Pin compatible with the CS4391

I

Description

The CS4392 is a comple te stereo digita l-to-analog s ys­tem including digital interpolation, fifth-order delta-sigma
digital-to-analog conversion, digital de-emphasis, vol­ume control, channel mixing and analog filtering. The
advantages of this archi tec ture i nc lud e: id eal di fferent ial
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera­ture, and a high tolerance to clock jitter.

The CS4392 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, has selectable digital
filters, and co nsumes very little power . These features
are ideal for DVD, SACD players, A/V receivers, CD and
set-top box systems. The CS4392 is pin and register
compatible with the CS4 391, m aking ea sy p erforma nce
upgrades possible.

ORDERING INFORMATION

CS4392-KS -10 to 70 °C 20-pin SOIC
CS4392-KZ -10 to 70 °C 20-pin TSSOP
CDB4392 Evaluation Board

M1

(SDA/CDIN)

RST

SCLK

LRCK

SDATA

SERIAL

PORT

Advance Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

M2

(SCL/CCLK) (AD0/CS)

M3

MODE SELECT

(CONTROL PORT)

VOLUME

CONTROL

MIXER

VOLUME

CONTROL

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

M0

AMUTEC

EXTERNAL

MUTE CONTROL

INTERPOLATION

FILTER

INTERPOLATOR

FILTER

MCLK

Copyright  Cirrus Logic, Inc. 2000

(All Rights Reserved)

∆Σ

DAC

∆Σ

DAC

CMOUT

REFERENCE

FILT+BMUTEC

ANALOG

FILTER

ANALOG

FILTER

AOUTA+

AOUTA-

AOUTB+

AOUTB-

OCT ‘00

DS459PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS .................................................................................5

ANALOG CHARACTERISTICS................................................................................................ 5

POWER AND THERMAL CHARACTERISTICS . ....... ............................................. ..................7

DIGITAL CHARACTERISTICS................................................................................................. 8

ABSOLUTE MAXIMUM RATINGS ...........................................................................................8

RECOMMENDED OPERATING CONDITIONS.......................................................................8

SWITCHING CHARACTERISTICS - PCM MODES................................................................. 9

SWITCHING CHARACTERISTICS - DSD..............................................................................10

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE.......................11

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE....................................12

2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 13

3. REGISTER QUICK REFERENCE .......................................................................................... 15

4. REGISTER DESCRIPTION .................................................................................................... 16

4.1 Mode Control 1 - Address 01h ......................................................................................... 16

4.1.1 Auto-Mute (Bit 7) .................................................................................................16

4.1.2 Digital Interface Formats (Bits 6:4) ......................................................................16

4.1.3 De-Emphasis Control (Bits 3:2) ...........................................................................17

4.1.4 Functional Mode (Bits 1:0) .................................................................................. 17

4.2 Volume and Mixing Control (Address 02h) ...................................................................... 18

4.2.1 Channel A Volume = Channel B Volume (Bit 7) ................................................. 18

4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) .........................................................18

4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ......................................................18

4.3 Channel A Volume Control - Address 03h ....................................................................... 20

4.4 Channel B Volume Control - Address 04h........................................................................ 20

4.4.1 Mute (Bit 7) ......................... ....... ...... ....... ...... ...... ....... .......................................... 20

4.4.2 Volume Control (Bits 6:0) ....................................................................................20

4.5 Mode Control 2 - Address 05h ......................................................................................... 20

4.5.1 Invert Signal Polarity (Bits 7:6) ............................................................................20

4.5.2 Control Port Enable (Bit 5) .................................................................................. 21

4.5.3 Power Down (Bit 4) .............................................................................................21

4.5.4 AMUTEC = BMUTEC (Bit 3) ...............................................................................21

4.5.5 Freeze (Bit 2) ......................................... ...... ...... ....... ...... ....... ...... .......................21

4.5.6 Master Clock Divide (Bit 1) ..................................................................................21

CS4392

Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

I2C is a registered trademark of Ph ilips Semiconductors.
Preliminary product inf o rmation describes products whi ch are in production, b ut f or whi c h ful l char act er iza t i on da ta i s not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s
of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be pri nted for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.

2 DS459PP1

CS4392

4.6 Mode Control 3 - Address 06h ......................................................................................... 21

4.6.1 Interpolation Filter Select (Bit 4) .......................................................................... 21

4.6.2 Soft Volume Ramp-up after Reset (Bit 3) ........................................................... 22

4.6.3 Soft Ramp-down before Reset (Bit 2) .......................................... ....... ...... ....... ... 22

4.7 Chip ID - Register 07h .....................................................................................................22

5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 23

6. PIN DESCRIPTION - DSD MODE .......................................................................................... 27

7. APPLICATIONS ..................................................................................................................... 31

7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 31

7.2 Recommended Power-up Sequence and Access to Control Port Mode ......................... 31

7.3 Analog Output and Filtering ............................................................................................. 31

7.4 Interpolation Filter ............................................................................................................ 31

8. CONTROL PORT INTERFACE ............................................. ................................................. 33

8.1 SPI Mode ......................................................................................................................... 33

8.2 Two-Wire Mode ............................................................................................................... 33

9. PARAMETER DEFINITIONS .................................................................................................. 35

Total Harmonic Distortion + Noise (THD+N) ................................................................... 35

Dynamic Range ............................................................................................................... 35

Interchannel Isolation ...................................................................................................... 35

Interchannel Gain Mismatch ........................................................................................... 35

Gain Error........................................................................................................................ 35

Gain Drift ......................................................................................................................... 35

10. REFERENCES ...................................................................................................................... 35

11. PACKAGE DIMENSIONS ................................................................................................. 36

DS459PP1 3

LIST OF TABLES

Table 1. Digital Interface Formats - PCM Modes .......................................................................... 16

Table 2. Digital Interface Formats - DSD Mode ............................................................................17

Table 3. De-Emphasis Mode Selection........................................................................................17

Table 4. Functional Mode Selection..............................................................................................17

Table 5. Soft Cross or Zero Cross Mode Selection......................................................................18

Table 6. ATAPI Decode.................................................................................................................19

Table 7. Digital Volume Control Example Settings........................................................................20

Table 8. Common Clock Frequencies...........................................................................................24

Table 9. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options..........25

Table 10. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ...............25

Table 11. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options ..25
Table 12. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ... 25

Table 13. Direct Stream Digital (DSD), Stand-Alone Mode Options .............................................28

Table 14. Memory Address Pointer (MAP).................................................................................... 34

LIST OF FIGURES

Figure 1. Serial Mode Input Timing .............................................. ....... ...... ...................................... 9

Figure 2. Direct Stream Digital - Serial Audio Input Timing...........................................................10

Figure 3. Two-Wire Mode Control Port Timing..............................................................................11

Figure 4. SPI Control Port Timing ............................. ............................................. ....................... 1 2

Figure 5. Typical Connection Diagram - PCM Mode.....................................................................13

Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 14

Figure 7. De-Emphasis Curve............................. ...... .................................................................... 1 7

Figure 8. ATAPI Block Diagram .................................................................................................... 19

Figure 9. Format 0, Left Justified up to 24-Bit Data....................................................................... 29

Figure 10. Format 1, I2S up to 24-Bit Data ...................................................................................29

Figure 11. Format 2, Right Justified 16-Bit Data ........................................................................... 29

Figure 12. Format 3, Right Justified 24-Bit Data ........................................................................... 29

Figure 13. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 30

Figure 14. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 30

Figure 15. CS4392 Output Filter ................................................................................................... 32

Figure 16. Control Port Timing, SPI mode ....................................................................................34

Figure 17. Control Port Timing, Two-Wire Mode...........................................................................34

CS4392

4 DS459PP1

1. CHARACTERISTICS/SPECIFICATIONS

CS4392

ANALOG CHARACTERISTICS (T

put Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Sample Rate = 48, 96, or 192 kHz, 24-bit data,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

Parameter

= 25° C; Logic "1" = VL = VA; Logic "0" = AG ND; Full -Scale Ou t-

A

= 3 kΩ, CL = 10 pF)

L

VA = 5 V

Symbol Min Typ Max Unit

Dynamic Performance - Single Speed Mode (48kHz)

Dynamic Range (Note 1) unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1) 0 dB

-20 dB

-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N -

TBD
TBD

-

-

111
114

-100

-91

-51

-

-

TBD

-

TBD

dB
dB

dB
dB
dB

Dynamic Performance - Double Speed Mode (96kHz)

Dynamic Range (Note 1) unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1) 0 dB

-20 dB

-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N -

TBD
TBD

-

-

111
114

-100

-91

-51

-

-

TBD

-

TBD

dB
dB

dB
dB
dB

Dynamic Performance - Quad Speed Mode (192kHz)

Dynamic Range (Note 1) unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1) 0 dB

-20 dB

-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N -

TBD
TBD

-

-

111
114

-100

-91

-51

-

-

TBD

-

TBD

dB
dB

dB
dB
dB

Parameter Symbol Min Typ Max Units

Analog Output

Full Scale Differential Output Voltage TBD 1.0xVA TBD Vpp
Common Mode Voltage CMOUT - 0.5xVA - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
AC-Load Resistance R
Load Capacitance C

DS459PP1 5

L
L

3--kΩ

--100pF

CS4392

ANALOG CHARACTERISTICS (continued)

Fast Roll-Off Slow Roll-Off

Parameter Symbol

Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note2)

Passband (Note 3) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 -0.01 - +0.01 dB
StopBand .5465 - - .5834 - - Fs
StopBand Attenuation (Note 5) 90 - - 64 - - dB
Group Delay tgd - TBD - - TBD - s
Passband Group Delay Deviation 0 - 20 kHz - - TBD - TBD s
De-emphasis Error Fs = 32 kHz

(Relative to 1kHz) Fs = 44.1 kHz

Fs = 48 kHz

0
0

-

-

-

-

-

-

-

-

.4535
.499800

±0.23
±0.14
±0.09

--0.4166

0.4998FsFs

-

-

-

-

±0.23

-

±0.14

-

±0.09

Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 2)

Passband (Note 4) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .5834 - - .7917 - - Fs
StopBand Attenuation (Note 5) 80 - - 70 - - dB
Group Delay tgd - TBD - - TBD - s
Passband Group Delay Deviation 0 - 20 kHz - - TBD - - TBD s

0
0

-

-

.4166
.499800

-

-

.2083
.4998FsFs

Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 2)

Passband (Note 4) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .6355 - - .8683 - - Fs
StopBand Attenuation (Note 5) 75 - - 75 - - dB
Group Delay tgd - TBD - - TBD - s
Passband Group Delay Deviation 0 - 20 kHz - - TBD - - TBD s

0
0

-

-

.1046
.489700

-

-

.1042
.4813FsFs

Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 2)

Passband (Note 4) to -3 dB corner TBD - TBD TBD - TBD Fs
Frequency Response 10 Hz to 20 kHz TBD - TBD TBD - TBD dB

Notes: 1. Triangular PDF dit h er e d dat a.

2. Filter response is not tested but is guaranteed by design.

3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 5. Increasing
the capacitance will also increase the PSRR.

4. Response is clock dependent and will scale with Fs.

5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.

UnitMin Typ Max Min Typ Max

dB
dB
dB

6 DS459PP1

CS4392

POWER AND THERMAL CHARACTERISTICS GND = 0 V ( All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Base-rate Mode

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA=5V
Normal Operation VL=3V

Power Supply Current- VA=5V
Power Down Mode (Note 6) VL=3V

Power Supply Current- VA=5V
Normal Operation VL=5V

Power Supply Current- VA=5V
Power Down Mode (Note 6) VL=5V

Total Power Dissipation- All Supplies=5V
Normal Operation VA=5V, VL=1.8V

Package Thermal Resistance θ
Power Supply Rejection Ratio (Note 7) 1 kHz

60 Hz

I

A

I

D_L

I

A

I

D_L

I

A

I

D_L

I

A

I

D_L

JA

PSRR -

-

--

-

-

-

-

-

-

-

-

TBD
TBD

TBD
TBD

25

TBD

60

TBD

125

TBD

-

-

-

-

-

-

-

-

-

-

mA

µA
µA

µA

mA

µA
µA

µA

mW
mW

-TBD-°C/Watt
60

-

40

-

-

dB
dB

Notes: 6.

7. Valid with the recommended capacitor values on FILT+ as shown in Figure 5. Increasing the

GND = 0 V ( All voltages with respect to ground. All measurements taken with all zeros input and open

outputs, unless otherwise specified.) Power Down Mode is defined as RST
data lines held static.

capacitance will also increase the PSRR. NOTE: Care should be taken when selecting capacitor type,
as any leakage current in excess of 1.0 µA will cause degradation in analog performance.

= LO with all clocks and

DS459PP1 7

CS4392

DIGITAL CHARACTERISTICS (T

Parameters Symbol Min Typ Max Units

High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current I
Input Capacitance - 8 - pF

Maximum MUTEC Drive Current - 3 - mA

= 25° C)

A

V

IH

V

IL

in

70% - - VL

- 20% VL

--±10µA

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply VA

VL
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

in

IND

A

stg

-0.3

-0.3

- ±10 mA

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

6.0
VA

V
V

RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply VA

VL

4.75

1.8

5.0

-

5.5
VA

V
V

8 DS459PP1

CS4392

SWITCHING CHARACTERISTICS - PCM MODES (T

= -10 to 70° C; VL = 5.5 to 1.8 Volts;

A

Inputs: Logic 0 = 0 V, Logic 1 = VL, CL = 20 pF)

Parameters Symbol Min Typ Max Units

Input Sample Rate Fs 4 - 200 kHz
LRCK Duty Cycle 45 50 55 %
MCLK Duty Cycle 405060%
SCLK Frequency

SCLK Frequency Note 8
SCLK rising to LRCK edge delay t

SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t

slrd
slrs

sdlrs

sdh

-

­20 - - ns
20 - - ns
20 - - ns
20 - - ns

-MCLK/2Hz

-MCLK/4Hz

Notes: 8. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

LRCK

SCLK

SDATA

t

t

slrd

t

sdlrs

slrs

t

sdh

Figure 1. Serial Mode Input Timing

DS459PP1 9

CS4392

SWITCHING CHARACTERISTICS - DSD (T

Logic 1 = VL = 5.5 to 1.8 Volts; C

=20pF)

L

= -10 to 70° C; Logic 0 = AGND = DGND;

A

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 405060%
DSD_SCLK Pulse Width Low t

DSD_SCLK Pulse Width High t
DSD_SCLK Period t

DSD_L or DSD_R valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_L or DSD_R hold time t

DSD_SCLK

t

sdlrstsdh

sclkl

sclkh

sclkw

sdlrs

sdh

t

TBD - - ns
TBD - - ns
TBD

--ns

TBD - - ns
TBD - - ns

t

sclkh

sclkl

DSD_L, DSD_R

Figure 2. Direct Stream Digital - Serial Audio Input Timing

10 DS459PP1

CS4392

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE

(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)

Parameter Symbol Min Max Unit

Two-Wire Mode

SCL Clock Frequency f

Rising Edge to Start t

RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 10) t
SDA Setup time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t

scl

irs

buf

hdst

low

high

sust
hdd

sud

r
f

susp

-100KHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

-300ns

4.7 - µs

Notes: 9. The Two-Wire mode is compatible with the I

10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

RST

t

irs

Stop Start

SDA

SCL

t

buf

t

t

hdst

low

t

hdd

t

high

2

C protocol.

t

sud

Repeated

Start

t

sust

t

hdst

Stop

t

f

t

r

t

susp

Figure 3. Two-Wire Mode Control Port Timing

DS459PP1 11

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST
CCLK Edge to CS

High Time Between Transmissions t

CS

Falling to CCLK Edge t

CS

Falling (Note 11) t

CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 12) t
Rise Time of CCLK and CDIN (Note 13) t
Fall Time of CCLK and CDIN (Note 13) t

sclk

srs

spi
csh
css

scl
sch
dsu

dh

r2
f2

-6MHz
500 - ns
500 - ns

1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns

-100ns

-100ns

CS4392

Notes: 11. t

12. Data must be held for sufficient time to bridge the transition time of CCLK.

13. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz

SCK

RST

CS

CCLK

CDIN

t

srs

t

t

css

spi

tr2t

t

t

sch

scl

f2

t

t

dsu

dh

= 0 at all other times.

spi

t

csh

Figure 4. SPI Control Port Timing

12 DS459PP1