CRMT 24LLC02TS8, 24LLC02S8, 24LLC02N8 Datasheet

OVERVIEW

The 24LLC02 serial EEPROM has a 2,048-bit capacity, supporting the standard I2 C™-bus serial interface.
It is fabricated using Ceramate's most advanced CMOS technology. It has been developed for low power and low

voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for
the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP)
pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write
operation. Another significant feature of the 24LLC02

is its support for fast mode and standard mode.

FEATURES

I2C-Bus Interface

• Two-wire seri al interface

• Automatic word address increment

EEPROM

• 2K-bit (2,048-bit/256-byte) storage area

• 16-byte page buffer

• Hardware-based write protection for the entire

EEPROM (using the WP pin)

• EEPROM programming voltage generated
on chip

• 1,000,000 erase/write

cycles

• 100 years data retention

Operating Characteristics

• Operating voltage
— 1.8 V to 5.5 V

• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stan d-by current: < 5 µA at 5.5 V

• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)

• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode

• Electrostatic discharge (ESD)
— 5,000 V (HBM)
—

500 V (MM)

Packages

• 8-pin P-DIP , SOP , TSSOP

24LLC02

2K-bit Serial EEPROM for Low Power

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]
Tel:[phone] Http: www.ceramate.com.tw
Fax:[phone]

Page 1 of 19 Rev 1.2 May 6,2002

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]

ORDERING INFORMATION

24 LLC 02 X X

Operating Voltage Type Temp. grade Packing
LLC:1.8~5.5V,CMOS 02=2K Blank:-25℃~+70℃ Blank :Tube

A :Taping(SOP8)
T :Taping(TSSOP8)

Start/Stop

Logic

Slave Address

Comparator

Word Address

Pointer

Row

decoder

EEPROM
Cell Array

256 x 8 bits

HV Generation
Timing Control

Control Logic

Column Decoder

Data Register

DOUT and ACK

SCL

WP

SDA

A0
A1
A2

Figure 1-1. 24LLC02 Block Diagram

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]
Tel:[phone] Http: www.ceramate.com.tw
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Page 2 of 19 Rev 1.2 May 6,2002

24LLC02

2K-bit Serial EEPROM for Low Power

24LLC02

VCC WP SCL SDA

A0 A1 A2 VSS

NOTE: The 24LLC02 is available in 8-pin DIP, SOP,TSSOP package.

Figure 1-2. Pin Assignment Diagram

Table 1-1. 24LLC02 Pin Descriptions

Name Type Description Circuit

Type

A0, A1, A2 Input Input pins for device address selection. To configure a device address,

these pins should be connected to the VCC or V

SS

of the device.

These pins are internally pulled down to VSS.

1

V

SS

– Ground pin. –

SDA I/O Bi-directional data pin for the I2C-bus serial data interface. Schmitt

trigger input and open-drain output. An external pull-up resistor must
be connected to V

CC.

Typical values for this pull-up resistor are 4.7 kΩ

(100 kHz) and 1 kΩ (400 kHz).

3

SCL Input Schmitt trigger input pin for serial clock input. 2
WP Input

Input pin for hardware write protection control. If you tie this pin to V

CC,

the write function is disabled to protect previously written data in the
entire memory; if you tie it to VSS, the write function is enabled.

This pin is internally pulled down to VSS.

1

V

CC

– Single power supply. –

NOTE : See the following page for diagrams of pin circuit types 1, 2, and 3.

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]
Tel:[phone] Http: www.ceramate.com.tw
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Page 3 of 19 Rev 1.2 May 6,2002

24LLC02

2K-bit Serial EEPROM for Low Power

A0, A1,

A2, WP

Figure 1-3. Pin Circuit Type 1

SCL

Noise

Filter

Figure 1-4. Pin Circuit Type 2

SDA

VSS

Data Out

Noise

Filter

Data In

Figure 1-5. Pin Circuit Type 3

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]
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24LLC02

2K-bit Serial EEPROM for Low Power

FUNCTION DESCRIPTION

I2C-BUS INTERFACE
The 24LLC02 supports the I 2 C-bus serial interface data transmission protocol. The two-wire bus consists of a

serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V

CC by a

pull-up resistor that is located somewhere on the bus.

Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions
, controlling bus access. Using the A0, A1, and A2 input pins, up to eight 24LLC02 devices can be connected
to the same I2C-bus as slaves (see Figure 1-6). Both the master and slaves can operate as transmitter or receiver
, but the master device determines which bus operating mode would be active.

SDA

Bus Master

(Transmitter/

Receiver)

MCU

242LLC

Tx/Rx

A0 A1 A2

Slave 1

To VCC or V

SS

Tx/Rx

A0 A1 A2

Slave 2

To VCC or V

SS

Tx/Rx

A0 A1 A2

Slave 3

To VCC or V

SS

Tx/Rx

A0 A1 A2

Slave 8

To VCC or V

SS

V

CCVCC

SCL

Figure 1-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]
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24LLC02

2K-bit Serial EEPROM for Low Power

24LLC02

24LLC02

24LLC02

24LLC02

I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.

— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.

The I2C-bus interface supports the following communication protocols:

• Bus not busy : The SDA and the SCL lines remain High level when the bus is not active.

• Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High

level. All bus commands must be preceded by a start condition.

• Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains
High level. All bus operations must be completed by a stop condition (see Figure 1-7).

SCL

SDA

Start

Condition

Data or

ACK Valid

Data

Change

~

~

~

~

Stop

Condition

Figure 1-7. Data Transmission Sequence

• Data valid : Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.

• ACK (Acknowledge) : An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of
data (see Figure 1-8). But the slave does not send an ACK if an internal write cycle is still in progress.

In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition
to be issued by the master before returning to its stand-by mode.

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: [e-mail]
Tel:[phone] Http: www.ceramate.com.tw
Fax:[phone]

Page 6 of 19 Rev 1.2 May 6,2002

24LLC02

2K-bit Serial EEPROM for Low Power