Critikon Dinamap CO2 Modul Service manual

CO2 MODULE

INTRODUCTION

This area contains component information about the
Model 7345 CO2 Module. The CO2 Module monitors
the partial pressure of respiratory carbon dioxide. It
measures the absorption of infrared light by
respiratory gases and calculates endtidal carbon
dioxide (ETCO2) and inspired CO2. A sampling
pump allows monitoring of a mainstream or
sidestream sample of airway gases. Respiration
rate is calculated by measuring the time intervals
between peaks of the CO2 waveform. The displayed
rate is the result of averaging the inverse of the 8
most recently detected time intervals.

The CO2 Module provides automatic compensation
for the effect of barometric pressure on the CO2
reading, user-selectable compensation for the
presence of more than 60% oxygen and the
presence of more than 50% nitrous oxide, and the
ability to modify the detection algorithm to
compensate for artifact-induced waveforms.

PHYSICAL
DESCRIPTION

The CO2 Module is shown in FO-7B. The Module
contains a front panel with one patient connector and
sampling pump inlet and outlet, a flex PWA, an OEM
PWA, and a digital/power supply PWA. The flex PWA
provides power and signal connections from the
OEM PWA to the front panel sensor connector.

FUNCTIONAL
PRINCIPLES OF
OPERATION

Isolated Circuits

A functional block diagram of the CO2 Module is
shown in FO-7A. The diagram is divided into
isolated circuitry and non-isolated circuitry. The
isolated circuitry includes the CO2 sensor, the flex
PWA, and the OEM PWA. The isolated (ISO)
interface and push-pull transformer isolate this
circuitry from the non-isolated core logic. The core
logic provides communication between the system
host and CO2 Module through the PNet synchronous
serial interface. It also controls data acquisition and
data processing functions for the CO2 monitoring
channel.

Isolated circuits are shown in the top half of FO-7A.
The sampling pump receives power from the OEM
PWA through the front panel connector. Power from
the Module is applied to an infrared (IR) light emitter
in the CO2 sensor. The signal from an IR receptor in
the CO2 sensor is received through the front panel
connector and is connected to the OEM PWA via the
flex PWA.

Non-Isolated Circuits

The isolated interface provides an isolated
asynchronous serial communication channel
between the core logic and the OEM PWA. The
isolated power block consisting of isolated +12V,
+5V, and two -12V power supplies provides isolated
power to the OEM PWA and the sensor connected
circuitry.

Non-isolated circuits are shown in the bottom half of

FO-7A. Functional blocks include the PNet interface,

pulse width modulator (PWM) and power switcher,
isolated power control, reset/failsafe, 68302 CPU,
128Kx8 data memory, 128Kx8 program memory, the
model and serial number EEPROM, and logic
analyzer/test interface.

Power (+12V and +5V), is received through J1. The
+12V is applied to the PWM and power switcher that
powers the isolated circuitry. ISO power control

limits the PWM power-on until after the CPU is reset
and shuts down the PWM if a failsafe condition
occurs.

The Module will not be damaged when plugged into
a live slot. Core logic power inputs to a Module are
limited to a peak inrush current during hot-plugging.
Within 2 seconds the Module responds to
identification and wakes up in a minimized power
state until registered with the system.

The PNet interface allows asynchronous and
synchronous data transfer between the core logic
and the external devices. Synchronous operation is
always used in MPS systems. Asynchronous
operation is for test and development only. The
reset/failsafe logic provides power-on reset,
processor reset and halt, and failsafe if a problem
occurs with the microprocessor. The
microprocessor controls and transfers data within
the core logic. The program memory is a FLASH
device that can be loaded with program information
from the PNET interface or the logic analyzer
interface. Data memory temporarily stores status
and monitoring data for processing.

COMPONENT
PRINCIPLES OF
OPERATION

Schematic diagram SC315-446 is provided. The

first sheet of the schematic shows an overall block

diagram of the CO2 digital PWA.

CO2 Front End

The EMI filtering at the CO2 front end connector is
provided in a flex PWA (313-103) which contains a
common mode ferrite core and 100 pF bypass
capacitors on each signal pin of J2. The flex PWA is
also shielded. Signals are sent and received
through front end connector J2 with the following pin­out:

PIN NAME PIN NAME

1 SRC+ 11 EEDIN
2 SRC- 12 SPANSW
3 EECS 13 SRC_SHEILD
4 REF_IN 14 ZERO_SW
5 CASE_HTR 15 CASE_THRM
6 CO2_IN 16 DET_HTR
7 EESK 17 DET_THRM
8 HTR_RTN 18 -12CAPNO
9 EEDOUT 19 +12V
10 VDD 20 AGND

OEM PWA

Isolated Power

The OEM PWA is a self-contained CO2 detection
system. It has no serviceable parts, and must be
returned for repair.

The isolated power section provides patient isolation
from earth ground by isolating the power for the
patient connected circuitry. The isolated power
supply is shown on sheet 7 of the schematic.

Pulse Width Modulator (PWM) U102 drives the FET
power switchers Q101, Q102 for push-pull
transformer T101. The PWM senses primary current
via feedback resistor R112. The transformer has
one center-tapped primary side and two center
tapped secondary sides with nominal output
voltages of 6.1V and 15.9V.

Short-circuit protection for the isolated power
supplies is provided by the pulse-to-pulse current
limit feature of the PWM. Resistor R112 senses the
current through power switchers Q101 and Q102,
R116 and C122 filter out the switching spikes in the
voltage across R112, and resistors R114 and R115
set the current limit value of the PWM. The PWM will
function normally once the short is removed.

The PWM is synchronized to the Core Logic clock
(200 KHz) by TIMER2 output from the CPU.
Removing R143 allows the PWM to free run
asynchronously at approximately 100KHz.

The output of the PWM is the logical OR of FS-1 and
ISO_PS_ON-0. During power-on, ISO_PS_ON-0
remains pulled up until the CPU comes out of the
reset state. During failsafe conditions, FS-1 is
asserted, and the ISO_PS is shut down.

The 6.1V from the secondary of push-pull
transformer T101 is bridge rectified by CR101 and
CR102 to give approximately +5.3Vdc. This voltage
is then regulated using U101a and controlled power
FET Q109 to give +5Vdc (ISO_+5V). Op-amp U101
gets a precision reference of +5V from REF02 U105.

The 15.9V from the secondary of isolation
transformer T101 is bridge rectified by CR103 and
CR104 to give approximately+15Vdc, and CR105
and CR106 to give approximately -15 Vdc. The
+15Vdc is regulated by op-amp U104a and
controlled power FET Q105 to give regulated +12Vdc
(ISO_+12V). The +12V regulator gets a precision
reference of +5V from REF02 U105. The -15Vdc is
regulated by op-amp U104b and controlled power
FET Q104 to give regulated -12Vdc (ISO_-12V1). A
second, independent, low power -12V output (ISO_­12V2) is implemented with regulator U106.

Isolated Interface

Op-amp U104b used in the -12Vdc regulator gets a
non-inverting input from instrumentation amplifier
U103, which scales the difference in voltage
between the +12V and -12V outputs to a 4.9V
nominal output. Window comparators U112a and
U112b generate POWER_GOOD when the output of
U103 is 4.9V ±2%. POWER_GOOD from U112 is
sent back to the Core Logic CPU via optocoupler
U110. If the output from U103 falls out of the 4.9V
±2% range, POWER_GOOD goes false and signals
the Core logic CPU to shut down the power supply.

As shown on sheet 7 of the schematic, opto­couplers U107 and U108 provide a full duplex,
isolated serial channel between the non-isolated
core logic and the isolated circuitry as ISO_DATA_IN
and ISO_DATA_OUT. Q107 and Q108 buffer the
signal to the opto-couplers. U110 couples the
POWER_GOOD signal across the isolated interface.

Core Logic

The core logic is shown on sheets 2 through 6 of the
schematic. The core logic provides communication
between the system host and Module through the
PNet synchronous serial interface. It also controls
data acquisition and data processing functions for
the CO2 sensor. The Module is an 8-bit version of
the core logic with one 128Kx8 RAM and 128Kx8
ROM device. The microprocessor runs at 9.869
MHz.

PNet Interface

The PNet interface, shown on sheet 2 of the
schematic, provides the following functions:

• RS485 drivers (U7 and U8) for serial data and
clock,

• Module select and presence detection (U2),

• Module synchronization.

Core signals are received on PNet connector J1
(sheet 1) with the following pin-out:

PIN NAME PIN NAME

1A,1B +5V 6B M_SELECT
2A DATA+ 7A M_PRESENT
2B DATA- 7B TXOC-0
3A,3B +3.3V 8A M_SYNC-0
4A CLK+ 8B -12V
4B CLK- 10A,10B +12V
5A,5B GROUND 1,2 GROUND
6A M_RESET

The CO2 Module is designed to be inserted and
removed (‘hot-plugged’) from powered systems.
Ground pins 1 and 2 are longer than the other
connector pins, thus they make first and break last to
protect the circuitry. This is partially because of
protective impedance located on the system
backplane, in series with the modules +5V and +12V
power. Also series impedance on PNet control lines
limits inrush and protects logic devices from
excessive currents during a hot-plug power up.

The PNet protocol defines two modes of operation:
synchronous and asynchronous. The normal mode
of operation is synchronous, with half duplex
transmitted and received data on differential signals
DATA+ and DATA-. As shown on sheet 2 of the
schematic, the device transmitting the serial data
also generates differential clock signals CLK+ and
CLK-. Transceiver direction for data and clock are
controlled by the 68302 processor-generated
TX_EN-0 (low true transmit enable) signal through
U2. In the synchronous mode, both data and clock
transceivers U7 and U8 are set to receive (i.e.,
transmit disabled) when fail-safe signal FS-0 is
asserted.

The alternate serial mode, full duplex asynchronous,
is entered by asserting processor generated control
bit ASYCH_EN. This mode transmits data onto the
differential signals CLK+ and CLK-, and receives
data from the differential signals DATA+ and DATA-.
The transmitter in the Module is disabled unless the
Module has been commanded to transmit per the
PNet protocol. The Module transmitter is
immediately disabled after the last character of a
transmission has been sent.

The Module select input (M_SELECT, hi true)
instructs the Module to respond to identification
requests. When both M_SELECT input and
M_RESET input (hi true) are asserted, the Module
performs a hardware reset.

The Module present output, M_PRESENT is
connected to M_SELECT through diode CR1 to allow
a means of determining if the Module is plugged into
an instrument. When M_SELECT is asserted
(pulled hi) M_PRESENT is hi true.

Module transmitter open collector signal TXOC-0
from Q1 signifies the Module transmitter is enabled.
Serial data is then transmitted in the synchronous
mode.

M_SYNC is used for timing of shorter latency periods
than supported by the serial data protocols. A
Module only asserts M_SYNC when enabled by the
host.

Reset Logic

The reset logic is shown on sheet 3 of the
schematic. Reset logic U9 generates a power-on­reset when power is applied. RESET-0 AND HALT-0
signals remain low for minimum of 130 msec after
all logic voltages are in specification.

External reset, processor reset, and halt signals are
low for minimum of 24 clocks when external reset
asserted. Power monitoring, processor reset, and
halt signals are low if logic voltages drop below
specification. They remain low for minimum of 130
msec after logic voltages return to the specified
range.

The reset circuit consisting of U6b and U6d provides
open drain outputs to the processor bi-directional
reset and halt signals.

Fail-Safe Logic

Fail-safe latch (U6a and U6c) ensures that the
Module enters a safe state if the processor fails to
operate correctly. The latch is set by a low true output
from the processor watchdog timer (WDOG-0). The
data transmitter is disabled, isolated power is shut
down, and the Module remains in a safe state until
the latch is cleared by a power on or external reset.

Microprocessor

The core logic design is based around the 68302
microprocessor (U10) shown on sheet 4 of the
schematic. The 68302 combines a 68000 core with
a three channel communication processor, and
system integration circuits.